DDR3L SDRAM

MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM
(Die Rev :E) data sheet specifications when running in
1.5V compatible mode.

Features

• V

DD

 = V

DDQ

 = 1.35V (1.283–1.45V)

• Backward compatible to V

DD

 = V

DDQ

 = 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe
• 8

n

-bit prefetch architecture

• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T

C 

of 105°C

– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
– 16ms, 8192-cycle refresh at >95°C to 105°C

• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration

Options

Marking

• Configuration

 

– 1 Gig x 4

1G4

– 512 Meg x 8

512M8

– 256 Meg x 16

256M16

• FBGA package (Pb-free) – x4, x8

 

– 78-ball (9mm x 10.5mm) Rev. E

RH

– 78-ball (7.5mm x 10.6mm) Rev. N

RG

– 78-ball (8mm x 10.5mm) Rev. P

DA

• FBGA package (Pb-free) – x16

 

– 96-ball (9mm x 14mm) Rev. E

HA

– 96-ball (7.5mm x 13.5mm) Rev. N

LY

– 96-ball (8mm x 14mm) Rev. P

TW

• Timing – cycle time

 

– 938ps @ CL = 14 (DDR3-2133)

-093

– 1.07ns @ CL = 13 (DDR3-1866)

-107

– 1.25ns @ CL = 11 (DDR3-1600)

-125

• Operating temperature

– Commercial (0°C 

”

 T

C

 

”

 +95°C)

None

– Industrial (–40°C 

”

 T

C

 

”

 +95°C)

IT

– Automotive (–40°C 

”

 T

C

 

”

 +105°C)

AT

• Revision

:E/:N/:P

Table 1: Key Timing Parameters

Speed Grade

Data Rate (MT/s)

Target 

t

RCD-

t

RP-CL

t

RCD (ns)

t

RP (ns)

CL (ns)

-093

 1, 2

2133

14-14-14

13.09

13.09

13.09

-107

 1

1866

13-13-13

13.91

13.91

13.91

-125

1600

11-11-11

13.75

13.75

13.75

Notes:

1. Backward compatible to 1600, CL = 11 (-125).
2. Backward compatible to 1866, CL = 13 (-107).

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

1

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter

1 Gig x 4

512 Meg x 8

256 Meg x 16

Configuration

128 Meg x 4 x 8 banks

64 Meg x 8 x 8 banks

32 Meg x 16 x 8 banks

Refresh count

8K

8K

8K

Row address

64K (A[15:0])

64K (A[15:0])

32K (A[14:0])

Bank address

8 (BA[2:0])

8 (BA[2:0])

8 (BA[2:0])

Column address

2K (A[11, 9:0])

1K (A[9:0])

1K (A[9:0])

Page size

1KB

1KB

2KB

Figure 1: DDR3L Part Numbers

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Note:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: 
http://www.micron.com.

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Contents

Important Notes and Warnings  .......................................................................................................................  11
State Diagram  ................................................................................................................................................  12
Functional Description ...................................................................................................................................  13

Industrial Temperature  ...............................................................................................................................  13
Automotive Temperature  ............................................................................................................................  13
General Notes  ............................................................................................................................................  14

Functional Block Diagrams  .............................................................................................................................  15
Ball Assignments and Descriptions  .................................................................................................................  17
Package Dimensions .......................................................................................................................................  23
Electrical Specifications  ..................................................................................................................................  29

Absolute Ratings .........................................................................................................................................  29
Input/Output Capacitance ..........................................................................................................................  30

Thermal Characteristics ..................................................................................................................................  31
Electrical Specifications – I

DD

 Specifications and Conditions ............................................................................  33

Electrical Characteristics – Operating I

DD

 Specifications  ..................................................................................  44

Electrical Specifications – DC and AC  ..............................................................................................................  49

DC Operating Conditions  ...........................................................................................................................  49
Input Operating Conditions  ........................................................................................................................  50
DDR3L 1.35V AC Overshoot/Undershoot Specification  ................................................................................  54
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals  ..............................................................  57
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals  .................................................................  59

ODT Characteristics  .......................................................................................................................................  60

1.35V ODT Resistors  ...................................................................................................................................  61
ODT Sensitivity  ..........................................................................................................................................  62
ODT Timing Definitions  .............................................................................................................................  62

Output Driver Impedance ...............................................................................................................................  66

34 Ohm Output Driver Impedance  ..............................................................................................................  67
DDR3L 34 Ohm Driver  ................................................................................................................................   68
DDR3L 34 Ohm Output Driver Sensitivity  ....................................................................................................  69
DDR3L Alternative 40 Ohm Driver ...............................................................................................................  70
DDR3L 40 Ohm Output Driver Sensitivity  ....................................................................................................  70

Output Characteristics and Operating Conditions ............................................................................................  72

Reference Output Load  ...............................................................................................................................  75
Slew Rate Definitions for Single-Ended Output Signals .................................................................................  75
Slew Rate Definitions for Differential Output Signals ....................................................................................  77

Speed Bin Tables  ............................................................................................................................................  78
Electrical Characteristics and AC Operating Conditions  ...................................................................................  83
Command and Address Setup, Hold, and Derating .......................................................................................... 103
Data Setup, Hold, and Derating ...................................................................................................................... 110
Commands – Truth Tables  ............................................................................................................................. 118
Commands  ................................................................................................................................................... 121

DESELECT  ................................................................................................................................................ 121
NO OPERATION  ........................................................................................................................................ 121
ZQ CALIBRATION LONG  ........................................................................................................................... 121
ZQ CALIBRATION SHORT .......................................................................................................................... 121
ACTIVATE  ................................................................................................................................................. 121
READ  ........................................................................................................................................................ 121
WRITE  ...................................................................................................................................................... 122
PRECHARGE  ............................................................................................................................................. 123
REFRESH  .................................................................................................................................................. 123

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

3

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

SELF REFRESH .......................................................................................................................................... 124
DLL Disable Mode ..................................................................................................................................... 125

Input Clock Frequency Change  ...................................................................................................................... 129
Write Leveling  ............................................................................................................................................... 131

Write Leveling Procedure  ........................................................................................................................... 133
Write Leveling Mode Exit Procedure  ........................................................................................................... 135

Initialization  ................................................................................................................................................. 136
Voltage Initialization/Change  ........................................................................................................................ 138

V

DD

 Voltage Switching  ............................................................................................................................... 139

Mode Registers .............................................................................................................................................. 140
Mode Register 0 (MR0) ................................................................................................................................... 141

Burst Length  ............................................................................................................................................. 141
Burst Type  ................................................................................................................................................. 142
DLL RESET ................................................................................................................................................ 143
Write Recovery  .......................................................................................................................................... 144
Precharge Power-Down (Precharge PD)  ...................................................................................................... 144
CAS Latency (CL) ....................................................................................................................................... 144

Mode Register 1 (MR1) ................................................................................................................................... 146

DLL Enable/DLL Disable  ........................................................................................................................... 146
Output Drive Strength  ............................................................................................................................... 147
OUTPUT ENABLE/DISABLE  ...................................................................................................................... 147
TDQS Enable ............................................................................................................................................. 147
On-Die Termination  .................................................................................................................................. 148
WRITE LEVELING  ..................................................................................................................................... 148
POSTED CAS ADDITIVE Latency ................................................................................................................ 148

Mode Register 2 (MR2) ................................................................................................................................... 149

CAS Write Latency (CWL) ........................................................................................................................... 150
AUTO SELF REFRESH (ASR) ....................................................................................................................... 150
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 150
SRT vs. ASR  ............................................................................................................................................... 151
DYNAMIC ODT  ......................................................................................................................................... 151

Mode Register 3 (MR3) ................................................................................................................................... 151

MULTIPURPOSE REGISTER (MPR)  ............................................................................................................ 152
MPR Functional Description ...................................................................................................................... 153
MPR Register Address Definitions and Bursting Order ................................................................................. 154
MPR Read Predefined Pattern  .................................................................................................................... 159

MODE REGISTER SET (MRS) Command  ........................................................................................................ 159
ZQ CALIBRATION Operation  ......................................................................................................................... 160
ACTIVATE Operation  ..................................................................................................................................... 161
READ Operation ............................................................................................................................................ 163
WRITE Operation  .......................................................................................................................................... 174

DQ Input Timing  ....................................................................................................................................... 182

PRECHARGE Operation  ................................................................................................................................. 184
SELF REFRESH Operation .............................................................................................................................. 184
Extended Temperature Usage  ........................................................................................................................ 186
Power-Down Mode ........................................................................................................................................ 187
RESET Operation ........................................................................................................................................... 195
On-Die Termination (ODT) ............................................................................................................................ 197

Functional Representation of ODT  ............................................................................................................. 197
Nominal ODT ............................................................................................................................................ 197

Dynamic ODT  ............................................................................................................................................... 199

Dynamic ODT Special Use Case  ................................................................................................................. 199

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Functional Description .............................................................................................................................. 199

Synchronous ODT Mode ................................................................................................................................ 205

ODT Latency and Posted ODT .................................................................................................................... 205
Timing Parameters  .................................................................................................................................... 205
ODT Off During READs .............................................................................................................................. 208

Asynchronous ODT Mode .............................................................................................................................. 210

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 212

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)  ........................................................ 214

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)  ...................................................... 216

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

5

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

List of Figures

Figure 1:   DDR3L Part Numbers  ........................................................................................................................  2
Figure 2:   Simplified State Diagram  .................................................................................................................  12
Figure 3:   1 Gig x 4 Functional Block Diagram  ..................................................................................................  15
Figure 4:   512 Meg x 8 Functional Block Diagram  .............................................................................................  16
Figure 5:   256 Meg x 16 Functional Block Diagram  ...........................................................................................  16
Figure 6:   78-Ball FBGA – x4, x8 (Top View)  ......................................................................................................  17
Figure 7:   96-Ball FBGA – x16 (Top View)  .........................................................................................................  18
Figure 8:   78-Ball FBGA – x4, x8 (RH)  ...............................................................................................................  23
Figure 9:   78-Ball FBGA – x4, x8 (RG)  ...............................................................................................................  24
Figure 10:   78-Ball FBGA – x4, x8 (DA)  .............................................................................................................  25
Figure 11:   96-Ball FBGA – x16 (HA) .................................................................................................................  26
Figure 12:   96-Ball FBGA – x16 (LY) ..................................................................................................................  27
Figure 13:   96-Ball FBGA – x16 (TW) ................................................................................................................  28
Figure 14:   Thermal Measurement Point  .........................................................................................................  31
Figure 15:   DDR3L 1.35V Input Signal ..............................................................................................................  53
Figure 16:   Overshoot  .....................................................................................................................................  54
Figure 17:   Undershoot ...................................................................................................................................  55
Figure 18:   V

IX

 for Differential Signals  ..............................................................................................................  55

Figure 19:   Single-Ended Requirements for Differential Signals  ........................................................................  55
Figure 20:   Definition of Differential AC-Swing and 

t

DVAC ...............................................................................  56

Figure 21:   Nominal Slew Rate Definition for Single-Ended Input Signals ..........................................................  58
Figure 22:   DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# ..............  59
Figure 23:   ODT Levels and I-V Characteristics  ................................................................................................  60
Figure 24:   ODT Timing Reference Load  ..........................................................................................................  63
Figure 25:   

t

AON and 

t

AOF Definitions  ............................................................................................................  64

Figure 26:   

t

AONPD and 

t

AOFPD Definitions  ...................................................................................................  64

Figure 27:   

t

ADC Definition .............................................................................................................................  65

Figure 28:   Output Driver ................................................................................................................................   66
Figure 29:   DQ Output Signal  ..........................................................................................................................  73
Figure 30:   Differential Output Signal  ..............................................................................................................  74
Figure 31:   Reference Output Load for AC Timing and Output Slew Rate  ...........................................................  75
Figure 32:   Nominal Slew Rate Definition for Single-Ended Output Signals  .......................................................  76
Figure 33:   Nominal Differential Output Slew Rate Definition for DQS, DQS# ....................................................  77
Figure 34:   Nominal Slew Rate and 

t

VAC for 

t

IS (Command and Address – Clock)  ............................................. 106

Figure 35:   Nominal Slew Rate for 

t

IH (Command and Address – Clock) ........................................................... 107

Figure 36:   Tangent Line for 

t

IS (Command and Address – Clock)  .................................................................... 108

Figure 37:   Tangent Line for 

t

IH (Command and Address – Clock) .................................................................... 109

Figure 38:   Nominal Slew Rate and 

t

VAC for 

t

DS (DQ – Strobe) ......................................................................... 114

Figure 39:   Nominal Slew Rate for 

t

DH (DQ – Strobe)  ...................................................................................... 115

Figure 40:   Tangent Line for 

t

DS (DQ – Strobe)  ................................................................................................ 116

Figure 41:   Tangent Line for 

t

DH (DQ – Strobe)  ............................................................................................... 117

Figure 42:   Refresh Mode  ............................................................................................................................... 124
Figure 43:   DLL Enable Mode to DLL Disable Mode  ........................................................................................ 126
Figure 44:   DLL Disable Mode to DLL Enable Mode  ........................................................................................ 127
Figure 45:   DLL Disable 

t

DQSCK  .................................................................................................................... 128

Figure 46:   Change Frequency During Precharge Power-Down  ........................................................................ 130
Figure 47:   Write Leveling Concept ................................................................................................................. 131
Figure 48:   Write Leveling Sequence  ............................................................................................................... 134
Figure 49:   Write Leveling Exit Procedure  ....................................................................................................... 135
Figure 50:   Initialization Sequence  ................................................................................................................. 137

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

6

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 51:   V

DD

 Voltage Switching  .................................................................................................................. 139

Figure 52:   MRS to MRS Command Timing (

t

MRD) ......................................................................................... 140

Figure 53:   MRS to nonMRS Command Timing (

t

MOD)  .................................................................................. 141

Figure 54:   Mode Register 0 (MR0) Definitions  ................................................................................................ 142
Figure 55:   READ Latency  .............................................................................................................................. 145
Figure 56:   Mode Register 1 (MR1) Definition  ................................................................................................. 146
Figure 57:   READ Latency (AL = 5, CL = 6)  ....................................................................................................... 149
Figure 58:   Mode Register 2 (MR2) Definition  ................................................................................................. 149
Figure 59:   CAS Write Latency  ........................................................................................................................ 150
Figure 60:   Mode Register 3 (MR3) Definition  ................................................................................................. 152
Figure 61:   Multipurpose Register (MPR) Block Diagram  ................................................................................. 153
Figure 62:   MPR System Read Calibration with BL8: Fixed Burst Order Single Readout  ..................................... 155
Figure 63:   MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 156
Figure 64:   MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble  .................................... 157
Figure 65:   MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble  .................................... 158
Figure 66:   ZQ CALIBRATION Timing (ZQCL and ZQCS)  ................................................................................. 160
Figure 67:   Example: Meeting 

t

RRD (MIN) and 

t

RCD (MIN)  ............................................................................. 161

Figure 68:   Example: 

t

FAW ............................................................................................................................. 162

Figure 69:   READ Latency  .............................................................................................................................. 163
Figure 70:   Consecutive READ Bursts (BL8)  .................................................................................................... 165
Figure 71:   Consecutive READ Bursts (BC4)  .................................................................................................... 165
Figure 72:   Nonconsecutive READ Bursts  ....................................................................................................... 166
Figure 73:   READ (BL8) to WRITE (BL8)  .......................................................................................................... 166
Figure 74:   READ (BC4) to WRITE (BC4) OTF  .................................................................................................. 167
Figure 75:   READ to PRECHARGE (BL8) .......................................................................................................... 167
Figure 76:   READ to PRECHARGE (BC4)  ......................................................................................................... 168
Figure 77:   READ to PRECHARGE (AL = 5, CL = 6)  ........................................................................................... 168
Figure 78:   READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 168
Figure 79:   Data Output Timing – 

t

DQSQ and Data Valid Window   .................................................................... 170

Figure 80:   Data Strobe Timing – READs  ......................................................................................................... 171
Figure 81:   Method for Calculating 

t

LZ and 

t

HZ ............................................................................................... 172

Figure 82:   

t

RPRE Timing  ............................................................................................................................... 172

Figure 83:   

t

RPST Timing  ............................................................................................................................... 173

Figure 84:   

t

WPRE Timing  .............................................................................................................................. 175

Figure 85:   

t

WPST Timing  .............................................................................................................................. 175

Figure 86:   WRITE Burst  ................................................................................................................................ 176
Figure 87:   Consecutive WRITE (BL8) to WRITE (BL8)   ..................................................................................... 177
Figure 88:   Consecutive WRITE (BC4) to WRITE (BC4) via OTF   ........................................................................ 177
Figure 89:   Nonconsecutive WRITE to WRITE   ................................................................................................. 178
Figure 90:   WRITE (BL8) to READ (BL8)  .......................................................................................................... 178
Figure 91:   WRITE to READ (BC4 Mode Register Setting)  ................................................................................. 179
Figure 92:   WRITE (BC4 OTF) to READ (BC4 OTF)  ........................................................................................... 180
Figure 93:   WRITE (BL8) to PRECHARGE  ........................................................................................................ 181
Figure 94:   WRITE (BC4 Mode Register Setting) to PRECHARGE  ...................................................................... 181
Figure 95:   WRITE (BC4 OTF) to PRECHARGE  ................................................................................................ 182
Figure 96:   Data Input Timing  ........................................................................................................................ 183
Figure 97:   Self Refresh Entry/Exit Timing  ...................................................................................................... 185
Figure 98:   Active Power-Down Entry and Exit  ................................................................................................ 189
Figure 99:   Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 189
Figure 100:   Precharge Power-Down (Slow-Exit Mode) Entry and Exit  .............................................................. 190
Figure 101:   Power-Down Entry After READ or READ with Auto Precharge (RDAP)  ........................................... 190
Figure 102:   Power-Down Entry After WRITE  .................................................................................................. 191

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

7

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 103:   Power-Down Entry After WRITE with Auto Precharge (WRAP)  ...................................................... 191
Figure 104:   REFRESH to Power-Down Entry  .................................................................................................. 192
Figure 105:   ACTIVATE to Power-Down Entry  ................................................................................................. 192
Figure 106:   PRECHARGE to Power-Down Entry  ............................................................................................. 193
Figure 107:   MRS Command to Power-Down Entry  ......................................................................................... 193
Figure 108:   Power-Down Exit to Refresh to Power-Down Entry  ....................................................................... 194
Figure 109:   RESET Sequence ......................................................................................................................... 196
Figure 110:   On-Die Termination  ................................................................................................................... 197
Figure 111:   Dynamic ODT: ODT Asserted Before and After the WRITE, BC4  .................................................... 202
Figure 112:   Dynamic ODT: Without WRITE Command   .................................................................................. 202
Figure 113:   Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8  ............ 203
Figure 114:   Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 204
Figure 115:   Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 204
Figure 116:   Synchronous ODT  ...................................................................................................................... 206
Figure 117:   Synchronous ODT (BC4)  ............................................................................................................. 207
Figure 118:   ODT During READs  .................................................................................................................... 209
Figure 119:   Asynchronous ODT Timing with Fast ODT Transition  .................................................................. 211
Figure 120:   Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off ) Entry  ............ 213
Figure 121:   Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off ) Exit ............... 215
Figure 122:   Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 217
Figure 123:   Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping  ................... 217

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

8

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

List of Tables

Table 1:   Key Timing Parameters  .......................................................................................................................  1
Table 2:   Addressing  .........................................................................................................................................  2
Table 3:   78-Ball FBGA – x4, x8 Ball Descriptions  ..............................................................................................  19
Table 4:   96-Ball FBGA – x16 Ball Descriptions  .................................................................................................  21
Table 5:   Absolute Maximum Ratings  ..............................................................................................................  29
Table 6:   DDR3L Input/Output Capacitance  ....................................................................................................  30
Table 7:   Thermal Characteristics ....................................................................................................................  31
Table 8:   Thermal Impedance  .........................................................................................................................  32
Table 9:   Timing Parameters Used for I

DD

 Measurements – Clock Units  ............................................................  33

Table 10:   I

DD0

 Measurement Loop ..................................................................................................................  34

Table 11:   I

DD1

 Measurement Loop ..................................................................................................................  35

Table 12:   I

DD

 Measurement Conditions for Power-Down Currents ...................................................................  36

Table 13:   I

DD2N

 and I

DD3N

 Measurement Loop  ................................................................................................  37

Table 14:   I

DD2NT

 Measurement Loop  ..............................................................................................................  37

Table 15:   I

DD4R

 Measurement Loop  ................................................................................................................  38

Table 16:   I

DD4W

 Measurement Loop  ...............................................................................................................  39

Table 17:   I

DD5B

 Measurement Loop  ................................................................................................................  40

Table 18:   I

DD

 Measurement Conditions for I

DD6

, I

DD6ET

, and I

DD8

 ....................................................................  41

Table 19:   I

DD7

 Measurement Loop ..................................................................................................................  42

Table 20:   I

DD

 Maximum Limits Die Rev. E for 1.35/1.5V Operation ...................................................................  44

Table 21:   I

DD

 Maximum Limits Die Rev. N for 1.35V/1.5V Operation  ................................................................  45

Table 22:   I

DD

 Maximum Limits Die Rev. P for 1.35V/1.5V Operation .................................................................  47

Table 23:   DDR3L 1.35V DC Electrical Characteristics and Operating Conditions  ..............................................  49
Table 24:   DDR3L 1.35V DC Electrical Characteristics and Input Conditions  .....................................................  50
Table 25:   DDR3L 1.35V Input Switching Conditions – Command and Address  .................................................  51
Table 26:   DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) ..............................  52
Table 27:   DDR3L Control and Address Pins .....................................................................................................  54
Table 28:   DDR3L 1.35V Clock, Data, Strobe, and Mask Pins  .............................................................................  54
Table 29:   DDR3L 1.35V – Minimum Required Time 

t

DVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...

 56

Table 30:   Single-Ended Input Slew Rate Definition ..........................................................................................  57
Table 31:   DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................  59
Table 32:   On-Die Termination DC Electrical Characteristics ............................................................................  60
Table 33:   1.35V R

TT

 Effective Impedance  ........................................................................................................  61

Table 34:   ODT Sensitivity Definition  ..............................................................................................................  62
Table 35:   ODT Temperature and Voltage Sensitivity  ........................................................................................  62
Table 36:   ODT Timing Definitions ..................................................................................................................  63
Table 37:   DDR3L(1.35V) Reference Settings for ODT Timing Measurements  ....................................................  63
Table 38:   DDR3L 34 Ohm Driver Impedance Characteristics  ...........................................................................  67
Table 39:   DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations  ...........................................  68
Table 40:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.35V  .....................................  68

Table 41:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.45V  .....................................  68

Table 42:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.283  .....................................  69

Table 43:   DDR3L 34 Ohm Output Driver Sensitivity Definition  ........................................................................  69
Table 44:   DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity  ..................................................  69
Table 45:   DDR3L 40 Ohm Driver Impedance Characteristics  ...........................................................................  70
Table 46:   DDR3L 40 Ohm Output Driver Sensitivity Definition  ........................................................................  70
Table 47:   40 Ohm Output Driver Voltage and Temperature Sensitivity ..............................................................  71
Table 48:   DDR3L Single-Ended Output Driver Characteristics  .........................................................................  72
Table 49:   DDR3L Differential Output Driver Characteristics  ............................................................................  73
Table 50:   DDR3L Differential Output Driver Characteristics V

OX(AC)

 .................................................................  74

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

9

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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Table 51:   Single-Ended Output Slew Rate Definition  .......................................................................................  75
Table 52:   Differential Output Slew Rate Definition  ..........................................................................................  77
Table 53:   DDR3L-1066 Speed Bins ..................................................................................................................  78
Table 54:   DDR3L-1333 Speed Bins ..................................................................................................................  79
Table 55:   DDR3L-1600 Speed Bins ..................................................................................................................  80
Table 56:   DDR3L-1866 Speed Bins ..................................................................................................................  81
Table 57:   DDR3L-2133 Speed Bins ..................................................................................................................  82
Table 58:   Electrical Characteristics and AC Operating Conditions ....................................................................  83
Table 59:   Electrical Characteristics and AC Operating Conditions for Speed Extensions ....................................  93
Table 60:   DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based   ............... 103
Table 61:   DDR3L-800/1066 Derating Values 

t

IS/

t

IH – AC160/DC90-Based ....................................................... 104

Table 62:   DDR3L-800/1066/1333/1600 Derating Values for 

t

IS/

t

IH – AC135/DC90-Based  ................................ 104

Table 63:   DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based  ................................................ 104

Table 64:   DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL[AC]

) for Valid ADD/CMD Transition  . 105

Table 65:   DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based   ....................... 110
Table 66:   DDR3L Derating Values for 

t

DS/

t

DH – AC160/DC90-Based  .............................................................. 111

Table 67:   DDR3L Derating Values for 

t

DS/

t

DH – AC135/DC90-Based  .............................................................. 111

Table 68:   DDR3L Derating Values for 

t

DS/

t

DH – AC130/DC90-Based at 2V/ns ................................................. 112

Table 69:   DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL(AC)

) for Valid DQ Transition  ............. 113

Table 70:   Truth Table – Command ................................................................................................................. 118
Table 71:   Truth Table – CKE  .......................................................................................................................... 120
Table 72:   READ Command Summary  ............................................................................................................ 122
Table 73:   WRITE Command Summary  .......................................................................................................... 122
Table 74:   READ Electrical Characteristics, DLL Disable Mode ......................................................................... 128
Table 75:   Write Leveling Matrix  ..................................................................................................................... 132
Table 76:   Burst Order .................................................................................................................................... 143
Table 77:   MPR Functional Description of MR3 Bits  ........................................................................................ 153
Table 78:   MPR Readouts and Burst Order Bit Mapping  ................................................................................... 154
Table 79:   Self Refresh Temperature and Auto Self Refresh Description  ............................................................ 186
Table 80:   Self Refresh Mode Summary  ........................................................................................................... 186
Table 81:   Command to Power-Down Entry Parameters  .................................................................................. 187
Table 82:   Power-Down Modes ....................................................................................................................... 188
Table 83:   Truth Table – ODT (Nominal)  ......................................................................................................... 198
Table 84:   ODT Parameters  ............................................................................................................................ 198
Table 85:   Write Leveling with Dynamic ODT Special Case  .............................................................................. 199
Table 86:   Dynamic ODT Specific Parameters  ................................................................................................. 200
Table 87:   Mode Registers for R

TT,nom

 ............................................................................................................. 200

Table 88:   Mode Registers for R

TT(WR)

 ............................................................................................................. 201

Table 89:   Timing Diagrams for Dynamic ODT ................................................................................................ 201
Table 90:   Synchronous ODT Parameters ........................................................................................................ 206
Table 91:   Asynchronous ODT Timing Parameters for All Speed Bins  ............................................................... 211
Table 92:   ODT Parameters for Power-Down (DLL Off ) Entry and Exit Transition Period  ................................... 213

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

10

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.

Automotive Applications.

 Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications.

 Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.

Customer Responsibility.

 Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.

Limited Warranty.

 In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

4Gb: x4, x8, x16 DDR3L SDRAM
Important Notes and Warnings

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

11

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION

Bank

active

Reading

Writing

Activating

Refreshing

Self

refresh

Idle

Active 

power-

down

ZQ

calibration

From any
state

Power
applied

Reset 

procedure

  Power 

on

Initial-

ization

MRS, MPR, 

write

leveling

Precharge

power-

down

Writing

Reading

Automatic
sequence

Command
sequence

Precharging

READ

READ

READ

READ AP

READ AP

READ AP

PRE, PREA

PRE,  PREA

PRE,  PREA

WRITE

WRITE

CKE L

CKE L

CKE L

WRITE

WRITE AP

WRITE AP

WRITE AP

PDE

PDE

PDX

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE

PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8 
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry

4Gb: x4, x8, x16 DDR3L SDRAM

State Diagram

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

12

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8

n

-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8

n

-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding 

n

-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-
mand, and address signals are registered at every positive edge of CK. Input data is reg-
istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-
erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad-
dress bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row pre-
charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when T

C 

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T

C 

is < 0°C or

>95°C.

Automotive Temperature

The Automotive temperature (AT) device requires that the case temperature not exceed
–40°C or 105°C. Micron specification requires the refresh rate to 4X when T

C 

exceeds

95°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T

C 

is < 0°C or

>95°C.

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.

• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[

n

:0]

. For example, 

1Gb: 

n

 = 12 (x16); 1Gb: 

n

 = 13 (x4,

x8); 2Gb: 

n

 = 13 (x16) and 2Gb: 

n

 = 14 (x4, x8); 4Gb: 

n

 = 14 (x16); and 4Gb: 

n

 = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1k

ȍ

* resistor.

– Connect UDQS# to V

DD

 via 1k

ȍ

* resistor.

– Connect UDM to V

DD

 via 1k

ȍ

* resistor.

– Connect DQ[15:8] individually to either V

SS

, V

DD

, or V

REF

 via 1k

ȍ

 resistors,* or float

DQ[15:8].

*If ODT is used, 1k

ȍ

 resistor should be changed to 4x that of the selected ODT.

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

14

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© 2017 Micron Technology, Inc. All rights reserved.

Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.

Figure 3: 1 Gig x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

16

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

11

Command 

decode

A[15:0]
BA[2:0]

16

Address
register

19

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(65,536 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank

control

logic

19

Bank 1

Bank 2

Bank 3

16

8

3

3

Refresh
counter

4

32

32

32

DQS, DQS#

Columns 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To pull-up/pull-down

networks

READ 

drivers

DQ[3:0]

READ

FIFO

and

data

MUX

Data

4

3

Bank 1

Bank 2

Bank 3

DM

DM

CK, CK#

DQS, DQS#

ZQ CAL

CS#

ZQ

RZQ

CK, CK#

RAS#

WE#

CAS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

OTF

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

 WRITE 

drivers

and 

input

logic

ODT

control

V

SSQ

A12

OTF

BC4

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 4: 512 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

16

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

10

Command 

decode

A[15:0]
BA[2:0]

16

19

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(65,536  x 128 x 64)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank 

control

logic

19

Bank 1

Bank 2

Bank 3

16

7

3

3

Refresh
counter

8

64

64

64

DQS, DQS#

Columns 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read 

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

8

3

Bank 1

Bank 2

Bank 3

DM/TDQS
(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

ZQ

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT(WR)

R

TT,nom

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

BC4 (burst chop)

BC4

BC4

Write 

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128
x64)

ODT

control

Address
register

A12

V

SSQ

OTF

OTF

Figure 5: 256 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

13

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

10

Command 

decode

A[14:0]
BA[2:0]

15

Address
register

18

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

18

Bank 1

Bank 2

Bank 3

15

7

3

3

Refresh
counter

16

128

128

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ 

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

16

BC4 (burst chop)

3

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

ZQ

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

BC4

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

 WRITE 

drivers

and

input

logic

ODT

control

V

SSQ

A12

OTF

OTF

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

16

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1

2

3

4

6

7

8

9

5

V

SS

V

SS

V

DDQ

V

SSQ

V

REFDQ

NC

ODT

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SSQ

DQ2

NF, DQ6

V

DDQ

V

SS

V

DD

CS#

BA0

A3

A5

A7

RESET#

NC

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A0

A2

A9

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

V

DD

NF, DQ7

CK

CK#

A10/AP

A15

A12/BC#

A1

A11

A14

V

DD

V

DDQ

V

SSQ

V

SSQ

V

DDQ

NC

CKE

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SSQ

DQ3

V

SS

NF, DQ5

V

SS

V

DD

ZQ

V

REFCA

BA1

A4

A6

A8

A

B

C

D

E

F

G

H

J

K

L

M

N

Notes:

1. Ball descriptions listed in Table 3 (page 19) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

17

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 7: 96-Ball FBGA – x16 (Top View)

1

2

3

4

6

7

8

9

5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

SS

V

DDQ

V

SSQ

V

REFDQ

NC

ODT

NC

V

SS

V

DD

V

SS

V

DD

V

SS

DQ13

V

DD

DQ11

V

DDQ

V

SSQ

DQ2

DQ6

V

DDQ

V

SS

V

DD

CS#

BA0

A3

A5

A7

RESET#

DQ15

V

SS

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

A0

A2

A9

A13

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

V

DD

DQ7

CK

CK#

A10/AP

NC

A12/BC#

A1

A11

A14

V

DDQ

DQ14

DQ10

V

SSQ

V

SSQ

DQ3

V

SS

DQ5

V

SS

V

DD

ZQ

V

REFCA

BA1

A4

A6

A8

V

SS

V

SSQ

V

DDQ

V

DD

V

DDQ

V

SSQ

V

SSQ

V

DDQ

NC

CKE

NC

V

SS

V

DD

V

SS

V

DD

V

SS

Notes:

1. Ball descriptions listed in Table 4 (page 21) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol

Type

Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input

Address inputs:

 Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 118).

BA[2:0]

Input

Bank address inputs:

 BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V

REFCA

.

CK, CK#

Input

Clock:

 CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock enable:

 CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/
disabled is dependent upon the DDR3 SDRAM configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-
bled during SELF REFRESH. CKE is referenced to V

REFCA

.

CS#

Input

Chip select:

 CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V

REFCA

.

DM

Input

Input data mask:

 DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT

Input

On-die termination:

 ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

.

RAS#, CAS#, WE#

Input

Command inputs:

 RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

.

RESET#

Input

Reset:

 RESET# is an active LOW CMOS input referenced to V

SS

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 

ุ

 0.8 × V

DD

 and

DC LOW 

ื

 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol

Type

Description

DQ[3:0]

I/O

Data input/output:

 Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to V

REFDQ

.

DQ[7:0]

I/O

Data input/output:

 Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to V

REFDQ

.

DQS, DQS#

I/O

Data strobe:

 Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS#

Output

Termination data strobe: 

Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.

V

DD

Supply

Power supply:

 1.5V ±0.075V.

V

DDQ

Supply

DQ power supply:

 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

V

REFCA

Supply

Reference voltage for control, command, and address:

 V

REFCA

 must be

maintained at all times (including self refresh) for proper device operation.

V

REFDQ

Supply

Reference voltage for data:

 V

REFDQ

 must be maintained at all times (excluding self

refresh) for proper device operation.

V

SS

Supply

Ground.

V

SSQ

Supply

DQ ground:

 Isolated on the device for improved noise immunity.

ZQ

Reference

External reference ball for output drive calibration:

 This ball is tied to an

external 240

˖

 resistor (RZQ), which is tied to V

SSQ

.

NC

–

No connect:

 These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF

–

No function:

 When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

20

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol

Type

Description

A[14:13], A12/BC#,

A11, A10/AP, A[9:0]

Input

Address inputs: 

Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 118).

BA[2:0]

Input

Bank address inputs:

 BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V

REFCA

.

CK, CK#

Input

Clock:

 CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock enable:

 CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for power-
down entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to V

REFCA

.

CS#

Input

Chip select:

 CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V

REFCA

.

LDM

Input

Input data mask:

 LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

.

ODT

Input

On-die termination: 

ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to V

REFCA

.

RAS#, CAS#, WE#

Input

Command inputs:

 RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

.

RESET#

Input

Reset:

 RESET# is an active LOW CMOS input referenced to V

SS

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 

ุ

 0.8 × V

DD

 and

DC LOW 

ื

 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

21

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)

Symbol

Type

Description

UDM

Input

Input data mask:

 UDM is an upper-byte, input mask signal for write data. Upper-

byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to V

REFDQ

.

DQ[7:0]

I/O

Data input/output:

 Lower byte of bidirectional data bus for the x16 configuration.

DQ[7:0] are referenced to V

REFDQ

.

DQ[15:8]

I/O

Data input/output:

 Upper byte of bidirectional data bus for the x16 configuration.

DQ[15:8] are referenced to V

REFDQ

.

LDQS, LDQS#

I/O

Lower byte data strobe:

 Output with read data. Edge-aligned with read data.

Input with write data. Center-aligned to write data.

UDQS, UDQS#

I/O

Upper byte data strobe:

 Output with read data. Edge-aligned with read data.

Input with write data. DQS is center-aligned to write data.

V

DD

Supply

Power supply:

 1.5V ±0.075V.

V

DDQ

Supply

DQ power supply:

 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

V

REFCA

Supply

Reference voltage for control, command, and address:

 V

REFCA

 must be

maintained at all times (including self refresh) for proper device operation.

V

REFDQ

Supply

Reference voltage for data:

 V

REFDQ

 must be maintained at all times (excluding self

refresh) for proper device operation.

V

SS

Supply

Ground.

V

SSQ

Supply

DQ ground:

 Isolated on the device for improved noise immunity.

ZQ

Reference

External reference ball for output drive calibration:

 This ball is tied to an

external 240

˖

 resistor (RZQ), which is tied to V

SSQ

.

NC

–

No connect:

 These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

22

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Package Dimensions

Figure 8: 78-Ball FBGA – x4, x8 (RH)

6.4 CTR

9 ±0.1

0.8 TYP

10.5 ±0.1

9.6 CTR

0.8 TYP

1.1 ±0.1

0.25 MIN

1

A

2

3

7

8

9

B

C

D

E

F

G

H

J

K

L

M

N

0.12 A

A

0.155

78X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.35 SMD
ball pads.

Seating plane

Ball A1 ID
(covered by SR)

Ball A1 ID

1.8 CTR

Nonconductive

overmold

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

23

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 9: 78-Ball FBGA – x4, x8 (RG)

1.8 CTR

nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

A

0.25 MIN

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

9.6 CTR

10.6 ±0.1

78X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

24

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 10: 78-Ball FBGA – x4, x8 (DA)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

0.29 MIN

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

9.6 CTR

10.5 ±0.1

78X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

A

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

25

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 11: 96-Ball FBGA – x16 (HA)

Ball A1 Index

Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.

14 ±0.1

0.8 TYP

1.1 ±0.1

12 CTR

Ball A1 Index
(covered by SR)

0.8 TYP

9 ±0.1

0.25 MIN

6.4 CTR

96X Ø0.45

9 8 7 

3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

0.12 A

Seating plane

1.8 CTR

Nonconductive

overmold

0.155

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

26

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 12: 96-Ball FBGA – x16 (LY)

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

A

0.29 MIN

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

12 CTR

13.5 ±0.1

96X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42
SMD ball pads.

0.8 TYP

1.8 CTR

Nonconductive

overmold

0.155

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

27

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Figure 13: 96-Ball FBGA – x16 (TW)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

12 CTR

14 ±0.1

96X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

Notes:

1. All dimensions are in millimeters.
2. Material composition: Pb-free SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

28

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Electrical Specifications

Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.

Table 5: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

V

DD

V

DD

 supply voltage relative to V

SS

–0.4

1.975

V

1

V

DDQ

V

DD

 supply voltage relative to V

SSQ

–0.4

1.975

V

 

V

IN

, V

OUT

Voltage on any pin relative to V

SS

–0.4

1.975

V

 

T

C

Operating case temperature – Commercial

0

95

°C

2, 3

Operating case temperature – Industrial

–40

95

°C

2, 3

Operating case temperature – Automotive

–40

105

°C

2, 3

T

STG

Storage temperature

–55

150

°C

 

Notes:

1. V

DD

 and V

DDQ

 must be within 300mV of each other at all times, and V

REF

 must not be

greater than 0.6 × V

DDQ

. When V

DD

 and V

DDQ

 are <500mV, V

REF

 can be 

ื

300mV.

2. MAX operating case temperature. T

C

 is measured in the center of the package.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T

C

 dur-

ing operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

29

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Input/Output Capacitance

Table 6: DDR3L Input/Output Capacitance

Note 1 applies to the entire table

Capacitance
Parameters

Sym

DDR3L

-800

DDR3L

-1066

DDR3L

-1333

DDR3L

-1600

DDR3L

-1866

DDR3L

-2133

Unit Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

CK and CK#

C

CK

0.8

1.6

0.8

1.6

0.8

1.4

0.8

1.4

0.8

1.3

0.8

1.3

pF

 

˂

C: CK to CK#

C

DCK

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

pF

 

Single-end
I/O: DQ, DM

C

IO

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1.4

2.1

pF

2

Differential
I/O: DQS,
DQS#, TDQS,
TDQS#

C

IO

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1.4

2.1

pF

3

˂

C: DQS to

DQS#, TDQS,
TDQS#

C

DDQS

0.0

0.2

0.0

0.2

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

pF

3

˂

C: DQ to

DQS

C

DIO

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

pF

4

Inputs (CTRL,
CMD, ADDR)

C

I

0.75

1.3

0.75

1.3

0.75

1.3

0.75

1.2

0.75

1.2

0.75

1.2

pF

5

˂

C: CTRL to

CK

C

DI_CTRL

–0.5

0.3

–0.5

0.3

–0.4

0.2

–0.4

0.2

–0.4

0.2

–0.4

0.2

pF

6

˂

C:

CMD_ADDR
to CK

C

DI_CMD

_ADDR

–0.5

0.5

–0.5

0.5

–0.4

0.4

–0.4

0.4

–0.4

0.4

–0.4

0.4

pF

7

ZQ pin
capacitance

C

ZQ

–

3.0

–

3.0

–

3.0

–

3.0

–

3.0

–

3.0

pF

 

Reset pin
capacitance

C

RE

–

3.0

–

3.0

–

3.0

–

3.0

–

3.0

–

3.0

pF

 

Notes:

1. V

DD

 = 1.35V (1.283–1.45V), V

DDQ

 = V

DD

, V

REF

 = V

SS

, 

f 

= 100 MHz, T

C 

= 25°C. V

OUT(DC)

 = 0.5

× V

DDQ

, V

OUT

 = 0.1V (peak-to-peak).

2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. C

DDQS

 is for DQS vs. DQS# and TDQS vs. TDQS# separately.

4. C

DIO

 = C

IO(DQ)

 - 0.5 × (C

IO(DQS)

 + C

IO(DQS#)

).

5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =

A[

n

:0], BA[2:0].

6. C

DI_CTRL

 = C

I(CTRL)

 - 0.5 × (C

CK(CK)

 + C

CK(CK#)

).

7. C

DI_CMD_ADDR

 = C

I(CMD_ADDR)

 - 0.5 × (C

CK(CK)

 + C

CK(CK#)

).

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Thermal Characteristics

Table 7: Thermal Characteristics

Notes 1–3 apply to entire table

Parameter

Symbol

Value

Units

Notes

Operating temperature - Commercial

T

C

0 to 85

°C

Operating temperature - Industrial

T

C

-40 to 95

°C

4

Operating temperature - Automotive

T

C

-40 to105

°C

5

Notes:

1. MAX operating case temperature T

C

 is measured in the center of the package, as shown

below.

2. A thermal solution must be designed to ensure that the device does not exceed the

maximum T

C

 during operation.

3. Device functionality is not guaranteed if the device exceeds maximum T

C

 during

operation.

4. If T

C

 exceeds 85°C, but is less than 95°C, the DRAM must be refreshed manually at 2x re-

fresh, which is a 3.9μs interval refresh rate. The use of self refresh temperature (SRT) or
automatic self refresh (ASR), must be enabled.

5. If T

C

 exceeds 95°C, but less than 105°C, the DRAM must be refreshed manually at 4x re-

fresh, which is a 1.95μs interval refresh rate. The use of self refresh temperature (SRT) or
automatic self refresh (ASR), must be enabled.

Figure 14: Thermal Measurement Point

(L/2)

L

W

(W/2)

Tc test point

4Gb: x4, x8, x16 DDR3L SDRAM

Thermal Characteristics

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 8: Thermal Impedance

Die Rev.

Package

Substrate

ˆ

ˆ

 JA (°C/W)

Airflow =

0m/s

ˆ

 JA (°C/W)

Airflow =

1m/s

ˆ

 JA (°C/W)

Airflow =

2m/s

ˆ

 JB (°C/W)

ˆ

 JC (°C/W)

E

78-ball

Low conduc-

tivity

63.7

49.6

44.0

N/A

4.0

High con-

ductivity

42.3

35.7

32.9

29.7

N/A

96-ball

Low conduc-

tivity

50.4

39.2

35.1

N/A

3.9

High con-

ductivity

31.3

26.1

24.3

19.2

N/A

N

78-ball

Low conduc-

tivity

61.7

47.6

42.6

N/A

5.7

High con-

ductivity

40.6

33.4

31.2

19.1

N/A

96-ball

Low conduc-

tivity

52.1

42.1

38.4

N/A

5.6

High con-

ductivity

32.6

27.9

26.5

12.6

N/A

P

78-ball

Low conduc-

tivity

88.3

70.6

64.1

N/A

10.8

High con-

ductivity

56.5

48.4

45.7

25.5

N/A

96-ball

Low conduc-

tivity

54.3

42.1

37.3

N/A

4.6

High con-

ductivity

34.8

29.0

26.9

16.9

N/A

Note:

1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

4Gb: x4, x8, x16 DDR3L SDRAM

Thermal Characteristics

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Electrical Specifications – I

DD

 Specifications and Conditions

Within the following I

DD

 measurement tables, the following definitions and conditions

are used, unless stated otherwise:

• LOW: V

IN

 

”

 V

IL(AC)max

; HIGH: V

IN

 

•

 V

IH(AC)min

.

• Midlevel: Inputs are V

REF

 = V

DD

/2.

• R

ON

 set to RZQ/7 (34

ȍ

).

• R

TT,nom

 set to RZQ/6 (40

ȍ

).

• R

TT(WR)

 set to RZQ/2 (120

ȍ

).

• Q

OFF

 is enabled in MR1.

• ODT is enabled in MR1 (R

TT,nom

) and MR2 (R

TT(WR)

).

• TDQS is disabled in MR1.
• External DQ/DQS/DM load resistor is 25

ȍ

 to V

DDQ

/2.

• Burst lengths are BL8 fixed.
• AL equals 0 (except in I

DD7

).

• I

DD

 specifications are tested after the device is properly initialized.

• Input slew rate is specified by AC parametric test conditions.
• Optional ASR is disabled.
• Read burst type uses nibble sequential (MR0[3] = 0).
• Loop patterns must be executed at least once before current measurements begin.

Table 9: Timing Parameters Used for I

DD

 Measurements – Clock Units

I

DD

Parameter

DDR3L

-800

DDR3L

-1066

DDR3L

-1333

DDR3L

-1600

DDR3L

-1866

DDR3L

-2133

Unit

-25E

-25

-187E

-187

-15E

-15

-125E

-125

-107

-093

5-5-5

6-6-6

7-7-7

8-8-8

9-9-9

10-10-10 10-10-10 11-11-11 13-13-13 14-14-14

t

CK (MIN) I

DD

2.5

1.875

1.5

1.25

1.07

0.938

ns

CL I

DD

5

6

7

8

9

10

10

11

13

14

CK

t

RCD (MIN) I

DD

5

6

7

8

9

10

10

11

13

14

CK

t

RC (MIN) I

DD

20

21

27

28

33

34

38

39

45

50

CK

t

RAS (MIN) I

DD

15

15

20

20

24

24

28

28

32

36

CK

t

RP (MIN)

5

6

7

8

9

10

10

11

13

14

CK

t

FAW

x4, x8

16

16

20

20

20

20

24

24

26

27

CK

x16

20

20

27

27

30

30

32

32

33

38

CK

t

RRD

I

DD

x4, x8

4

4

4

4

4

4

5

5

5

6

CK

x16

4

4

6

6

5

5

6

6

6

7

CK

t

RFC

1Gb

44

44

59

59

74

74

88

88

103

118

CK

2Gb

64

64

86

86

107

107

128

128

150

172

CK

4Gb

104

104

139

139

174

174

208

208

243

279

CK

8Gb

140

140

187

187

234

234

280

280

328

375

CK

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 10: I

DD0

 Measurement Loop

CK, CK#

CKE

Sub-

Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

–

1

D

1

0

0

0

0

0

0

0

0

0

0

–

2

D

1

0

0

0

0

0

0

0

0

0

0

–

3

D#

1

1

1

1

0

0

0

0

0

0

0

–

4

D#

1

1

1

1

0

0

0

0

0

0

0

–

 

Repeat cycles 1 through 4 until 

n

RAS - 1; truncate if needed

n

RAS

PRE

0

0

1

0

0

0

0

0

0

0

0

–

 

Repeat cycles 1 through 4 until 

n

RC - 1; truncate if needed

n

RC

ACT

0

0

1

1

0

0

0

0

0

F

0

–

n

RC  +  1

D

1

0

0

0

0

0

0

0

0

F

0

–

n

RC  +  2

D

1

0

0

0

0

0

0

0

0

F

0

–

n

RC  +  3

D#

1

1

1

1

0

0

0

0

0

F

0

–

n

RC  +  4

D#

1

1

1

1

0

0

0

0

0

F

0

–

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC - 1 + 

n

RAS -1; truncate if needed

n

RC + 

n

RAS

PRE

0

0

1

0

0

0

0

0

0

F

0

–

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 2 × RC - 1; truncate if needed

1

2 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 1

2

4 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 2

3

6 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 3

4

8 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 4

5

10 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 5

6

12 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 6

7

14 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. Only selected bank (single) active.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 11: I

DD1

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

2

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

–

1

D

1

0

0

0

0

0

0

0

0

0

0

–

2

D

1

0

0

0

0

0

0

0

0

0

0

–

3

D#

1

1

1

1

0

0

0

0

0

0

0

–

4

D#

1

1

1

1

0

0

0

0

0

0

0

–

 

Repeat cycles 1 through 4 until 

n

RCD - 1; truncate if needed

n

RCD

RD

0

1

0

1

0

0

0

0

0

0

0

00000000

 

Repeat cycles 1 through 4 until 

n

RAS - 1; truncate if needed

n

RAS

PRE

0

0

1

0

0

0

0

0

0

0

0

–

 

Repeat cycles 1 through 4 until 

n

RC - 1; truncate if needed

n

RC

ACT

0

0

1

1

0

0

0

0

0

F

0

–

n

RC  +  1

D

1

0

0

0

0

0

0

0

0

F

0

–

n

RC  +  2

D

1

0

0

0

0

0

0

0

0

F

0

–

n

RC  +  3

D#

1

1

1

1

0

0

0

0

0

F

0

–

n

RC  +  4

D#

1

1

1

1

0

0

0

0

0

F

0

–

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC + 

n

RCD - 1; truncate if needed

n

RC + 

n

RCD

RD

0

1

0

1

0

0

0

0

0

F

0

00110011

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC + 

n

RAS - 1; truncate if needed

n

RC + 

n

RAS

PRE

0

0

1

0

0

0

0

0

0

F

0

–

 Repeat 

cycle 

n

RC + 1 through 

n

RC + 4 until 2 × 

n

RC - 1; truncate if needed

1

2 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 1

2

4 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 2

3

6 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 3

4

8 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 4

5

10 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 5

6

12 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 6

7

14 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. Only selected bank (single) active.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 12: I

DD

 Measurement Conditions for Power-Down Currents

Name

I

DD2P0

 Precharge

Power-Down

Current (Slow Exit)

1

I

DD2P1

 Precharge

Power-Down

Current (Fast Exit)

1

I

DD2Q

 Precharge

Quiet

Standby Current

I

DD3P

 Active

Power-Down

Current

Timing pattern

N/A

N/A

N/A

N/A

CKE

LOW

LOW

HIGH

LOW

External clock

Toggling

Toggling

Toggling

Toggling

t

CK

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

RC

N/A

N/A

N/A

N/A

t

RAS

N/A

N/A

N/A

N/A

t

RCD

N/A

N/A

N/A

N/A

t

RRD

N/A

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

N/A

CL

N/A

N/A

N/A

N/A

AL

N/A

N/A

N/A

N/A

CS#

HIGH

HIGH

HIGH

HIGH

Command inputs

LOW

LOW

LOW

LOW

Row/column addr

LOW

LOW

LOW

LOW

Bank addresses

LOW

LOW

LOW

LOW

DM

LOW

LOW

LOW

LOW

Data I/O

Midlevel

Midlevel

Midlevel

Midlevel

Output buffer DQ, DQS

Enabled

Enabled

Enabled

Enabled

ODT

2

Enabled, off

Enabled, off

Enabled, off

Enabled, off

Burst length

8

8

8

8

Active banks

None

None

None

All

Idle banks

All

All

All

None

Special notes

N/A

N/A

N/A

N/A

Notes:

1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast

exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).

2. “Enabled, off” means the MR bits are enabled, but the signal is LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 13: I

DD2N

 and I

DD3N

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

D

1

0

0

0

0

0

0

0

0

0

0

–

1

D

1

0

0

0

0

0

0

0

0

0

0

–

2

D#

1

1

1

1

0

0

0

0

0

F

0

–

3

D#

1

1

1

1

0

0

0

0

0

F

0

–

1

4–7

Repeat sub-loop 0, use BA[2:0] = 1

2

8–11

Repeat sub-loop 0, use BA[2:0] = 2

3

12–15

Repeat sub-loop 0, use BA[2:0] = 3

4

16–19

Repeat sub-loop 0, use BA[2:0] = 4

5

20–23

Repeat sub-loop 0, use BA[2:0] = 5

6

24–27

Repeat sub-loop 0, use BA[2:0] = 6

7

28–31

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed during I

DD2N

; all banks open during I

DD3N

.

Table 14: I

DD2NT

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

D

1

0

0

0

0

0

0

0

0

0

0

–

1

D

1

0

0

0

0

0

0

0

0

0

0

–

2

D#

1

1

1

1

0

0

0

0

0

F

0

–

3

D#

1

1

1

1

0

0

0

0

0

F

0

–

1

4–7

Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0

2

8–11

Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1

3

12–15

Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1

4

16–19

Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0

5

20–23

Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0

6

24–27

Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1

7

28–31

Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 15: I

DD4R

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

0

0

RD

0

1

0

1

0

0

0

0

0

0

0

00000000

1

D

1

0

0

0

0

0

0

0

0

0

0

–

2

D#

1

1

1

1

0

0

0

0

0

0

0

–

3

D#

1

1

1

1

0

0

0

0

0

0

0

–

4

RD

0

1

0

1

0

0

0

0

0

F

0

00110011

5

D

1

0

0

0

0

0

0

0

0

F

0

–

6

D#

1

1

1

1

0

0

0

0

0

F

0

–

7

D#

1

1

1

1

0

0

0

0

0

F

0

–

1

8–15

Repeat sub-loop 0, use BA[2:0] = 1

2

16–23

Repeat sub-loop 0, use BA[2:0] = 2

3

24–31

Repeat sub-loop 0, use BA[2:0] = 3

4

32–39

Repeat sub-loop 0, use BA[2:0] = 4

5

40–47

Repeat sub-loop 0, use BA[2:0] = 5

6

48–55

Repeat sub-loop 0, use BA[2:0] = 6

7

56–63

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. All banks open.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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© 2017 Micron Technology, Inc. All rights reserved.

Table 16: I

DD4W

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

4

T

oggling

Static HIGH

0

0

WR

0

1

0

0

1

0

0

0

0

0

0

00000000

1

D

1

0

0

0

1

0

0

0

0

0

0

–

2

D#

1

1

1

1

1

0

0

0

0

0

0

–

3

D#

1

1

1

1

1

0

0

0

0

0

0

–

4

WR

0

1

0

0

1

0

0

0

0

F

0

00110011

5

D

1

0

0

0

1

0

0

0

0

F

0

–

6

D#

1

1

1

1

1

0

0

0

0

F

0

–

7

D#

1

1

1

1

1

0

0

0

0

F

0

–

1

8–15

Repeat sub-loop 0, use BA[2:0] = 1

2

16–23

Repeat sub-loop 0, use BA[2:0] = 2

3

24–31

Repeat sub-loop 0, use BA[2:0] = 3

4

32–39

Repeat sub-loop 0, use BA[2:0] = 4

5

40–47

Repeat sub-loop 0, use BA[2:0] = 5

6

48–55

Repeat sub-loop 0, use BA[2:0] = 6

7

56–63

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the WR command.
4. All banks open.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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© 2017 Micron Technology, Inc. All rights reserved.

Table 17: I

DD5B

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

REF

0

0

0

1

0

0

0

0

0

0

0

–

1a

1

D

1

0

0

0

0

0

0

0

0

0

0

–

2

D

1

0

0

0

0

0

0

0

0

0

0

–

3

D#

1

1

1

1

0

0

0

0

0

F

0

–

4

D#

1

1

1

1

0

0

0

0

0

F

0

–

1b

5–8

Repeat sub-loop 1a, use BA[2:0] = 1

1c

9–12

Repeat sub-loop 1a, use BA[2:0] = 2

1d

13–16

Repeat sub-loop 1a, use BA[2:0] = 3

1e

17–20

Repeat sub-loop 1a, use BA[2:0] = 4

1f

21–24

Repeat sub-loop 1a, use BA[2:0] = 5

1g

25–28

Repeat sub-loop 1a, use BA[2:0] = 6

1h

29–32

Repeat sub-loop 1a, use BA[2:0] = 7

2

33–

n

RFC - 1

Repeat sub-loop 1a through 1h until 

n

RFC - 1; truncate if needed

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

40

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Table 18: I

DD

 Measurement Conditions for I

DD6

, I

DD6ET

, and I

DD8

I

DD

 Test

I

DD6

: Self Refresh Current

Normal Temperature Range

T

C

 = 0°C to +85°C

I

DD6ET

: Self Refresh Current

Extended Temperature Range

T

C

 = 0°C to +95°C

I

DD8

: Reset

2

CKE

LOW

LOW

Midlevel

External clock

Off, CK and CK# = LOW

Off, CK and CK# = LOW

Midlevel

t

CK

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

t

RAS

N/A

N/A

N/A

t

RCD

N/A

N/A

N/A

t

RRD

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

CL

N/A

N/A

N/A

AL

N/A

N/A

N/A

CS#

Midlevel

Midlevel

Midlevel

Command inputs

Midlevel

Midlevel

Midlevel

Row/column addresses

Midlevel

Midlevel

Midlevel

Bank addresses

Midlevel

Midlevel

Midlevel

Data I/O

Midlevel

Midlevel

Midlevel

Output buffer DQ, DQS

Enabled

Enabled

Midlevel

ODT

1

Enabled, midlevel

Enabled, midlevel

Midlevel

Burst length

N/A

N/A

N/A

Active banks

N/A

N/A

None

Idle banks

N/A

N/A

All

SRT

Disabled (normal)

Enabled (extended)

N/A

ASR

Disabled

Disabled

N/A

Notes:

1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable

and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns + 

t

RFC.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

41

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© 2017 Micron Technology, Inc. All rights reserved.

Table 19: I

DD7

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

–

1

RDA

0

1

0

1

0

0

0

1

0

0

0

00000000

2

D

1

0

0

0

0

0

0

0

0

0

0

–

3

Repeat cycle 2 until 

n

RRD - 1

1

n

RRD

ACT

0

0

1

1

0

1

0

0

0

F

0

–

n

RRD + 1

RDA

0

1

0

1

0

1

0

1

0

F

0

00110011

n

RRD + 2

D

1

0

0

0

0

1

0

0

0

F

0

–

n

RRD + 3

Repeat cycle 

n

RRD + 2 until 2 × 

n

RRD - 1

2

2 × 

n

RRD

Repeat sub-loop 0, use BA[2:0] = 2

3

3 × 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 3

4

4 × 

n

RRD

D

1

0

0

0

0

3

0

0

0

F

0

–

4 × 

n

RRD + 1

Repeat cycle 4 × 

n

RRD until 

n

FAW - 1, if needed

5

n

FAW

Repeat sub-loop 0, use BA[2:0] = 4

6

n

FAW + 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 5

7

n

FAW + 2 × 

n

RRD

Repeat sub-loop 0, use BA[2:0] = 6

8

n

FAW + 3 × 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 7

9

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

7

0

0

0

F

0

–

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 

n

FAW + 4 × 

n

RRD until 2 × 

n

FAW - 1, if needed

10

2 × 

n

FAW

ACT

0

0

1

1

0

0

0

0

0

F

0

–

2 × 

n

FAW  +  1

RDA

0

1

0

1

0

0

0

1

0

F

0

00110011

2 × 

n

FAW  +  2

D

1

0

0

0

0

0

0

0

0

F

0

–

2 × 

n

FAW + 3

Repeat cycle 2 × 

n

FAW + 2 until 2 × 

n

FAW + 

n

RRD - 1

11

2 × 

n

FAW + 

n

RRD

ACT

0

0

1

1

0

1

0

0

0

0

0

–

2 × 

n

FAW + 

n

RRD + 1

RDA

0

1

0

1

0

1

0

1

0

0

0

00000000

2 × 

n

FAW + 

n

RRD + 2

D

1

0

0

0

0

1

0

0

0

0

0

–

2 × 

n

FAW + 

n

RRD + 3

Repeat cycle 2 × 

n

FAW + 

n

RRD + 2 until 2 × 

n

FAW + 2 × 

n

RRD - 1

12

2 × 

n

FAW + 2 × 

n

RRD

Repeat sub-loop 10, use BA[2:0] = 2

13

2 × 

n

FAW + 3 × 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 3

14

2 × 

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

3

0

0

0

0

0

–

2 × 

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 2 × 

n

FAW + 4 × 

n

RRD until 3 × 

n

FAW - 1, if needed

15

3 × 

n

FAW

Repeat sub-loop 10, use BA[2:0] = 4

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

42

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Table 19: I

DD7

 Measurement Loop (Continued)

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

16

3 × 

n

FAW + 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 5

17

3 × 

n

FAW + 2 × 

n

RRD

Repeat sub-loop 10, use BA[2:0] = 6

18

3 × 

n

FAW + 3 × 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 7

19

3 × 

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

7

0

0

0

0

0

–

3 × 

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 3 × 

n

FAW + 4 × 

n

RRD until 4 × 

n

FAW - 1, if needed

Notes:

1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. AL = CL-1.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

43

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Electrical Characteristics – Operating I

DD

 Specifications

Table 20: I

DD

 Maximum Limits Die Rev. E for 1.35/1.5V Operation

Speed Bin

DDR3/3L

-1066

DDR3/3L

-1333

DDR3/3L

-1600

DDR3/3L

-1866

Units

Notes

Parameter

Symbol

Width

Operating current 0: One bank
ACTIVATE-to-PRECHARGE

I

DD0

x4, x8

44

47

55

62

mA

1, 2

x16

55

58

66

73

mA

1, 2

Operating current 1: One bank
ACTIVATE-to-READ-to-PRECHARGE

I

DD1

x4

53

57

61

65

mA

1, 2

x8

59

62

66

70

mA

1, 2

x16

80

84

87

91

mA

1, 2

Precharge power-down current:
Slow exit

I

DD2P0

All

18

18

18

18

mA

1, 2

Precharge power-down current:
Fast exit

I

DD2P1

All

26

28

32

37

mA

1, 2

Precharge quiet standby current

I

DD2Q

All

27

28

32

35

mA

1, 2

Precharge standby current

I

DD2N

All

28

29

32

35

mA

1, 2

Precharge standby ODT current

I

DD2NT

x4, x8

32

35

39

42

mA

1, 2

x16

35

39

42

45

mA

1, 2

Active power-down current

I

DD3P

All

32

35

38

41

mA

1, 2

Active standby current

I

DD3N

x4, x8

32

35

38

41

mA

1, 2

x16

41

45

47

49

mA

1, 2

Burst read operating current

I

DD4R

x4

113

130

147

164

mA

1, 2

x8

123

140

157

174

mA

1, 2

x16

185

202

235

252

mA

1, 2

Burst write operating current

I

DD4W

x4

87

103

118

133

mA

1, 2

x8

95

110

125

141

mA

1, 2

x16

137

152

171

190

mA

1, 2

Burst refresh current

I

DD5B

All

224

228

235

242

mA

1, 2

Room temperature self refresh

I

DD6

All

20

20

20

20

mA

1, 2, 3

Extended temperature self refresh

I

DD6ET

All

25

25

25

25

mA

2, 4

All banks interleaved read current

I

DD7

x4, x8

160

190

220

251

mA

1, 2

x16

198

217

243

274

mA

1, 2

Reset current

I

DD8

All

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

C 

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

ื

 T

C

 

ื

 +85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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© 2017 Micron Technology, Inc. All rights reserved.

5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

Table 21: I

DD

 Maximum Limits Die Rev. N for 1.35V/1.5V Operation

Speed Bin

DDR3/3L

-1066

DDR3/3L

-1333

DDR3/3L

-1600

DDR3/3L

-1866

DDR3/3L

-2133

Units

Notes

Parameter

Symbol Width

Operating current 0: One bank
ACTIVATE-to-PRECHARGE

I

DD0

x4, x8

42

45

47

49

51

mA

1, 2

x16

52

55

57

59

61

mA

1, 2

Operating current 1: One bank
ACTIVATE-to-READ-to-PRE-
CHARGE

I

DD1

x4

50

53

56

59

62

mA

1, 2

x8

55

58

61

64

67

mA

1, 2

x16

75

78

81

84

87

mA

1, 2

Precharge power-down cur-
rent: Slow exit

I

DD2P0

All

8

8

8

8

8

mA

1, 2

Precharge power-down cur-
rent: Fast exit

I

DD2P1

All

10

12

14

16

18

mA

1, 2

Precharge quiet standby cur-
rent

I

DD2Q

All

20

22

24

26

28

mA

1, 2

Precharge standby current

I

DD2N

All

20

22

24

26

28

mA

1, 2

Precharge standby ODT current

I

DD2NT

x4, x8

24

26

28

30

32

mA

1, 2

x16

27

29

31

33

35

mA

1, 2

Active power-down current

I

DD3P

All

22

24

26

28

30

mA

1, 2

Active standby current

I

DD3N

x4, x8

26

28

30

32

34

mA

1, 2

x16

34

36

38

40

42

mA

1, 2

Burst read operating current

I

DD4R

x4

65

75

85

95

105

mA

1, 2

x8

75

85

95

105

115

mA

1, 2

x16

135

145

155

165

175

mA

1, 2

Burst write operating current

I

DD4W

x4

65

75

85

95

105

mA

1, 2

x8

75

85

95

105

115

mA

1, 2

x16

135

145

155

165

175

mA

1, 2

Burst refresh current

I

DD5B

All

165

170

175

180

185

mA

1, 2

Room temperature self refresh

I

DD6

All

12

12

12

12

12

mA

1, 2, 3

Extended temperature self re-
fresh

I

DD6ET

All

16

16

16

16

16

mA

2, 4

All banks interleaved read cur-
rent

I

DD7

x4, x8

110

120

130

140

150

mA

1, 2

x16

170

180

190

200

210

mA

1, 2

Reset current

I

DD8

All

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

C 

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

45

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