DDR3L SDRAM

MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM
(Die Rev :E) data sheet specifications when running in
1.5V compatible mode.

Features

• V

DD

 = V

DDQ

 = 1.35V (1.283–1.45V)

• Backward compatible to V

DD

 = V

DDQ

 = 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe
• 8

n

-bit prefetch architecture

• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T

of 105°C

– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
– 16ms, 8192-cycle refresh at >95°C to 105°C

• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration

Options

Marking

• Configuration

 

– 1 Gig x 4

1G4

– 512 Meg x 8

512M8

– 256 Meg x 16

256M16

• FBGA package (Pb-free) – x4, x8

 

– 78-ball (9mm x 10.5mm) Rev. E

RH

– 78-ball (7.5mm x 10.6mm) Rev. N

RG

– 78-ball (8mm x 10.5mm) Rev. P

DA

• FBGA package (Pb-free) – x16

 

– 96-ball (9mm x 14mm) Rev. E

HA

– 96-ball (7.5mm x 13.5mm) Rev. N

LY

– 96-ball (8mm x 14mm) Rev. P

TW

• Timing – cycle time

 

– 938ps @ CL = 14 (DDR3-2133)

-093

– 1.07ns @ CL = 13 (DDR3-1866)

-107

– 1.25ns @ CL = 11 (DDR3-1600)

-125

• Operating temperature

– Commercial (0°C 

”

 T

C

 

”

 +95°C)

None

– Industrial (–40°C 

”

 T

C

 

”

 +95°C)

IT

– Automotive (–40°C 

”

 T

C

 

”

 +105°C)

AT

• Revision

:E/:N/:P

Table 1: Key Timing Parameters

Speed Grade

Data Rate (MT/s)

Target 

t

RCD-

t

RP-CL

t

RCD (ns)

t

RP (ns)

CL (ns)

-093

 1, 2

2133

14-14-14

13.09

13.09

13.09

-107

 1

1866

13-13-13

13.91

13.91

13.91

-125

1600

11-11-11

13.75

13.75

13.75

Notes:

1. Backward compatible to 1600, CL = 11 (-125).
2. Backward compatible to 1866, CL = 13 (-107).

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

1

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

datasheets/MT41K256M16TW-html.html

Table 2: Addressing

Parameter

1 Gig x 4

512 Meg x 8

256 Meg x 16

Configuration

128 Meg x 4 x 8 banks

64 Meg x 8 x 8 banks

32 Meg x 16 x 8 banks

Refresh count

8K

8K

8K

Row address

64K (A[15:0])

64K (A[15:0])

32K (A[14:0])

Bank address

8 (BA[2:0])

8 (BA[2:0])

8 (BA[2:0])

Column address

2K (A[11, 9:0])

1K (A[9:0])

1K (A[9:0])

Page size

1KB

1KB

2KB

Figure 1: DDR3L Part Numbers

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Note:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: 
http://www.micron.com.

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Contents

Important Notes and Warnings  .......................................................................................................................  11
State Diagram  ................................................................................................................................................  12
Functional Description ...................................................................................................................................  13

Industrial Temperature  ...............................................................................................................................  13
Automotive Temperature  
............................................................................................................................  13
General Notes  ............................................................................................................................................  14

Functional Block Diagrams  .............................................................................................................................  15
Ball Assignments and Descriptions  .................................................................................................................  17
Package Dimensions .......................................................................................................................................  23
Electrical Specifications  ..................................................................................................................................  29

Absolute Ratings .........................................................................................................................................  29
Input/Output Capacitance ..........................................................................................................................  30

Thermal Characteristics ..................................................................................................................................  31
Electrical Specifications – I

DD

 Specifications and Conditions ............................................................................  33

Electrical Characteristics – Operating I

DD

 Specifications  ..................................................................................  44

Electrical Specifications – DC and AC  ..............................................................................................................  49

DC Operating Conditions  ...........................................................................................................................  49
Input Operating Conditions  ........................................................................................................................  50
DDR3L 1.35V AC Overshoot/Undershoot Specification  ................................................................................  54
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals  ..............................................................  57
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals  .................................................................  59

ODT Characteristics  .......................................................................................................................................  60

1.35V ODT Resistors  ...................................................................................................................................  61
ODT Sensitivity  ..........................................................................................................................................  62
ODT Timing Definitions  
.............................................................................................................................  62

Output Driver Impedance ...............................................................................................................................  66

34 Ohm Output Driver Impedance  ..............................................................................................................  67
DDR3L 34 Ohm Driver  ................................................................................................................................   68
DDR3L 34 Ohm Output Driver Sensitivity  ....................................................................................................  69
DDR3L Alternative 40 Ohm Driver ...............................................................................................................  70
DDR3L 40 Ohm Output Driver Sensitivity  
....................................................................................................  70

Output Characteristics and Operating Conditions ............................................................................................  72

Reference Output Load  ...............................................................................................................................  75
Slew Rate Definitions for Single-Ended Output Signals 
.................................................................................  75
Slew Rate Definitions for Differential Output Signals ....................................................................................  77

Speed Bin Tables  ............................................................................................................................................  78
Electrical Characteristics and AC Operating Conditions  ...................................................................................  83
Command and Address Setup, Hold, and Derating .......................................................................................... 103
Data Setup, Hold, and Derating ...................................................................................................................... 110
Commands – Truth Tables  ............................................................................................................................. 118
Commands  ................................................................................................................................................... 121

DESELECT  ................................................................................................................................................ 121
NO OPERATION  
........................................................................................................................................ 121
ZQ CALIBRATION LONG  
........................................................................................................................... 121
ZQ CALIBRATION SHORT 
.......................................................................................................................... 121
ACTIVATE  
................................................................................................................................................. 121
READ  
........................................................................................................................................................ 121
WRITE  ...................................................................................................................................................... 122
PRECHARGE  ............................................................................................................................................. 123
REFRESH  
.................................................................................................................................................. 123

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

SELF REFRESH .......................................................................................................................................... 124
DLL Disable Mode ..................................................................................................................................... 125

Input Clock Frequency Change  ...................................................................................................................... 129
Write Leveling  ............................................................................................................................................... 131

Write Leveling Procedure  ........................................................................................................................... 133
Write Leveling Mode Exit Procedure  ........................................................................................................... 135

Initialization  ................................................................................................................................................. 136
Voltage Initialization/Change  ........................................................................................................................ 138

V

DD

 Voltage Switching  ............................................................................................................................... 139

Mode Registers .............................................................................................................................................. 140
Mode Register 0 (MR0) ................................................................................................................................... 141

Burst Length  ............................................................................................................................................. 141
Burst Type  ................................................................................................................................................. 142
DLL RESET ................................................................................................................................................ 143
Write Recovery  .......................................................................................................................................... 144
Precharge Power-Down (Precharge PD)  
...................................................................................................... 144
CAS Latency (CL) 
....................................................................................................................................... 144

Mode Register 1 (MR1) ................................................................................................................................... 146

DLL Enable/DLL Disable  ........................................................................................................................... 146
Output Drive Strength  ............................................................................................................................... 147
OUTPUT ENABLE/DISABLE  
...................................................................................................................... 147
TDQS Enable 
............................................................................................................................................. 147
On-Die Termination  .................................................................................................................................. 148
WRITE LEVELING  
..................................................................................................................................... 148
POSTED CAS ADDITIVE Latency 
................................................................................................................ 148

Mode Register 2 (MR2) ................................................................................................................................... 149

CAS Write Latency (CWL) ........................................................................................................................... 150
AUTO SELF REFRESH (ASR) 
....................................................................................................................... 150
SELF REFRESH TEMPERATURE (SRT)
 ........................................................................................................ 150
SRT vs. ASR  ............................................................................................................................................... 151
DYNAMIC ODT  
......................................................................................................................................... 151

Mode Register 3 (MR3) ................................................................................................................................... 151

MULTIPURPOSE REGISTER (MPR)  ............................................................................................................ 152
MPR Functional Description ...................................................................................................................... 153
MPR Register Address Definitions and Bursting Order ................................................................................. 154
MPR Read Predefined Pattern  .................................................................................................................... 159

MODE REGISTER SET (MRS) Command  ........................................................................................................ 159
ZQ CALIBRATION Operation  ......................................................................................................................... 160
ACTIVATE Operation  ..................................................................................................................................... 161
READ Operation ............................................................................................................................................ 163
WRITE Operation  .......................................................................................................................................... 174

DQ Input Timing  ....................................................................................................................................... 182

PRECHARGE Operation  ................................................................................................................................. 184
SELF REFRESH Operation 
.............................................................................................................................. 184
Extended Temperature Usage  ........................................................................................................................ 186
Power-Down Mode ........................................................................................................................................ 187
RESET Operation ........................................................................................................................................... 195
On-Die Termination (ODT) ............................................................................................................................ 197

Functional Representation of ODT  ............................................................................................................. 197
Nominal ODT 
............................................................................................................................................ 197

Dynamic ODT  ............................................................................................................................................... 199

Dynamic ODT Special Use Case  ................................................................................................................. 199

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Functional Description .............................................................................................................................. 199

Synchronous ODT Mode ................................................................................................................................ 205

ODT Latency and Posted ODT .................................................................................................................... 205
Timing Parameters  
.................................................................................................................................... 205
ODT Off During READs .............................................................................................................................. 208

Asynchronous ODT Mode .............................................................................................................................. 210

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 212

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)  ........................................................ 214

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)  ...................................................... 216

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

List of Figures

Figure 1:   DDR3L Part Numbers  ........................................................................................................................  2
Figure 2:   Simplified State Diagram  .................................................................................................................  12
Figure 3:   1 Gig x 4 Functional Block Diagram  ..................................................................................................  15
Figure 4:   512 Meg x 8 Functional Block Diagram  .............................................................................................  16
Figure 5:   256 Meg x 16 Functional Block Diagram  
...........................................................................................  16
Figure 6:   78-Ball FBGA – x4, x8 (Top View)  ......................................................................................................  17
Figure 7:   96-Ball FBGA – x16 (Top View)  .........................................................................................................  18
Figure 8:   78-Ball FBGA – x4, x8 (RH)  ...............................................................................................................  23
Figure 9:   78-Ball FBGA – x4, x8 (RG)  ...............................................................................................................  24
Figure 10:   78-Ball FBGA – x4, x8 (DA)  .............................................................................................................  25
Figure 11:   96-Ball FBGA – x16 (HA) .................................................................................................................  26
Figure 12:   96-Ball FBGA – x16 (LY) ..................................................................................................................  27
Figure 13:   96-Ball FBGA – x16 (TW) ................................................................................................................  28
Figure 14:   Thermal Measurement Point  .........................................................................................................  31
Figure 15:   DDR3L 1.35V Input Signal ..............................................................................................................  53
Figure 16:   Overshoot  .....................................................................................................................................  54
Figure 17:   Undershoot ...................................................................................................................................  55
Figure 18:   V

IX

 for Differential Signals  ..............................................................................................................  55

Figure 19:   Single-Ended Requirements for Differential Signals  ........................................................................  55
Figure 20:   Definition of Differential AC-Swing and 

t

DVAC ...............................................................................  56

Figure 21:   Nominal Slew Rate Definition for Single-Ended Input Signals ..........................................................  58
Figure 22:   DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# ..............  59
Figure 23:   ODT Levels and I-V Characteristics  ................................................................................................  60
Figure 24:   ODT Timing Reference Load  ..........................................................................................................  63
Figure 25:   

t

AON and 

t

AOF Definitions  ............................................................................................................  64

Figure 26:   

t

AONPD and 

t

AOFPD Definitions  ...................................................................................................  64

Figure 27:   

t

ADC Definition .............................................................................................................................  65

Figure 28:   Output Driver ................................................................................................................................   66
Figure 29:   DQ Output Signal  ..........................................................................................................................  73
Figure 30:   Differential Output Signal  ..............................................................................................................  74
Figure 31:   Reference Output Load for AC Timing and Output Slew Rate  ...........................................................  75
Figure 32:   Nominal Slew Rate Definition for Single-Ended Output Signals  .......................................................  76
Figure 33:   Nominal Differential Output Slew Rate Definition for DQS, DQS# ....................................................  77
Figure 34:   Nominal Slew Rate and 

t

VAC for 

t

IS (Command and Address – Clock)  ............................................. 106

Figure 35:   Nominal Slew Rate for 

t

IH (Command and Address – Clock) ........................................................... 107

Figure 36:   Tangent Line for 

t

IS (Command and Address – Clock)  .................................................................... 108

Figure 37:   Tangent Line for 

t

IH (Command and Address – Clock) .................................................................... 109

Figure 38:   Nominal Slew Rate and 

t

VAC for 

t

DS (DQ – Strobe) ......................................................................... 114

Figure 39:   Nominal Slew Rate for 

t

DH (DQ – Strobe)  ...................................................................................... 115

Figure 40:   Tangent Line for 

t

DS (DQ – Strobe)  ................................................................................................ 116

Figure 41:   Tangent Line for 

t

DH (DQ – Strobe)  ............................................................................................... 117

Figure 42:   Refresh Mode  ............................................................................................................................... 124
Figure 43:   DLL Enable Mode to DLL Disable Mode  ........................................................................................ 126
Figure 44:   DLL Disable Mode to DLL Enable Mode  ........................................................................................ 127
Figure 45:   DLL Disable 

t

DQSCK  .................................................................................................................... 128

Figure 46:   Change Frequency During Precharge Power-Down  ........................................................................ 130
Figure 47:   Write Leveling Concept ................................................................................................................. 131
Figure 48:   Write Leveling Sequence  ............................................................................................................... 134
Figure 49:   Write Leveling Exit Procedure  ....................................................................................................... 135
Figure 50:   Initialization Sequence  ................................................................................................................. 137

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

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Figure 51:   V

DD

 Voltage Switching  .................................................................................................................. 139

Figure 52:   MRS to MRS Command Timing (

t

MRD) ......................................................................................... 140

Figure 53:   MRS to nonMRS Command Timing (

t

MOD)  .................................................................................. 141

Figure 54:   Mode Register 0 (MR0) Definitions  ................................................................................................ 142
Figure 55:   READ Latency  .............................................................................................................................. 145
Figure 56:   Mode Register 1 (MR1) Definition  ................................................................................................. 146
Figure 57:   READ Latency (AL = 5, CL = 6)  ....................................................................................................... 149
Figure 58:   Mode Register 2 (MR2) Definition  
................................................................................................. 149
Figure 59:   CAS Write Latency  ........................................................................................................................ 150
Figure 60:   Mode Register 3 (MR3) Definition  ................................................................................................. 152
Figure 61:   Multipurpose Register (MPR) Block Diagram  ................................................................................. 153
Figure 62:   MPR System Read Calibration with BL8: Fixed Burst Order Single Readout  ..................................... 155
Figure 63:   MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 156
Figure 64:   MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble  .................................... 157
Figure 65:   MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble  .................................... 158
Figure 66:   ZQ CALIBRATION Timing (ZQCL and ZQCS)  ................................................................................. 160
Figure 67:   Example: Meeting 

t

RRD (MIN) and 

t

RCD (MIN)  ............................................................................. 161

Figure 68:   Example: 

t

FAW ............................................................................................................................. 162

Figure 69:   READ Latency  .............................................................................................................................. 163
Figure 70:   Consecutive READ Bursts (BL8)  .................................................................................................... 165
Figure 71:   Consecutive READ Bursts (BC4)  
.................................................................................................... 165
Figure 72:   Nonconsecutive READ Bursts  ....................................................................................................... 166
Figure 73:   READ (BL8) to WRITE (BL8)
  .......................................................................................................... 166
Figure 74:   READ (BC4) to WRITE (BC4) OTF  .................................................................................................. 167
Figure 75:   READ to PRECHARGE (BL8) 
.......................................................................................................... 167
Figure 76:   READ to PRECHARGE (BC4)  ......................................................................................................... 168
Figure 77:   READ to PRECHARGE (AL = 5, CL = 6)  
........................................................................................... 168
Figure 78:   READ with Auto Precharge (AL = 4, CL = 6) 
..................................................................................... 168
Figure 79:   Data Output Timing – 

t

DQSQ and Data Valid Window   .................................................................... 170

Figure 80:   Data Strobe Timing – READs  ......................................................................................................... 171
Figure 81:   Method for Calculating 

t

LZ and 

t

HZ ............................................................................................... 172

Figure 82:   

t

RPRE Timing  ............................................................................................................................... 172

Figure 83:   

t

RPST Timing  ............................................................................................................................... 173

Figure 84:   

t

WPRE Timing  .............................................................................................................................. 175

Figure 85:   

t

WPST Timing  .............................................................................................................................. 175

Figure 86:   WRITE Burst  ................................................................................................................................ 176
Figure 87:   Consecutive WRITE (BL8) to WRITE (BL8)   ..................................................................................... 177
Figure 88:   Consecutive WRITE (BC4) to WRITE (BC4) via OTF   
........................................................................ 177
Figure 89:   Nonconsecutive WRITE to WRITE   ................................................................................................. 178
Figure 90:   WRITE (BL8) to READ (BL8)
  .......................................................................................................... 178
Figure 91:   WRITE to READ (BC4 Mode Register Setting)  ................................................................................. 179
Figure 92:   WRITE (BC4 OTF) to READ (BC4 OTF)  ........................................................................................... 180
Figure 93:   WRITE (BL8) to PRECHARGE  ........................................................................................................ 181
Figure 94:   WRITE (BC4 Mode Register Setting) to PRECHARGE
  ...................................................................... 181
Figure 95:   WRITE (BC4 OTF) to PRECHARGE  ................................................................................................ 182
Figure 96:   Data Input Timing  ........................................................................................................................ 183
Figure 97:   Self Refresh Entry/Exit Timing  ...................................................................................................... 185
Figure 98:   Active Power-Down Entry and Exit  ................................................................................................ 189
Figure 99:   Precharge Power-Down (Fast-Exit Mode) Entry and Exit 
................................................................. 189
Figure 100:   Precharge Power-Down (Slow-Exit Mode) Entry and Exit  .............................................................. 190
Figure 101:   Power-Down Entry After READ or READ with Auto Precharge (RDAP)  
........................................... 190
Figure 102:   Power-Down Entry After WRITE  .................................................................................................. 191

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
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Figure 103:   Power-Down Entry After WRITE with Auto Precharge (WRAP)  ...................................................... 191
Figure 104:   REFRESH to Power-Down Entry  .................................................................................................. 192
Figure 105:   ACTIVATE to Power-Down Entry  
................................................................................................. 192
Figure 106:   PRECHARGE to Power-Down Entry  ............................................................................................. 193
Figure 107:   MRS Command to Power-Down Entry  
......................................................................................... 193
Figure 108:   Power-Down Exit to Refresh to Power-Down Entry  ....................................................................... 194
Figure 109:   RESET Sequence ......................................................................................................................... 196
Figure 110:   On-Die Termination  ................................................................................................................... 197
Figure 111:   Dynamic ODT: ODT Asserted Before and After the WRITE, BC4  .................................................... 202
Figure 112:   Dynamic ODT: Without WRITE Command 
  .................................................................................. 202
Figure 113:   Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8  ............ 203
Figure 114:   Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 204
Figure 115:   Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 
.......................... 204
Figure 116:   Synchronous ODT  ...................................................................................................................... 206
Figure 117:   Synchronous ODT (BC4)  ............................................................................................................. 207
Figure 118:   ODT During READs  .................................................................................................................... 209
Figure 119:   Asynchronous ODT Timing with Fast ODT Transition  .................................................................. 211
Figure 120:   Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off ) Entry  ............ 213
Figure 121:   Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off ) Exit ............... 215
Figure 122:   Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 217
Figure 123:   Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping  
................... 217

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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List of Tables

Table 1:   Key Timing Parameters  .......................................................................................................................  1
Table 2:   Addressing  .........................................................................................................................................  2
Table 3:   78-Ball FBGA – x4, x8 Ball Descriptions  ..............................................................................................  19
Table 4:   96-Ball FBGA – x16 Ball Descriptions  .................................................................................................  21
Table 5:   Absolute Maximum Ratings  ..............................................................................................................  29
Table 6:   DDR3L Input/Output Capacitance  ....................................................................................................  30
Table 7:   Thermal Characteristics ....................................................................................................................  31
Table 8:   Thermal Impedance  .........................................................................................................................  32
Table 9:   Timing Parameters Used for I

DD

 Measurements – Clock Units  ............................................................  33

Table 10:   I

DD0

 Measurement Loop ..................................................................................................................  34

Table 11:   I

DD1

 Measurement Loop ..................................................................................................................  35

Table 12:   I

DD

 Measurement Conditions for Power-Down Currents ...................................................................  36

Table 13:   I

DD2N

 and I

DD3N

 Measurement Loop  ................................................................................................  37

Table 14:   I

DD2NT

 Measurement Loop  ..............................................................................................................  37

Table 15:   I

DD4R

 Measurement Loop  ................................................................................................................  38

Table 16:   I

DD4W

 Measurement Loop  ...............................................................................................................  39

Table 17:   I

DD5B

 Measurement Loop  ................................................................................................................  40

Table 18:   I

DD

 Measurement Conditions for I

DD6

, I

DD6ET

, and I

DD8

 ....................................................................  41

Table 19:   I

DD7

 Measurement Loop ..................................................................................................................  42

Table 20:   I

DD

 Maximum Limits Die Rev. E for 1.35/1.5V Operation ...................................................................  44

Table 21:   I

DD

 Maximum Limits Die Rev. N for 1.35V/1.5V Operation  ................................................................  45

Table 22:   I

DD

 Maximum Limits Die Rev. P for 1.35V/1.5V Operation .................................................................  47

Table 23:   DDR3L 1.35V DC Electrical Characteristics and Operating Conditions  ..............................................  49
Table 24:   DDR3L 1.35V DC Electrical Characteristics and Input Conditions  .....................................................  50
Table 25:   DDR3L 1.35V Input Switching Conditions – Command and Address  .................................................  51
Table 26:   DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) ..............................  52
Table 27:   DDR3L Control and Address Pins .....................................................................................................  54
Table 28:   DDR3L 1.35V Clock, Data, Strobe, and Mask Pins  
.............................................................................  54
Table 29:   DDR3L 1.35V – Minimum Required Time 

t

DVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...

 56

Table 30:   Single-Ended Input Slew Rate Definition ..........................................................................................  57
Table 31:   DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................  59
Table 32:   On-Die Termination DC Electrical Characteristics ............................................................................  60
Table 33:   1.35V R

TT

 Effective Impedance  ........................................................................................................  61

Table 34:   ODT Sensitivity Definition  ..............................................................................................................  62
Table 35:   ODT Temperature and Voltage Sensitivity
  ........................................................................................  62
Table 36:   ODT Timing Definitions ..................................................................................................................  63
Table 37:   DDR3L(1.35V) Reference Settings for ODT Timing Measurements  
....................................................  63
Table 38:   DDR3L 34 Ohm Driver Impedance Characteristics  ...........................................................................  67
Table 39:   DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations  ...........................................  68
Table 40:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.35V  .....................................  68

Table 41:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.45V  .....................................  68

Table 42:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.283  .....................................  69

Table 43:   DDR3L 34 Ohm Output Driver Sensitivity Definition  ........................................................................  69
Table 44:   DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity
  ..................................................  69
Table 45:   DDR3L 40 Ohm Driver Impedance Characteristics  ...........................................................................  70
Table 46:   DDR3L 40 Ohm Output Driver Sensitivity Definition  
........................................................................  70
Table 47:   40 Ohm Output Driver Voltage and Temperature Sensitivity ..............................................................  71
Table 48:   DDR3L Single-Ended Output Driver Characteristics  .........................................................................  72
Table 49:   DDR3L Differential Output Driver Characteristics  ............................................................................  73
Table 50:   DDR3L Differential Output Driver Characteristics V

OX(AC)

 .................................................................  74

4Gb: x4, x8, x16 DDR3L SDRAM

Description

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Table 51:   Single-Ended Output Slew Rate Definition  .......................................................................................  75
Table 52:   Differential Output Slew Rate Definition  ..........................................................................................  77
Table 53:   DDR3L-1066 Speed Bins ..................................................................................................................  78
Table 54:   DDR3L-1333 Speed Bins ..................................................................................................................  79
Table 55:   DDR3L-1600 Speed Bins ..................................................................................................................  80
Table 56:   DDR3L-1866 Speed Bins ..................................................................................................................  81
Table 57:   DDR3L-2133 Speed Bins ..................................................................................................................  82
Table 58:   Electrical Characteristics and AC Operating Conditions ....................................................................  83
Table 59:   Electrical Characteristics and AC Operating Conditions for Speed Extensions ....................................  93
Table 60:   DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based   ............... 103
Table 61:   DDR3L-800/1066 Derating Values 

t

IS/

t

IH – AC160/DC90-Based ....................................................... 104

Table 62:   DDR3L-800/1066/1333/1600 Derating Values for 

t

IS/

t

IH – AC135/DC90-Based  ................................ 104

Table 63:   DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based  ................................................ 104

Table 64:   DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL[AC]

) for Valid ADD/CMD Transition  . 105

Table 65:   DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based   ....................... 110
Table 66:   DDR3L Derating Values for 

t

DS/

t

DH – AC160/DC90-Based  .............................................................. 111

Table 67:   DDR3L Derating Values for 

t

DS/

t

DH – AC135/DC90-Based  .............................................................. 111

Table 68:   DDR3L Derating Values for 

t

DS/

t

DH – AC130/DC90-Based at 2V/ns ................................................. 112

Table 69:   DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL(AC)

) for Valid DQ Transition  ............. 113

Table 70:   Truth Table – Command ................................................................................................................. 118
Table 71:   Truth Table – CKE  .......................................................................................................................... 120
Table 72:   READ Command Summary  ............................................................................................................ 122
Table 73:   WRITE Command Summary  
.......................................................................................................... 122
Table 74:   READ Electrical Characteristics, DLL Disable Mode ......................................................................... 128
Table 75:   Write Leveling Matrix  ..................................................................................................................... 132
Table 76:   Burst Order .................................................................................................................................... 143
Table 77:   MPR Functional Description of MR3 Bits  ........................................................................................ 153
Table 78:   MPR Readouts and Burst Order Bit Mapping  ................................................................................... 154
Table 79:   Self Refresh Temperature and Auto Self Refresh Description  ............................................................ 186
Table 80:   Self Refresh Mode Summary  
........................................................................................................... 186
Table 81:   Command to Power-Down Entry Parameters  .................................................................................. 187
Table 82:   Power-Down Modes ....................................................................................................................... 188
Table 83:   Truth Table – ODT (Nominal)  ......................................................................................................... 198
Table 84:   ODT Parameters  
............................................................................................................................ 198
Table 85:   Write Leveling with Dynamic ODT Special Case  .............................................................................. 199
Table 86:   Dynamic ODT Specific Parameters  ................................................................................................. 200
Table 87:   Mode Registers for R

TT,nom

 ............................................................................................................. 200

Table 88:   Mode Registers for R

TT(WR)

 ............................................................................................................. 201

Table 89:   Timing Diagrams for Dynamic ODT ................................................................................................ 201
Table 90:   Synchronous ODT Parameters ........................................................................................................ 206
Table 91:   Asynchronous ODT Timing Parameters for All Speed Bins  ............................................................... 211
Table 92:   ODT Parameters for Power-Down (DLL Off ) Entry and Exit Transition Period  ................................... 213

4Gb: x4, x8, x16 DDR3L SDRAM

Description

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Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.

Automotive Applications.

 Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications.

 Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.

Customer Responsibility.

 Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.

Limited Warranty.

 In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

4Gb: x4, x8, x16 DDR3L SDRAM
Important Notes and Warnings

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION

Bank

active

Reading

Writing

Activating

Refreshing

Self

refresh

Idle

Active 

power-

down

ZQ

calibration

From any
state

Power
applied

Reset 

procedure

  Power 

on

Initial-

ization

MRS, MPR, 

write

leveling

Precharge

power-

down

Writing

Reading

Automatic
sequence

Command
sequence

Precharging

READ

READ

READ

READ AP

READ AP

READ AP

PRE, PREA

PRE,  PREA

PRE,  PREA

WRITE

WRITE

CKE L

CKE L

CKE L

WRITE

WRITE AP

WRITE AP

WRITE AP

PDE

PDE

PDX

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE

PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8 
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry

4Gb: x4, x8, x16 DDR3L SDRAM

State Diagram

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Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8

n

-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8

n

-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding 

n

-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-
mand, and address signals are registered at every positive edge of CK. Input data is reg-
istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-
erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad-
dress bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row pre-
charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T

is < 0°C or

>95°C.

Automotive Temperature

The Automotive temperature (AT) device requires that the case temperature not exceed
–40°C or 105°C. Micron specification requires the refresh rate to 4X when T

exceeds

95°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T

is < 0°C or

>95°C.

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.

• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[

n

:0]

. For example, 

1Gb: 

n

 = 12 (x16); 1Gb: 

n

 = 13 (x4,

x8); 2Gb: 

n

 = 13 (x16) and 2Gb: 

n

 = 14 (x4, x8); 4Gb: 

n

 = 14 (x16); and 4Gb: 

n

 = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1k

ȍ

* resistor.

– Connect UDQS# to V

DD

 via 1k

ȍ

* resistor.

– Connect UDM to V

DD

 via 1k

ȍ

* resistor.

– Connect DQ[15:8] individually to either V

SS

, V

DD

, or V

REF

 via 1k

ȍ

 resistors,* or float

DQ[15:8].

*If ODT is used, 1k

ȍ

 resistor should be changed to 4x that of the selected ODT.

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.

Figure 3: 1 Gig x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

16

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

11

Command 

decode

A[15:0]
BA[2:0]

16

Address
register

19

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(65,536 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank

control

logic

19

Bank 1

Bank 2

Bank 3

16

8

3

3

Refresh
counter

4

32

32

32

DQS, DQS#

Columns 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To pull-up/pull-down

networks

READ 

drivers

DQ[3:0]

READ

FIFO

and

data

MUX

Data

4

3

Bank 1

Bank 2

Bank 3

DM

DM

CK, CK#

DQS, DQS#

ZQ CAL

CS#

ZQ

RZQ

CK, CK#

RAS#

WE#

CAS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

OTF

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

 WRITE 

drivers

and 

input

logic

ODT

control

V

SSQ

A12

OTF

BC4

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Figure 4: 512 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

16

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

10

Command 

decode

A[15:0]
BA[2:0]

16

19

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(65,536  x 128 x 64)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank 

control

logic

19

Bank 1

Bank 2

Bank 3

16

7

3

3

Refresh
counter

8

64

64

64

DQS, DQS#

Columns 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read 

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

8

3

Bank 1

Bank 2

Bank 3

DM/TDQS
(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

ZQ

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT(WR)

R

TT,nom

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

BC4 (burst chop)

BC4

BC4

Write 

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128
x64)

ODT

control

Address
register

A12

V

SSQ

OTF

OTF

Figure 5: 256 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

13

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

10

Command 

decode

A[14:0]
BA[2:0]

15

Address
register

18

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

18

Bank 1

Bank 2

Bank 3

15

7

3

3

Refresh
counter

16

128

128

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ 

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

16

BC4 (burst chop)

3

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

ZQ

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

BC4

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

 WRITE 

drivers

and

input

logic

ODT

control

V

SSQ

A12

OTF

OTF

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

16

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1

2

3

4

6

7

8

9

5

V

SS

V

SS

V

DDQ

V

SSQ

V

REFDQ

NC

ODT

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SSQ

DQ2

NF, DQ6

V

DDQ

V

SS

V

DD

CS#

BA0

A3

A5

A7

RESET#

NC

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A0

A2

A9

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

V

DD

NF, DQ7

CK

CK#

A10/AP

A15

A12/BC#

A1

A11

A14

V

DD

V

DDQ

V

SSQ

V

SSQ

V

DDQ

NC

CKE

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SSQ

DQ3

V

SS

NF, DQ5

V

SS

V

DD

ZQ

V

REFCA

BA1

A4

A6

A8

A

B

C

D

E

F

G

H

J

K

L

M

N

Notes:

1. Ball descriptions listed in Table 3 (page 19) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

17

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Figure 7: 96-Ball FBGA – x16 (Top View)

1

2

3

4

6

7

8

9

5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

SS

V

DDQ

V

SSQ

V

REFDQ

NC

ODT

NC

V

SS

V

DD

V

SS

V

DD

V

SS

DQ13

V

DD

DQ11

V

DDQ

V

SSQ

DQ2

DQ6

V

DDQ

V

SS

V

DD

CS#

BA0

A3

A5

A7

RESET#

DQ15

V

SS

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

A0

A2

A9

A13

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

V

DD

DQ7

CK

CK#

A10/AP

NC

A12/BC#

A1

A11

A14

V

DDQ

DQ14

DQ10

V

SSQ

V

SSQ

DQ3

V

SS

DQ5

V

SS

V

DD

ZQ

V

REFCA

BA1

A4

A6

A8

V

SS

V

SSQ

V

DDQ

V

DD

V

DDQ

V

SSQ

V

SSQ

V

DDQ

NC

CKE

NC

V

SS

V

DD

V

SS

V

DD

V

SS

Notes:

1. Ball descriptions listed in Table 4 (page 21) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol

Type

Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input

Address inputs:

 Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 118).

BA[2:0]

Input

Bank address inputs:

 BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V

REFCA

.

CK, CK#

Input

Clock:

 CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock enable:

 CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/
disabled is dependent upon the DDR3 SDRAM configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-
bled during SELF REFRESH. CKE is referenced to V

REFCA

.

CS#

Input

Chip select:

 CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V

REFCA

.

DM

Input

Input data mask:

 DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT

Input

On-die termination:

 ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

.

RAS#, CAS#, WE#

Input

Command inputs:

 RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

.

RESET#

Input

Reset:

 RESET# is an active LOW CMOS input referenced to V

SS

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 

 0.8 × V

DD

 and

DC LOW 

 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol

Type

Description

DQ[3:0]

I/O

Data input/output:

 Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to V

REFDQ

.

DQ[7:0]

I/O

Data input/output:

 Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to V

REFDQ

.

DQS, DQS#

I/O

Data strobe:

 Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS#

Output

Termination data strobe: 

Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.

V

DD

Supply

Power supply:

 1.5V ±0.075V.

V

DDQ

Supply

DQ power supply:

 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

V

REFCA

Supply

Reference voltage for control, command, and address:

 V

REFCA

 must be

maintained at all times (including self refresh) for proper device operation.

V

REFDQ

Supply

Reference voltage for data:

 V

REFDQ

 must be maintained at all times (excluding self

refresh) for proper device operation.

V

SS

Supply

Ground.

V

SSQ

Supply

DQ ground:

 Isolated on the device for improved noise immunity.

ZQ

Reference

External reference ball for output drive calibration:

 This ball is tied to an

external 240

˖

 resistor (RZQ), which is tied to V

SSQ

.

NC

No connect:

 These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF

No function:

 When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

20

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol

Type

Description

A[14:13], A12/BC#,

A11, A10/AP, A[9:0]

Input

Address inputs: 

Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 118).

BA[2:0]

Input

Bank address inputs:

 BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V

REFCA

.

CK, CK#

Input

Clock:

 CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock enable:

 CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for power-
down entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to V

REFCA

.

CS#

Input

Chip select:

 CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V

REFCA

.

LDM

Input

Input data mask:

 LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

.

ODT

Input

On-die termination: 

ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to V

REFCA

.

RAS#, CAS#, WE#

Input

Command inputs:

 RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

.

RESET#

Input

Reset:

 RESET# is an active LOW CMOS input referenced to V

SS

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 

 0.8 × V

DD

 and

DC LOW 

 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

21

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)

Symbol

Type

Description

UDM

Input

Input data mask:

 UDM is an upper-byte, input mask signal for write data. Upper-

byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to V

REFDQ

.

DQ[7:0]

I/O

Data input/output:

 Lower byte of bidirectional data bus for the x16 configuration.

DQ[7:0] are referenced to V

REFDQ

.

DQ[15:8]

I/O

Data input/output:

 Upper byte of bidirectional data bus for the x16 configuration.

DQ[15:8] are referenced to V

REFDQ

.

LDQS, LDQS#

I/O

Lower byte data strobe:

 Output with read data. Edge-aligned with read data.

Input with write data. Center-aligned to write data.

UDQS, UDQS#

I/O

Upper byte data strobe:

 Output with read data. Edge-aligned with read data.

Input with write data. DQS is center-aligned to write data.

V

DD

Supply

Power supply:

 1.5V ±0.075V.

V

DDQ

Supply

DQ power supply:

 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

V

REFCA

Supply

Reference voltage for control, command, and address:

 V

REFCA

 must be

maintained at all times (including self refresh) for proper device operation.

V

REFDQ

Supply

Reference voltage for data:

 V

REFDQ

 must be maintained at all times (excluding self

refresh) for proper device operation.

V

SS

Supply

Ground.

V

SSQ

Supply

DQ ground:

 Isolated on the device for improved noise immunity.

ZQ

Reference

External reference ball for output drive calibration:

 This ball is tied to an

external 240

˖

 resistor (RZQ), which is tied to V

SSQ

.

NC

No connect:

 These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

22

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Package Dimensions

Figure 8: 78-Ball FBGA – x4, x8 (RH)

6.4 CTR

9 ±0.1

0.8 TYP

10.5 ±0.1

9.6 CTR

0.8 TYP

1.1 ±0.1

0.25 MIN

1

A

2

3

7

8

9

B

C

D

E

F

G

H

J

K

L

M

N

0.12 A

A

0.155

78X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.35 SMD
ball pads.

Seating plane

Ball A1 ID
(covered by SR)

Ball A1 ID

1.8 CTR

Nonconductive

overmold

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

23

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Figure 9: 78-Ball FBGA – x4, x8 (RG)

1.8 CTR

nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

A

0.25 MIN

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

9.6 CTR

10.6 ±0.1

78X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

24

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Figure 10: 78-Ball FBGA – x4, x8 (DA)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

0.29 MIN

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

9.6 CTR

10.5 ±0.1

78X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

A

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

25

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Figure 11: 96-Ball FBGA – x16 (HA)

Ball A1 Index

Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.

14 ±0.1

0.8 TYP

1.1 ±0.1

12 CTR

Ball A1 Index
(covered by SR)

0.8 TYP

9 ±0.1

0.25 MIN

6.4 CTR

96X Ø0.45

9 8 7 

3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

0.12 A

Seating plane

1.8 CTR

Nonconductive

overmold

0.155

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

26

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Figure 12: 96-Ball FBGA – x16 (LY)

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

A

0.29 MIN

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

12 CTR

13.5 ±0.1

96X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42
SMD ball pads.

0.8 TYP

1.8 CTR

Nonconductive

overmold

0.155

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

27

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Figure 13: 96-Ball FBGA – x16 (TW)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

12 CTR

14 ±0.1

96X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

Notes:

1. All dimensions are in millimeters.
2. Material composition: Pb-free SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

28

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© 2017 Micron Technology, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

Electrical Specifications

Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.

Table 5: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

V

DD

V

DD

 supply voltage relative to V

SS

–0.4

1.975

V

1

V

DDQ

V

DD

 supply voltage relative to V

SSQ

–0.4

1.975

V

 

V

IN

, V

OUT

Voltage on any pin relative to V

SS

–0.4

1.975

V

 

T

C

Operating case temperature – Commercial

0

95

°C

2, 3

Operating case temperature – Industrial

–40

95

°C

2, 3

Operating case temperature – Automotive

–40

105

°C

2, 3

T

STG

Storage temperature

–55

150

°C

 

Notes:

1. V

DD

 and V

DDQ

 must be within 300mV of each other at all times, and V

REF

 must not be

greater than 0.6 × V

DDQ

. When V

DD

 and V

DDQ

 are <500mV, V

REF

 can be 

300mV.

2. MAX operating case temperature. T

C

 is measured in the center of the package.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T

C

 dur-

ing operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications

09005aef85af8fa8
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Input/Output Capacitance

Table 6: DDR3L Input/Output Capacitance

Note 1 applies to the entire table

Capacitance
Parameters

Sym

DDR3L

-800

DDR3L

-1066

DDR3L

-1333

DDR3L

-1600

DDR3L

-1866

DDR3L

-2133

Unit Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

CK and CK#

C

CK

0.8

1.6

0.8

1.6

0.8

1.4

0.8

1.4

0.8

1.3

0.8

1.3

pF

 

˂

C: CK to CK#

C

DCK

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

pF

 

Single-end
I/O: DQ, DM

C

IO

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1.4

2.1

pF

2

Differential
I/O: DQS,
DQS#, TDQS,
TDQS#

C

IO

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1.4

2.1

pF

3

˂

C: DQS to

DQS#, TDQS,
TDQS#

C

DDQS

0.0

0.2

0.0

0.2

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

pF

3

˂

C: DQ to

DQS

C

DIO

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

pF

4

Inputs (CTRL,
CMD, ADDR)

C

I

0.75

1.3

0.75

1.3

0.75

1.3

0.75

1.2

0.75

1.2

0.75

1.2

pF

5

˂

C: CTRL to

CK

C

DI_CTRL

–0.5

0.3

–0.5

0.3

–0.4

0.2

–0.4

0.2

–0.4

0.2

–0.4

0.2

pF

6

˂

C:

CMD_ADDR
to CK

C

DI_CMD

_ADDR

–0.5

0.5

–0.5

0.5

–0.4

0.4

–0.4

0.4

–0.4

0.4

–0.4

0.4

pF

7

ZQ pin
capacitance

C

ZQ

3.0

3.0

3.0

3.0

3.0

3.0

pF

 

Reset pin
capacitance

C

RE

3.0

3.0

3.0

3.0

3.0

3.0

pF

 

Notes:

1. V

DD

 = 1.35V (1.283–1.45V), V

DDQ

 = V

DD

, V

REF

 = V

SS

= 100 MHz, T

= 25°C. V

OUT(DC)

 = 0.5

× V

DDQ

, V

OUT

 = 0.1V (peak-to-peak).

2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. C

DDQS

 is for DQS vs. DQS# and TDQS vs. TDQS# separately.

4. C

DIO

 = C

IO(DQ)

 - 0.5 × (C

IO(DQS)

 + C

IO(DQS#)

).

5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =

A[

n

:0], BA[2:0].

6. C

DI_CTRL

 = C

I(CTRL)

 - 0.5 × (C

CK(CK)

 + C

CK(CK#)

).

7. C

DI_CMD_ADDR

 = C

I(CMD_ADDR)

 - 0.5 × (C

CK(CK)

 + C

CK(CK#)

).

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Thermal Characteristics

Table 7: Thermal Characteristics

Notes 1–3 apply to entire table

Parameter

Symbol

Value

Units

Notes

Operating temperature - Commercial

T

C

0 to 85

°C

Operating temperature - Industrial

T

C

-40 to 95

°C

4

Operating temperature - Automotive

T

C

-40 to105

°C

5

Notes:

1. MAX operating case temperature T

C

 is measured in the center of the package, as shown

below.

2. A thermal solution must be designed to ensure that the device does not exceed the

maximum T

C

 during operation.

3. Device functionality is not guaranteed if the device exceeds maximum T

C

 during

operation.

4. If T

C

 exceeds 85°C, but is less than 95°C, the DRAM must be refreshed manually at 2x re-

fresh, which is a 3.9μs interval refresh rate. The use of self refresh temperature (SRT) or
automatic self refresh (ASR), must be enabled.

5. If T

C

 exceeds 95°C, but less than 105°C, the DRAM must be refreshed manually at 4x re-

fresh, which is a 1.95μs interval refresh rate. The use of self refresh temperature (SRT) or
automatic self refresh (ASR), must be enabled.

Figure 14: Thermal Measurement Point

(L/2)

L

W

(W/2)

Tc test point

4Gb: x4, x8, x16 DDR3L SDRAM

Thermal Characteristics

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Table 8: Thermal Impedance

Die Rev.

Package

Substrate

ˆ

ˆ

 JA (°C/W)

Airflow =

0m/s

ˆ

 JA (°C/W)

Airflow =

1m/s

ˆ

 JA (°C/W)

Airflow =

2m/s

ˆ

 JB (°C/W)

ˆ

 JC (°C/W)

E

78-ball

Low conduc-

tivity

63.7

49.6

44.0

N/A

4.0

High con-

ductivity

42.3

35.7

32.9

29.7

N/A

96-ball

Low conduc-

tivity

50.4

39.2

35.1

N/A

3.9

High con-

ductivity

31.3

26.1

24.3

19.2

N/A

N

78-ball

Low conduc-

tivity

61.7

47.6

42.6

N/A

5.7

High con-

ductivity

40.6

33.4

31.2

19.1

N/A

96-ball

Low conduc-

tivity

52.1

42.1

38.4

N/A

5.6

High con-

ductivity

32.6

27.9

26.5

12.6

N/A

P

78-ball

Low conduc-

tivity

88.3

70.6

64.1

N/A

10.8

High con-

ductivity

56.5

48.4

45.7

25.5

N/A

96-ball

Low conduc-

tivity

54.3

42.1

37.3

N/A

4.6

High con-

ductivity

34.8

29.0

26.9

16.9

N/A

Note:

1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

4Gb: x4, x8, x16 DDR3L SDRAM

Thermal Characteristics

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Electrical Specifications – I

DD

 Specifications and Conditions

Within the following I

DD

 measurement tables, the following definitions and conditions

are used, unless stated otherwise:

• LOW: V

IN

 

”

 V

IL(AC)max

; HIGH: V

IN

 

•

 V

IH(AC)min

.

• Midlevel: Inputs are V

REF

 = V

DD

/2.

• R

ON

 set to RZQ/7 (34

ȍ

).

• R

TT,nom

 set to RZQ/6 (40

ȍ

).

• R

TT(WR)

 set to RZQ/2 (120

ȍ

).

• Q

OFF

 is enabled in MR1.

• ODT is enabled in MR1 (R

TT,nom

) and MR2 (R

TT(WR)

).

• TDQS is disabled in MR1.
• External DQ/DQS/DM load resistor is 25

ȍ

 to V

DDQ

/2.

• Burst lengths are BL8 fixed.
• AL equals 0 (except in I

DD7

).

• I

DD

 specifications are tested after the device is properly initialized.

• Input slew rate is specified by AC parametric test conditions.
• Optional ASR is disabled.
• Read burst type uses nibble sequential (MR0[3] = 0).
• Loop patterns must be executed at least once before current measurements begin.

Table 9: Timing Parameters Used for I

DD

 Measurements – Clock Units

I

DD

Parameter

DDR3L

-800

DDR3L

-1066

DDR3L

-1333

DDR3L

-1600

DDR3L

-1866

DDR3L

-2133

Unit

-25E

-25

-187E

-187

-15E

-15

-125E

-125

-107

-093

5-5-5

6-6-6

7-7-7

8-8-8

9-9-9

10-10-10 10-10-10 11-11-11 13-13-13 14-14-14

t

CK (MIN) I

DD

2.5

1.875

1.5

1.25

1.07

0.938

ns

CL I

DD

5

6

7

8

9

10

10

11

13

14

CK

t

RCD (MIN) I

DD

5

6

7

8

9

10

10

11

13

14

CK

t

RC (MIN) I

DD

20

21

27

28

33

34

38

39

45

50

CK

t

RAS (MIN) I

DD

15

15

20

20

24

24

28

28

32

36

CK

t

RP (MIN)

5

6

7

8

9

10

10

11

13

14

CK

t

FAW

x4, x8

16

16

20

20

20

20

24

24

26

27

CK

x16

20

20

27

27

30

30

32

32

33

38

CK

t

RRD

I

DD

x4, x8

4

4

4

4

4

4

5

5

5

6

CK

x16

4

4

6

6

5

5

6

6

6

7

CK

t

RFC

1Gb

44

44

59

59

74

74

88

88

103

118

CK

2Gb

64

64

86

86

107

107

128

128

150

172

CK

4Gb

104

104

139

139

174

174

208

208

243

279

CK

8Gb

140

140

187

187

234

234

280

280

328

375

CK

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 10: I

DD0

 Measurement Loop

CK, CK#

CKE

Sub-

Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D

1

0

0

0

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

0

0

4

D#

1

1

1

1

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RAS - 1; truncate if needed

n

RAS

PRE

0

0

1

0

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RC - 1; truncate if needed

n

RC

ACT

0

0

1

1

0

0

0

0

0

F

0

n

RC  +  1

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  2

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  3

D#

1

1

1

1

0

0

0

0

0

F

0

n

RC  +  4

D#

1

1

1

1

0

0

0

0

0

F

0

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC - 1 + 

n

RAS -1; truncate if needed

n

RC + 

n

RAS

PRE

0

0

1

0

0

0

0

0

0

F

0

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 2 × RC - 1; truncate if needed

1

2 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 1

2

4 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 2

3

6 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 3

4

8 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 4

5

10 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 5

6

12 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 6

7

14 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. Only selected bank (single) active.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 11: I

DD1

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

2

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D

1

0

0

0

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

0

0

4

D#

1

1

1

1

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RCD - 1; truncate if needed

n

RCD

RD

0

1

0

1

0

0

0

0

0

0

0

00000000

 

Repeat cycles 1 through 4 until 

n

RAS - 1; truncate if needed

n

RAS

PRE

0

0

1

0

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RC - 1; truncate if needed

n

RC

ACT

0

0

1

1

0

0

0

0

0

F

0

n

RC  +  1

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  2

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  3

D#

1

1

1

1

0

0

0

0

0

F

0

n

RC  +  4

D#

1

1

1

1

0

0

0

0

0

F

0

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC + 

n

RCD - 1; truncate if needed

n

RC + 

n

RCD

RD

0

1

0

1

0

0

0

0

0

F

0

00110011

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC + 

n

RAS - 1; truncate if needed

n

RC + 

n

RAS

PRE

0

0

1

0

0

0

0

0

0

F

0

 Repeat 

cycle 

n

RC + 1 through 

n

RC + 4 until 2 × 

n

RC - 1; truncate if needed

1

2 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 1

2

4 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 2

3

6 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 3

4

8 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 4

5

10 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 5

6

12 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 6

7

14 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. Only selected bank (single) active.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 12: I

DD

 Measurement Conditions for Power-Down Currents

Name

I

DD2P0

 Precharge

Power-Down

Current (Slow Exit)

1

I

DD2P1

 Precharge

Power-Down

Current (Fast Exit)

1

I

DD2Q

 Precharge

Quiet

Standby Current

I

DD3P

 Active

Power-Down

Current

Timing pattern

N/A

N/A

N/A

N/A

CKE

LOW

LOW

HIGH

LOW

External clock

Toggling

Toggling

Toggling

Toggling

t

CK

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

RC

N/A

N/A

N/A

N/A

t

RAS

N/A

N/A

N/A

N/A

t

RCD

N/A

N/A

N/A

N/A

t

RRD

N/A

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

N/A

CL

N/A

N/A

N/A

N/A

AL

N/A

N/A

N/A

N/A

CS#

HIGH

HIGH

HIGH

HIGH

Command inputs

LOW

LOW

LOW

LOW

Row/column addr

LOW

LOW

LOW

LOW

Bank addresses

LOW

LOW

LOW

LOW

DM

LOW

LOW

LOW

LOW

Data I/O

Midlevel

Midlevel

Midlevel

Midlevel

Output buffer DQ, DQS

Enabled

Enabled

Enabled

Enabled

ODT

2

Enabled, off

Enabled, off

Enabled, off

Enabled, off

Burst length

8

8

8

8

Active banks

None

None

None

All

Idle banks

All

All

All

None

Special notes

N/A

N/A

N/A

N/A

Notes:

1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast

exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).

2. “Enabled, off” means the MR bits are enabled, but the signal is LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 13: I

DD2N

 and I

DD3N

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

D

1

0

0

0

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D#

1

1

1

1

0

0

0

0

0

F

0

3

D#

1

1

1

1

0

0

0

0

0

F

0

1

4–7

Repeat sub-loop 0, use BA[2:0] = 1

2

8–11

Repeat sub-loop 0, use BA[2:0] = 2

3

12–15

Repeat sub-loop 0, use BA[2:0] = 3

4

16–19

Repeat sub-loop 0, use BA[2:0] = 4

5

20–23

Repeat sub-loop 0, use BA[2:0] = 5

6

24–27

Repeat sub-loop 0, use BA[2:0] = 6

7

28–31

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed during I

DD2N

; all banks open during I

DD3N

.

Table 14: I

DD2NT

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

D

1

0

0

0

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D#

1

1

1

1

0

0

0

0

0

F

0

3

D#

1

1

1

1

0

0

0

0

0

F

0

1

4–7

Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0

2

8–11

Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1

3

12–15

Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1

4

16–19

Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0

5

20–23

Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0

6

24–27

Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1

7

28–31

Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 15: I

DD4R

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

0

0

RD

0

1

0

1

0

0

0

0

0

0

0

00000000

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D#

1

1

1

1

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

0

0

4

RD

0

1

0

1

0

0

0

0

0

F

0

00110011

5

D

1

0

0

0

0

0

0

0

0

F

0

6

D#

1

1

1

1

0

0

0

0

0

F

0

7

D#

1

1

1

1

0

0

0

0

0

F

0

1

8–15

Repeat sub-loop 0, use BA[2:0] = 1

2

16–23

Repeat sub-loop 0, use BA[2:0] = 2

3

24–31

Repeat sub-loop 0, use BA[2:0] = 3

4

32–39

Repeat sub-loop 0, use BA[2:0] = 4

5

40–47

Repeat sub-loop 0, use BA[2:0] = 5

6

48–55

Repeat sub-loop 0, use BA[2:0] = 6

7

56–63

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. All banks open.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
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Table 16: I

DD4W

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

4

T

oggling

Static HIGH

0

0

WR

0

1

0

0

1

0

0

0

0

0

0

00000000

1

D

1

0

0

0

1

0

0

0

0

0

0

2

D#

1

1

1

1

1

0

0

0

0

0

0

3

D#

1

1

1

1

1

0

0

0

0

0

0

4

WR

0

1

0

0

1

0

0

0

0

F

0

00110011

5

D

1

0

0

0

1

0

0

0

0

F

0

6

D#

1

1

1

1

1

0

0

0

0

F

0

7

D#

1

1

1

1

1

0

0

0

0

F

0

1

8–15

Repeat sub-loop 0, use BA[2:0] = 1

2

16–23

Repeat sub-loop 0, use BA[2:0] = 2

3

24–31

Repeat sub-loop 0, use BA[2:0] = 3

4

32–39

Repeat sub-loop 0, use BA[2:0] = 4

5

40–47

Repeat sub-loop 0, use BA[2:0] = 5

6

48–55

Repeat sub-loop 0, use BA[2:0] = 6

7

56–63

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the WR command.
4. All banks open.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
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Table 17: I

DD5B

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

REF

0

0

0

1

0

0

0

0

0

0

0

1a

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D

1

0

0

0

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

F

0

4

D#

1

1

1

1

0

0

0

0

0

F

0

1b

5–8

Repeat sub-loop 1a, use BA[2:0] = 1

1c

9–12

Repeat sub-loop 1a, use BA[2:0] = 2

1d

13–16

Repeat sub-loop 1a, use BA[2:0] = 3

1e

17–20

Repeat sub-loop 1a, use BA[2:0] = 4

1f

21–24

Repeat sub-loop 1a, use BA[2:0] = 5

1g

25–28

Repeat sub-loop 1a, use BA[2:0] = 6

1h

29–32

Repeat sub-loop 1a, use BA[2:0] = 7

2

33–

n

RFC - 1

Repeat sub-loop 1a through 1h until 

n

RFC - 1; truncate if needed

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 18: I

DD

 Measurement Conditions for I

DD6

, I

DD6ET

, and I

DD8

I

DD

 Test

I

DD6

: Self Refresh Current

Normal Temperature Range

T

C

 = 0°C to +85°C

I

DD6ET

: Self Refresh Current

Extended Temperature Range

T

C

 = 0°C to +95°C

I

DD8

: Reset

2

CKE

LOW

LOW

Midlevel

External clock

Off, CK and CK# = LOW

Off, CK and CK# = LOW

Midlevel

t

CK

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

t

RAS

N/A

N/A

N/A

t

RCD

N/A

N/A

N/A

t

RRD

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

CL

N/A

N/A

N/A

AL

N/A

N/A

N/A

CS#

Midlevel

Midlevel

Midlevel

Command inputs

Midlevel

Midlevel

Midlevel

Row/column addresses

Midlevel

Midlevel

Midlevel

Bank addresses

Midlevel

Midlevel

Midlevel

Data I/O

Midlevel

Midlevel

Midlevel

Output buffer DQ, DQS

Enabled

Enabled

Midlevel

ODT

1

Enabled, midlevel

Enabled, midlevel

Midlevel

Burst length

N/A

N/A

N/A

Active banks

N/A

N/A

None

Idle banks

N/A

N/A

All

SRT

Disabled (normal)

Enabled (extended)

N/A

ASR

Disabled

Disabled

N/A

Notes:

1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable

and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns + 

t

RFC.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 19: I

DD7

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

1

RDA

0

1

0

1

0

0

0

1

0

0

0

00000000

2

D

1

0

0

0

0

0

0

0

0

0

0

3

Repeat cycle 2 until 

n

RRD - 1

1

n

RRD

ACT

0

0

1

1

0

1

0

0

0

F

0

n

RRD + 1

RDA

0

1

0

1

0

1

0

1

0

F

0

00110011

n

RRD + 2

D

1

0

0

0

0

1

0

0

0

F

0

n

RRD + 3

Repeat cycle 

n

RRD + 2 until 2 × 

n

RRD - 1

2

2 × 

n

RRD

Repeat sub-loop 0, use BA[2:0] = 2

3

3 × 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 3

4

4 × 

n

RRD

D

1

0

0

0

0

3

0

0

0

F

0

4 × 

n

RRD + 1

Repeat cycle 4 × 

n

RRD until 

n

FAW - 1, if needed

5

n

FAW

Repeat sub-loop 0, use BA[2:0] = 4

6

n

FAW + 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 5

7

n

FAW + 2 × 

n

RRD

Repeat sub-loop 0, use BA[2:0] = 6

8

n

FAW + 3 × 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 7

9

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

7

0

0

0

F

0

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 

n

FAW + 4 × 

n

RRD until 2 × 

n

FAW - 1, if needed

10

2 × 

n

FAW

ACT

0

0

1

1

0

0

0

0

0

F

0

2 × 

n

FAW  +  1

RDA

0

1

0

1

0

0

0

1

0

F

0

00110011

2 × 

n

FAW  +  2

D

1

0

0

0

0

0

0

0

0

F

0

2 × 

n

FAW + 3

Repeat cycle 2 × 

n

FAW + 2 until 2 × 

n

FAW + 

n

RRD - 1

11

2 × 

n

FAW + 

n

RRD

ACT

0

0

1

1

0

1

0

0

0

0

0

2 × 

n

FAW + 

n

RRD + 1

RDA

0

1

0

1

0

1

0

1

0

0

0

00000000

2 × 

n

FAW + 

n

RRD + 2

D

1

0

0

0

0

1

0

0

0

0

0

2 × 

n

FAW + 

n

RRD + 3

Repeat cycle 2 × 

n

FAW + 

n

RRD + 2 until 2 × 

n

FAW + 2 × 

n

RRD - 1

12

2 × 

n

FAW + 2 × 

n

RRD

Repeat sub-loop 10, use BA[2:0] = 2

13

2 × 

n

FAW + 3 × 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 3

14

2 × 

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

3

0

0

0

0

0

2 × 

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 2 × 

n

FAW + 4 × 

n

RRD until 3 × 

n

FAW - 1, if needed

15

3 × 

n

FAW

Repeat sub-loop 10, use BA[2:0] = 4

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 19: I

DD7

 Measurement Loop (Continued)

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

16

3 × 

n

FAW + 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 5

17

3 × 

n

FAW + 2 × 

n

RRD

Repeat sub-loop 10, use BA[2:0] = 6

18

3 × 

n

FAW + 3 × 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 7

19

3 × 

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

7

0

0

0

0

0

3 × 

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 3 × 

n

FAW + 4 × 

n

RRD until 4 × 

n

FAW - 1, if needed

Notes:

1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. AL = CL-1.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Electrical Characteristics – Operating I

DD

 Specifications

Table 20: I

DD

 Maximum Limits Die Rev. E for 1.35/1.5V Operation

Speed Bin

DDR3/3L

-1066

DDR3/3L

-1333

DDR3/3L

-1600

DDR3/3L

-1866

Units

Notes

Parameter

Symbol

Width

Operating current 0: One bank
ACTIVATE-to-PRECHARGE

I

DD0

x4, x8

44

47

55

62

mA

1, 2

x16

55

58

66

73

mA

1, 2

Operating current 1: One bank
ACTIVATE-to-READ-to-PRECHARGE

I

DD1

x4

53

57

61

65

mA

1, 2

x8

59

62

66

70

mA

1, 2

x16

80

84

87

91

mA

1, 2

Precharge power-down current:
Slow exit

I

DD2P0

All

18

18

18

18

mA

1, 2

Precharge power-down current:
Fast exit

I

DD2P1

All

26

28

32

37

mA

1, 2

Precharge quiet standby current

I

DD2Q

All

27

28

32

35

mA

1, 2

Precharge standby current

I

DD2N

All

28

29

32

35

mA

1, 2

Precharge standby ODT current

I

DD2NT

x4, x8

32

35

39

42

mA

1, 2

x16

35

39

42

45

mA

1, 2

Active power-down current

I

DD3P

All

32

35

38

41

mA

1, 2

Active standby current

I

DD3N

x4, x8

32

35

38

41

mA

1, 2

x16

41

45

47

49

mA

1, 2

Burst read operating current

I

DD4R

x4

113

130

147

164

mA

1, 2

x8

123

140

157

174

mA

1, 2

x16

185

202

235

252

mA

1, 2

Burst write operating current

I

DD4W

x4

87

103

118

133

mA

1, 2

x8

95

110

125

141

mA

1, 2

x16

137

152

171

190

mA

1, 2

Burst refresh current

I

DD5B

All

224

228

235

242

mA

1, 2

Room temperature self refresh

I

DD6

All

20

20

20

20

mA

1, 2, 3

Extended temperature self refresh

I

DD6ET

All

25

25

25

25

mA

2, 4

All banks interleaved read current

I

DD7

x4, x8

160

190

220

251

mA

1, 2

x16

198

217

243

274

mA

1, 2

Reset current

I

DD8

All

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

 T

C

 

 +85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

Table 21: I

DD

 Maximum Limits Die Rev. N for 1.35V/1.5V Operation

Speed Bin

DDR3/3L

-1066

DDR3/3L

-1333

DDR3/3L

-1600

DDR3/3L

-1866

DDR3/3L

-2133

Units

Notes

Parameter

Symbol Width

Operating current 0: One bank
ACTIVATE-to-PRECHARGE

I

DD0

x4, x8

42

45

47

49

51

mA

1, 2

x16

52

55

57

59

61

mA

1, 2

Operating current 1: One bank
ACTIVATE-to-READ-to-PRE-
CHARGE

I

DD1

x4

50

53

56

59

62

mA

1, 2

x8

55

58

61

64

67

mA

1, 2

x16

75

78

81

84

87

mA

1, 2

Precharge power-down cur-
rent: Slow exit

I

DD2P0

All

8

8

8

8

8

mA

1, 2

Precharge power-down cur-
rent: Fast exit

I

DD2P1

All

10

12

14

16

18

mA

1, 2

Precharge quiet standby cur-
rent

I

DD2Q

All

20

22

24

26

28

mA

1, 2

Precharge standby current

I

DD2N

All

20

22

24

26

28

mA

1, 2

Precharge standby ODT current

I

DD2NT

x4, x8

24

26

28

30

32

mA

1, 2

x16

27

29

31

33

35

mA

1, 2

Active power-down current

I

DD3P

All

22

24

26

28

30

mA

1, 2

Active standby current

I

DD3N

x4, x8

26

28

30

32

34

mA

1, 2

x16

34

36

38

40

42

mA

1, 2

Burst read operating current

I

DD4R

x4

65

75

85

95

105

mA

1, 2

x8

75

85

95

105

115

mA

1, 2

x16

135

145

155

165

175

mA

1, 2

Burst write operating current

I

DD4W

x4

65

75

85

95

105

mA

1, 2

x8

75

85

95

105

115

mA

1, 2

x16

135

145

155

165

175

mA

1, 2

Burst refresh current

I

DD5B

All

165

170

175

180

185

mA

1, 2

Room temperature self refresh

I

DD6

All

12

12

12

12

12

mA

1, 2, 3

Extended temperature self re-
fresh

I

DD6ET

All

16

16

16

16

16

mA

2, 4

All banks interleaved read cur-
rent

I

DD7

x4, x8

110

120

130

140

150

mA

1, 2

x16

170

180

190

200

210

mA

1, 2

Reset current

I

DD8

All

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

09005aef85af8fa8
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5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

 T

C

 

 85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

09005aef85af8fa8
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Table 22: I

DD

 Maximum Limits Die Rev. P for 1.35V/1.5V Operation

Speed Bin

DDR3/3L

-1600

DDR3/3L

-1866

DDR3/3L

-2133

Units

Notes

Parameter

Symbol

Width

Operating current 0: One bank ACTI-
VATE-to-PRECHARGE

I

DD0

x4, x8

28

29

31

mA

1, 2

X16

32

32

34

Operating current 1: One bank ACTI-
VATE-to-READ-to-PRECHARGE

I

DD1

x4, x8

43

44

47

mA

1, 2

x16

45

46

54

Precharge power-down current: Slow
exit

I

DD2P0

x4, x8

10

11

12

mA

1, 2

x16

12

12

12

Precharge power-down current: Fast
exit

I

DD2P1

x4, x8

11

11

13

mA

1, 2

x16

12

12

14

Precharge quiet standby current

I

DD2Q

ALL

15

15

17

mA

1, 2

Precharge standby current

I

DD2N

x4, x8

16

17

22

mA

1, 2

x16

17

17

22

Precharge standby ODT current

I

DD2NT

x4, x8

20

22

27

mA

1, 2

x16

22

23

28

Active power-down current

I

DD3P

x4,x8

15

15

17

mA

1, 2

x16

17

17

19

Active standby current

I

DD3N

x4, x8

20

21

23

mA

1, 2

x16

22

23

25

Burst read operating current

I

DD4R

x4, x8

90

90

110

mA

1, 2

x16

110

120

130

Burst write operating current

I

DD4W

x4, x8

90

90

110

mA

1, 2

16

120

130

140

Burst refresh current

I

DD5B

x4, x8

152

152

160

mA

1, 2

x16

156

156

160

Self refresh

I

DD6

ALL

15

15

15

mA

1, 2, 3

Extended temperature self refresh

I

DD6ET

ALL

23

23

23

mA

2, 4

All banks interleaved read current

I

DD7

x4, x8

130

146

150

mA

1, 2

x16

132

147

160

Reset current

I

DD8

All

I

DD2P

 + 2mA I

DD2P

 + 2mA I

DD2P

 + 2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

 T

C

 

 +85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

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5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

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Electrical Specifications – DC and AC

DC Operating Conditions

Table 23: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Nom

Max

Unit

Notes

Supply voltage

V

DD

1.283

1.35

1.45

V

1–7

I/O supply voltage

V

DDQ

1.283

1.35

1.45

V

1–7

Input leakage current
Any input 0V 

 V

IN

 

 V

DD

, V

REF

 pin 0V 

 V

IN

 

 1.1V

(All other pins not under test = 0V)

I

I

–2

2

μA

 

V

REF

 supply leakage current

V

REFDQ

 = V

DD

/2 or V

REFCA

 = V

DD

/2

(All other pins not under test = 0V)

I

VREF

–1

1

μA

8, 9

Notes:

1. V

DD

 and V

DDQ

 must track one another. V

DDQ

 must be 

 V

DD

. V

SS

 = V

SSQ

.

2. V

DD

 and V

DDQ

 may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the

DC (0 Hz to 250 kHz) specifications. V

DD

 and V

DDQ

 must be at same level for valid AC

timing parameters.

3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average

of V

DD

/V

DDQ

(t) over a very long period of time (for example, 1 second).

4. Under these supply voltages, the device operates to this DDR3L specification.
5. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
6. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifi-

cations under the same speed timings as defined for this device.

7. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is

in reset while V

DD

 and V

DDQ

 are changed for DDR3 operation (see VDD Voltage Switch-

ing (page 139)).

8. The minimum limit requirement is for testing purposes. The leakage current on the V

REF

pin should be minimal.

9. V

REF

 (see Table 24).

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

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Input Operating Conditions

Table 24: DDR3L 1.35V DC Electrical Characteristics and Input Conditions

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Nom

Max

Unit

Notes

V

IN

 low; DC/commands/address busses

V

IL

V

SS

N/A

See Table 25

V

 

V

IN

 high; DC/commands/address busses

V

IH

See Table 25

N/A

V

DD

V

 

Input reference voltage command/address bus

V

REFCA(DC)

0.49 × V

DD

0.5 × V

DD

0.51 × V

DD

V

1, 2

I/O reference voltage DQ bus

V

REFDQ(DC)

0.49 × V

DD

0.5 × V

DD

0.51 × V

DD

V

2, 3

I/O reference voltage DQ bus in SELF REFRESH

V

REFDQ(SR)

V

SS

0.5 × V

DD

V

DD

V

4

Command/address termination voltage
(system level, not direct DRAM input)

V

TT

0.5 × V

DDQ

V

5

Notes:

1. V

REFCA(DC)

 is expected to be approximately 0.5 × V

DD

 and to track variations in the DC

level. Externally generated peak noise (non-common mode) on V

REFCA

 may not exceed

±1% × V

DD

 around the V

REFCA(DC)

 value. Peak-to-peak AC noise on V

REFCA

 should not ex-

ceed ±2% of V

REFCA(DC)

.

2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-

cations if the DRAM induces additional AC noise greater than 20 MHz in frequency.

3. V

REFDQ(DC)

 is expected to be approximately 0.5 × V

DD

 and to track variations in the DC

level. Externally generated peak noise (non-common mode) on V

REFDQ

 may not exceed

±1% × V

DD

 around the V

REFDQ(DC)

 value. Peak-to-peak AC noise on V

REFDQ

 should not ex-

ceed ±2% of V

REFDQ(DC)

.

4. V

REFDQ(DC)

 may transition to V

REFDQ(SR)

 and back to V

REFDQ(DC)

 when in SELF REFRESH,

within restrictions outlined in the SELF REFRESH section.

5. V

TT

 is not applied directly to the device. V

TT

 is a system supply for signal termination re-

sistors. Minimum and maximum values are system-dependent.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

09005aef85af8fa8
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Table 25: DDR3L 1.35V Input Switching Conditions – Command and Address

Parameter/Condition

Symbol

DDR3L-800/1066

DDR3L-1333/1600

DDR3L-1866/2133

Units

Command and Address

Input high AC voltage: Logic 1

V

IH(AC160),min

5

160

160

mV

V

IH(AC135),min

5

135

135

135

mV

V

IH(AC125),min

5

125

mV

Input high DC voltage: Logic 1

V

IH(DC90),min

90

90

90

mV

Input low DC voltage: Logic 0

V

IL(DC90),min

–90

–90

–90

mV

Input low AC voltage: Logic 0

V

IL(AC125),min

5

–125

mV

V

IL(AC135),min

5

–135

–135

–135

mV

V

IL(AC160),min

5

–160

–160

mV

DQ and DM

Input high AC voltage: Logic 1

V

IH(AC160),min

5

160

160

mV

V

IH(AC135),min

5

135

135

135

mV

V

IH(AC125),min

5

130

mV

Input high DC voltage: Logic 1

V

IH(DC90),min

90

90

90

mV

Input low DC voltage: Logic 0

V

IL(DC90),min

–90

–90

–90

mV

Input low AC voltage: Logic 0

V

IL(AC125),min

5

–130

mV

V

IL(AC135),min

5

–135

–135

–135

mV

V

IL(AC160),min

5

–160

–160

mV

Notes:

1. All voltages are referenced to V

REF

. V

REF

 is V

REFCA

 for control, command, and address. All

slew rates and setup/hold times are specified at the DRAM ball. V

REF

 is V

REFDQ

 for DQ

and DM inputs.

2. Input setup timing parameters (

t

IS and 

t

DS) are referenced at V

IL(AC)

/V

IH(AC)

, not V

REF(DC)

.

3. Input hold timing parameters (

t

IH and 

t

DH) are referenced at V

IL(DC)

/V

IH(DC)

, not V

REF(DC)

.

4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is

900mV (peak-to-peak).

5. When two V

IH(AC)

 values (and two corresponding V

IL(AC)

 values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
V

IH(AC)

 value may be used for address/command inputs and the other V

IH(AC)

 value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC160),min

 and

V

IH(AC135),min

 (corresponding V

IL(AC160),min

 and V

IL(AC135),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC160),min

 with 

t

IS(AC160) of 210ps or V

IH(AC150),min

with 

t

IS(AC135) of 365ps; independently, the data inputs must use either V

IH(AC160),min

with 

t

DS(AC160) of 75ps or V

IH(AC150),min

 with 

t

DS(AC150) of 125ps.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

09005aef85af8fa8
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Table 26: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#)

Parameter/Condition

Symbol

Min

Max

Units

Notes

Differential input logic high – slew

V

IH,diff(AC)slew

180

N/A

mV

4

Differential input logic low – slew

V

IL,diff(AC)slew

N/A

–180

mV

4

Differential input logic high

V

IH,diff(AC)

2 × (V

IH(AC)

 - V

REF

)

V

DD

/V

DDQ

mV

5

Differential input logic low

V

IL,diff(AC)

V

SS

/V

SSQ

2 × (V

IL(AC)

 - V

REF

)

mV

6

Differential input crossing voltage
relative to V

DD

/2 for DQS, DQS#; CK,

CK#

V

IX

V

REF(DC)

 - 150

V

REF(DC)

 + 150

mV

5, 7, 9

Differential input crossing voltage
relative to V

DD

/2 for CK, CK#

V

IX

 (175)

V

REF(DC)

 - 175

V

REF(DC)

 + 175

mV

5, 7–9

Single-ended high level for strobes

V

SEH

V

DDQ

/2 + 160

V

DDQ

mV

5

Single-ended high level for CK, CK#

V

DD

/2 + 160

V

DD

mV

5

Single-ended low level for strobes

V

SEL

V

SSQ

V

DDQ

/2 - 160

mV

6

Single-ended low level for CK, CK#

V

SS

V

DD

/2 - 160

mV

6

Notes:

1. Clock is referenced to V

DD

 and V

SS

. Data strobe is referenced to V

DDQ

 and V

SSQ

.

2. Reference is V

REFCA(DC)

 for clock and V

REFDQ(DC)

 for strobe.

3. Differential input slew rate = 2 V/ns.
4. Defines slew rate reference points, relative to input crossing voltages.
5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli-

cable.

6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap-

plicable.

7. The typical value of V

IX(AC)

 is expected to be about 0.5 × V

DD

 of the transmitting device,

and V

IX(AC)

 is expected to track variations in V

DD

. V

IX(AC)

 indicates the voltage at which

differential input signals must cross.

8. The V

IX

 extended range (±175mV) is allowed only for the clock; this V

IX

 extended range

is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing V

SEL

, V

SEH

 of at least V

DD

/2 ±250mV, and

the differential slew rate of CK, CK# is greater than 3 V/ns.

9. V

IX

 must provide 25mV (single-ended) of the voltages separation.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

09005aef85af8fa8
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Figure 15: DDR3L 1.35V Input Signal

0.0V

V

REF

 - 90mV

V

REF

 = V

DD

/2

V

DD

  .51 x

V

IL(AC)

V

IL(DC)

V

REFDQ

 - AC noise

V

REFDQ

 - DC error

V

REFDQ

 + DC error

V

REFDQ

 + AC noise

V

IH(DC)

V

IH(AC)

V

DD

V

DD

 + 0.4V

Narrow pulse width

V

SS

 - 0.40V

Narrow pulse width

V

DDQ

V

DDQ

 + 0.4V

Overshoot

V

SS

 - 0.40V

Undershoot

V

SS

V

IL

 MIN(AC)

V

IL

 MIN(DC)

MAX 2% Total

DC MIN

V

REF

V

REF

 DC MAX

MAX 2% Total

V

IH

 MIN(DC)

V

IH

 MIN(AC)

Minimum V

IL

 and V

IH

 levels

V

IH(DC)

V

IH(AC)

V

IL(AC)

V

IL(DC)

V

IL

 and V

IH

 levels with ringback

V

REF

 DC MAX + 1%

V

REF

 DC MIN - 1% V

DD

V

REF

 + 90mV

V

REF

 + 125/135/160mV

V

REF

 - 125/135/160mV

V

DD

  .49 x

Note:

1. Numbers in diagrams reflect nominal values.

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DDR3L 1.35V AC Overshoot/Undershoot Specification

Table 27: DDR3L Control and Address Pins

Parameter

DDR3L-800

DRR3L-1066

DDR3L-1333

DDR3L-1600

DDR3L-1866

DDR3L-2133

Maximum peak ampli-
tude allowed for over-
shoot area
(see Figure 16)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum peak ampli-
tude allowed for under-
shoot area
(see Figure 17)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum overshoot area
above V

DD

 (see Figure 16)

0.67 V/ns

0.5 V/ns

0.4 V/ns

0.33 V/ns

0.28 V/ns

0.25 V/ns

Maximum undershoot
area below V

SS

 (see Fig-

ure 17)

0.67 V/ns

0.5 V/ns

0.4 V/ns

0.33 V/ns

0.28 V/ns

0.25 V/ns

Table 28: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins

Parameter

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

DDR3L-1866

DDR3L-2133

Maximum peak ampli-
tude allowed for over-
shoot area
(see Figure 16)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum peak ampli-
tude allowed for under-
shoot area
(see Figure 17)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum overshoot area
above V

DD

/V

DDQ

 (see Fig-

ure 16)

0.25 V/ns

0.19 V/ns

0.15 V/ns

0.13 V/ns

0.11 V/ns

0.10 V/ns

Maximum undershoot
area below V

SS

/V

SSQ

 (see 

Figure 17)

0.25 V/ns

0.19 V/ns

0.15 V/ns

0.13 V/ns

0.11 V/ns

0.10 V/ns

Figure 16: Overshoot

Maximum amplitude

Overshoot area

V

DD

/V

DDQ

Time (ns)

Volts (V)

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Figure 17: Undershoot

Maximum amplitude

Undershoot area

V

SS

/V

SSQ

Time (ns)

Volts (V)

Figure 18: V

IX

 for Differential Signals

CK, DQS

V

DD

/2, V

DDQ

/2

V

DD

/2, V

DDQ

/2

V

IX

V

IX

CK#, DQS#

V

DD

, V

DDQ

CK, DQS

V

DD

, V

DDQ

V

SS

, V

SSQ

CK#, DQS#

V

SS

, V

SSQ

X

X

X

X

X

X

X

X

V

IX

V

IX

Figure 19: Single-Ended Requirements for Differential Signals

V

SS

 or V

SSQ

V

DD

 or V

DDQ

V

SEL,max

V

SEH,min

V

SEH

V

SEL

CK or DQS

V

DD

/2 or V

DDQ

/2

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Figure 20: Definition of Differential AC-Swing and 

t

DVAC

V

IH,diff(AC)min

0.0

V

IL,diff,max

tDVAC

V

IH,diff,min

V

IL,diff(AC)max

Half cycle

tDVAC

CK - CK#

DQS - DQS#

Table 29: DDR3L 1.35V – Minimum Required Time 

t

DVAC for CK/CK#, DQS/DQS# Differential for AC

Ringback

Slew Rate (V/ns)

DDR3L-800/1066/1333/1600

DDR3L-1866/2133

t

DVAC at

320mV (ps)

t

DVAC at

270mV (ps)

t

DVAC at

270mV (ps)

t

DVAC at

250mV (ps)

t

DVAC at

260mV (ps)

>4.0

189

201

163

168

176

4.0

189

201

163

168

176

3.0

162

179

140

147

154

2.0

109

134

95

105

111

1.8

91

119

80

91

97

1.6

69

100

62

74

78

1.4

40

76

37

52

55

1.2

Note 1

44

5

22

24

1.0

Note 1

<1.0

Note 1

Note:

1. Rising input signal shall become equal to or greater than V

IH(AC)

 level and Falling input

signal shall become equal to or less than V

IL(AC)

 level.

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DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals

Setup (

t

IS and 

t

DS) nominal slew rate for a rising signal is defined as the slew rate be-

tween the last crossing of V

REF

 and the first crossing of V

IH(AC)min

. Setup (

t

IS and 

t

DS)

nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V

REF

 and the first crossing of V

IL(AC)max

.

Hold (

t

IH and 

t

DH) nominal slew rate for a rising signal is defined as the slew rate be-

tween the last crossing of V

IL(DC)max

 and the first crossing of V

REF

. Hold (

t

IH and 

t

DH)

nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V

IH(DC)min

 and the first crossing of V

REF

 (see Figure 21 (page 58)).

Table 30: Single-Ended Input Slew Rate Definition

Input Slew Rates

(Linear Signals)

Measured

Calculation

Input

Edge

From

To

Setup

Rising

V

REF

V

IH(AC),min

V

IH(AC),min

 - V

REF

ǻ

TRS

se

Falling

V

REF

V

IL(AC),max

V

REF

 - V

IL(AC),max

ǻ

TFS

se

Hold

Rising

V

IL(DC),max

V

REF

V

REF

 - V

IL(DC),max

ǻ

TFH

se

Falling

V

IH(DC),min

V

REF

V

IH(DC),min

 - V

REF

ǻ

TRSH

se

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Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals

ǻ

TRS

se

ǻ

TFS

se

ǻ

TRH

se

ǻ

TFH

se

V

REFDQ

 or

V

REFCA

V

IH(AC)min

V

IH(DC)min

V

IL(AC)max

V

IL(DC)max

V

REFDQ

 or 

V

REFCA

V

IH(AC)min

V

IH(DC)min

V

IL(AC)max

V

IL(DC)max

Setup

Hold

Single-ended input voltage (DQ,  CMD,  ADDR)

Single-ended input voltage (DQ, CMD,  ADDR)

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DDR3L 1.35V Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and meas-
ured, as shown in Table 31 and Figure 22. The nominal slew rate for a rising signal is
defined as the slew rate between V

IL,diff,max

 and V

IH,diff,min

. The nominal slew rate for a

falling signal is defined as the slew rate between V

IH,diff,min

 and V

IL,diff,max

.

Table 31: DDR3L 1.35V Differential Input Slew Rate Definition

Differential Input

Slew Rates

(Linear Signals)

Measured

Calculation

Input

Edge

From

To

CK and
DQS
reference

Rising

V

IL,diff,max

V

IH,diff,min

V

IH,diff,min

 - V

IL,diff,max

ǻ

TR

diff

Falling

V

IH,diff,min

V

IL,diff,max

V

IH,diff,min

 - V

IL,diff,max

ǻ

TF

diff

Figure 22: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#

ǻ

TR

diff

ǻ

TF

diff

V

IH,diff,min

V

IL,diff,max

0

Dif

ferential input voltage (DQS, DQS#; CK, CK#)

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ODT Characteristics

The ODT effective resistance R

TT

 is defined by MR1[9, 6, and 2]. ODT is applied to the

DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values
and a functional representation are listed in Table 32 and Table 33 (page 61). The indi-
vidual pull-up and pull-down resistors (R

TT(PU)

 and R

TT(PD)

) are defined as follows:

R

TT(PU)

 = (

V

DDQ

 - 

V

OUT

)/|

I

OUT

|, under the condition that R

TT(PD)

 is turned off

R

TT(PD)

 = (

V

OUT

)/|

I

OUT

|, under the condition that R

TT(PU)

 is turned off

Figure 23: ODT Levels and I-V Characteristics

R

TT(PU)

R

TT(PD)

ODT

Chip in termination mode

V

DDQ

DQ

V

SSQ

I

OUT

 = I

PD

 - I

PU

I

PU

I

PD

I

OUT

V

OUT

To
other
circuitry
such as 
RCV, . . .

Table 32: On-Die Termination DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Nom

Max

Unit

Notes

R

TT

 effective impedance

R

TT(EFF)

See Table 33 (page 61)

1, 2

Deviation of VM with respect to
V

DDQ

/2

˂

VM

–5

 

5

%

1, 2, 3

Notes:

1. Tolerance limits are applicable after proper ZQ calibration has been performed at a

stable temperature and voltage (V

DDQ

 = V

DD

, V

SSQ

 = V

SS

). Refer to ODT Sensitivity (page

62) if either the temperature or voltage changes after calibration.

2. Measurement definition for R

TT

: Apply V

IH(AC)

 to pin under test and measure current

I[V

IH(AC)

], then apply V

IL(AC)

 to pin under test and measure current I[V

IL(AC)

]:

R

TT 

V

IH(AC)

 - V

IL(AC)

I(V

IH(AC)

) - I(V

IL(AC)

)

 

3. Measure voltage (VM) at the tested pin with no load:

ǻ

VM = 

– 1

2 × VM

V

DDQ

× 100

4. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (T

C

).

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1.35V ODT Resistors

Table 33 provides an overview of the ODT DC electrical characteristics. The values pro-
vided are not specification requirements; however, they can be used as design guide-
lines to indicate what R

TT

 is targeted to provide:

• R

TT

 120

ȍ

 is made up of R

TT120(PD240)

 and R

TT120(PU240)

• R

TT

 60

ȍ

 is made up of R

TT60(PD120)

 and R

TT60(PU120)

• R

TT

 40

ȍ

 is made up of R

TT40(PD80)

 and R

TT40(PU80)

• R

TT

 30

ȍ

 is made up of R

TT30(PD60)

 and R

TT30(PU60)

• R

TT

 20

ȍ

 is made up of R

TT20(PD40)

 and R

TT20(PU40)

Table 33: 1.35V R

TT

 Effective Impedance

MR1

[9, 6, 2]

R

TT

Resistor

V

OUT

Min

Nom

Max

Units

0, 1, 0



˖

R

TT,120PD240

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/1

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/1

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/1

R

TT,120PU240

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/1

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/1

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/1



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/2

0, 0, 1



˖

R

TT,60PD120

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/2

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/2

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/2

R

TT,60PU120

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/2

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/2

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/2



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/4

0, 1, 1



˖

R

TT,40PD80

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/3

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/3

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/3

R

TT,40PU80

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/3

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/3

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/3



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/6

1, 0, 1



˖

R

TT,30PD60

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/4

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/4

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/4

R

TT,30PU60

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/4

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/4

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/4



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/8

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Table 33: 1.35V R

TT

 Effective Impedance (Continued)

MR1

[9, 6, 2]

R

TT

Resistor

V

OUT

Min

Nom

Max

Units

1, 0, 0



˖

R

TT,20PD40

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/6

R

TT,20PU40

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/6



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/12

ODT Sensitivity

If either the temperature or voltage changes after I/O calibration, then the tolerance
limits listed in Table 32 and Table 33 can be expected to widen according to Table 34
and Table 35.

Table 34: ODT Sensitivity Definition

Symbol

Min

Max

Unit

R

TT

0.9 - dR

TT

dT × |DT| - dR

TT

dV × |DV|

1.6 + dR

TT

dT × |DT| + dR

TT

dV × |DV|

RZQ/(2, 4, 6, 8, 12)

Note:

1.

˂

T = T - T(@ calibration), 

˂

V = V

DDQ

 - V

DDQ

(@ calibration) and V

DD

 = V

DDQ

.

Table 35: ODT Temperature and Voltage Sensitivity

Change

Min

Max

Unit

dR

TT

dT

0

1.5

%/°C

dR

TT

dV

0

0.15

%/mV

Note:

1.

˂

T = T - T(@ calibration), 

˂

V = V

DDQ

 - V

DDQ

(@ calibration) and V

DD

 = V

DDQ

.

ODT Timing Definitions

ODT loading differs from that used in AC timing measurements. The reference load for
ODT timings is shown in Figure 24. Two parameters define when ODT turns on or off
synchronously, two define when ODT turns on or off asynchronously, and another de-
fines when ODT turns on or off dynamically. Table 36 and Table 37 (page 63) outline
and provide definition and measurement references settings for each parameter.

ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to
turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance
begins to turn off.

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Figure 24: ODT Timing Reference Load

Timing reference point

DQ, DM

DQS, DQS#

TDQS, TDQS#

DUT

V

REF

V

TT

 = V

SSQ

V

DDQ

/2

ZQ

RZQ = 240

ȍ

V

SSQ

 

R

TT

 = 25

ȍ

CK, CK#

Table 36: ODT Timing Definitions

Symbol

Begin Point Definition

End Point Definition

Figure

t

AON

Rising edge of CK – CK# defined by the end
point of ODTLon

Extrapolated point at V

SSQ

Figure 25 (page 64)

t

AOF

Rising edge of CK – CK# defined by the end
point of ODTLoff

Extrapolated point at V

RTT,nom

Figure 25 (page 64)

t

AONPD

Rising edge of CK – CK# with ODT first being
registered HIGH

Extrapolated point at V

SSQ

Figure 26 (page 64)

t

AOFPD

Rising edge of CK – CK# with ODT first being
registered LOW

Extrapolated point at V

RTT,nom

Figure 26 (page 64)

t

ADC

Rising edge of CK – CK# defined by the end
point of ODTLcnw, ODTLcwn4, or ODTLcwn8

Extrapolated points at V

RTT(WR)

 and

V

RTT,nom

Figure 27 (page 65)

Table 37: DDR3L(1.35V) Reference Settings for ODT Timing Measurements

Measured

Parameter

R

TT,nom

 Setting

R

TT(WR)

 Setting

V

SW1

V

SW2

t

AON

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

AOF

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

AONPD

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

AOFPD

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

ADC

RZQ/12 (20

˖

RZQ/2 (20

˖

200mV

250mV

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Figure 25: 

t

AON and 

t

AOF Definitions

CK

CK#

tAON

V

SSQ

DQ, DM

DQS, DQS#

TDQS, TDQS#

Begin point: Rising edge of CK - CK# 
defined by the end point of ODTLon

V

SW1

End point: Extrapolated point at V

SSQ

T

SW1

T

SW2

CK

CK#

V

DDQ

/2

tAOF

Begin point: Rising edge of CK - CK# 
defined by the end point of ODTLoff

End point: Extrapolated point at V

RTT,nom

V

RTT,nom

V

SSQ

tAON

tAOF

V

SW2

V

SW2

V

SW1

T

SW1

T

SW1

Figure 26: 

t

AONPD and 

t

AOFPD Definitions

CK

CK#

tAONPD

V

SSQ

DQ, DM 
DQS, DQS# 
TDQS, TDQS#

Begin point: Rising edge of CK - CK# 
with ODT first registered high

V

SW1

End point: Extrapolated point at V

SSQ

T

SW2

CK

CK#

V

DDQ

/2

tAOFPD

Begin point: Rising edge of CK - CK# 
with ODT first registered low

End point: Extrapolated point at V

RTT,nom

V

RTT,nom

V

SSQ

tAONPD

tAOFPD

T

SW1

T

SW2

T

SW1

V

SW2

V

SW2

V

SW1

4Gb: x4, x8, x16 DDR3L SDRAM

ODT Characteristics

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Figure 27: 

t

ADC Definition

CK

CK#

tADC

DQ, DM 
DQS, DQS# 
TDQS, TDQS#

End point: 
Extrapolated 
point at V

RTT,nom

T

SW21

tADC

End point: Extrapolated point at V

RTT(WR)

V

DDQ

/2

V

SSQ

V

RTT,nom

V

RTT(WR)

V

RTT,nom

Begin point: Rising edge of CK - CK# 
defined by the end point of ODTLcnw

Begin point: Rising edge of CK - CK# defined by 
the end point of ODTLcwn4 or ODTLcwn8

T

SW11

V

SW1

V

SW2

T

SW12

T

SW22

4Gb: x4, x8, x16 DDR3L SDRAM

ODT Characteristics

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Output Driver Impedance

The output driver impedance is selected by MR1[5,1] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is per-
formed. Output specifications refer to the default output driver unless specifically sta-
ted otherwise. A functional representation of the output buffer is shown below. The out-
put driver impedance R

ON

 is defined by the value of the external reference resistor RZQ

as follows:

R

ON,x

 = 

RZQ

/

y

 (with RZQ = 240

ȍ

 ±1%; 

= 34

ȍ

 or 40

ȍ

 with 

= 7 or 6, respectively)

The individual pull-up and pull-down resistors R

ON(PU)

 and R

ON(PD)

 are defined as fol-

lows:

R

ON(PU)

 = (

V

DDQ

 - 

V

OUT

)/|

I

OUT

|, when R

ON(PD)

 is turned off

R

ON(PD)

 = (

V

OUT

)/|

I

OUT

|, when R

ON(PU)

 is turned off

Figure 28: Output Driver

R

ON(PU)

R

ON(PD)

Output driver

To
other
circuitry
such as
RCV, . . .

Chip in drive mode

V

DDQ

V

SSQ

I

PU

I

PD

I

OUT

V

OUT

DQ

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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34 Ohm Output Driver Impedance

The 34

ȍ

 driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings

and specifications listed herein apply to the 34

ȍ

 driver only. Its impedance R

ON

 is de-

fined by the value of the external reference resistor RZQ as follows: R

ON34

 = RZQ/7 (with

nominal RZQ = 240

ȍ

 ±1%) and is actually 34.3

ȍ

 ±1%.

Table 38: DDR3L 34 Ohm Driver Impedance Characteristics

MR1

[5, 1]

R

ON

Resistor

V

OUT

Min

Nom

Max

Units

0, 1



˖

R

ON,34PD

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/7

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/7

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/7

R

ON,34PU

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/7

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/7

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/7

Pull-up/pull-down mismatch (MM

PUPD

)

V

IL(AC)

 to V

IH(AC)

–10

N/A

10

%

Notes:

1. Tolerance limits assume RZQ of 240

˖

±1% and are applicable after proper ZQ calibra-

tion has been performed at a stable temperature and voltage: 

V

DDQ

 = 

V

DD

V

SSQ

 = 

V

SS

).

Refer to DDR3L 34 Ohm Output Driver Sensitivity (page 69) if either the temperature
or the voltage changes after calibration.

2. Measurement definition for mismatch between pull-up and pull-down (MM

PUPD

). Meas-

ure both R

ON(PU)

 and R

ON(PD) 

at 0.5 × V

DDQ

:

MM

PUPD

 = 

 × 

100

R

ON(PU)

 - R

ON(PD)

R

ON,nom

3. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (T

C

).

A larger maximum limit will result in slightly lower minimum currents.

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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DDR3L 34 Ohm Driver

Using Table 39, the 34

ȍ

 driver’s current range has been calculated and summarized in 

Table 40 (page 68) V

DD

 = 1.35V, Table 41 for V

DD

 = 1.45V, and Table 42 (page 69) for

V

DD

 = 1.283V. The individual pull-up and pull-down resistors R

ON34(PD)

 and R

ON34(PU)

are defined as follows:

R

ON34(PD) 

= (

V

OUT

)/|

I

OUT

|; R

ON34(PU) 

is turned off

R

ON34(PU)

 = (

V

DDQ

 - 

V

OUT

)/|

I

OUT

|; R

ON34(PD)

 is turned off

Table 39: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations

R

ON

Min

Nom

Max

Unit

RZQ = 240

˖



237.6

240

242.4

˖

RZQ/7 = (240

˖



33.9

34.3

34.6

˖

MR1[5,1]

R

ON

Resistor

V

OUT

Min

Nom

Max

Unit

0, 1



˖

R

ON34(PD)

0.2 × V

DDQ

20.4

34.3

38.1

˖

0.5 × V

DDQ

30.5

34.3

38.1

˖

0.8 × V

DDQ

30.5

34.3

48.5

˖

R

ON34(PU)

0.2 × V

DDQ

30.5

34.3

48.5

˖

0.5 × V

DDQ

30.5

34.3

38.1

˖

0.8 × V

DDQ

20.4

34.3

38.1

˖

Table 40: DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.35V

MR1[5,1]

R

ON

Resistor

V

OUT

Max

Nom

Min

Unit

0, 1



˖

R

ON34(PD)

I

OL

 @ 0.2 × V

DDQ

13.3

7.9

7.1

mA

I

OL

 @ 0.5 × V

DDQ

22.1

19.7

17.7

mA

I

OL

 @ 0.8 × V

DDQ

35.4

31.5

22.3

mA

R

ON34(PU)

I

OH

 @ 0.2 × V

DDQ

35.4

31.5

22.3

mA

I

OH

 @ 0.5 × V

DDQ

22.1

19.7

17.7

mA

I

OH

 @ 0.8 × V

DDQ

13.3

7.9

7.1

mA

Table 41: DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.45V

MR1[5,1]

R

ON

Resistor

V

OUT

Max

Nom

Min

Unit

0, 1



˖

R

ON34(PD)

I

OL

 @ 0.2 × V

DDQ

14.2

8.5

7.6

mA

I

OL

 @ 0.5 × V

DDQ

23.7

21.1

19.0

mA

I

OL

 @ 0.8 × V

DDQ

38.0

33.8

23.9

mA

R

ON34(PU)

I

OH

 @ 0.2 × V

DDQ

38.0

33.8

23.9

mA

I

OH

 @ 0.5 × V

DDQ

23.7

21.1

19.0

mA

I

OH

 @ 0.8 × V

DDQ

14.2

8.5

7.6

mA

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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Table 42: DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.283

MR1[5,1]

R

ON

Resistor

V

OUT

Max

Nom

Min

Unit

0, 1



˖

R

ON34(PD)

I

OL

 @ 0.2 × V

DDQ

12.6

7.5

6.7

mA

I

OL

 @ 0.5 × V

DDQ

21.0

18.7

16.8

mA

I

OL

 @ 0.8 × V

DDQ

33.6

29.9

21.2

mA

R

ON34(PU)

I

OH

 @ 0.2 × V

DDQ

33.6

29.9

21.2

mA

I

OH

 @ 0.5 × V

DDQ

21.0

18.7

16.8

mA

I

OH

 @ 0.8 × V

DDQ

12.6

7.5

6.7

mA

DDR3L 34 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after ZQ calibration, then the tolerance
limits listed in Table 38 (page 67) can be expected to widen according to Table 43 and 
Table 44.

Table 43: DDR3L 34 Ohm Output Driver Sensitivity Definition

Symbol

Min

Max

Unit

R

ON(PD)

 @ 0.2 × V

DDQ

0.6 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.1 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/7

R

ON(PD)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/7

R

ON(PD)

 @ 0.8 × V

DDQ

0.9 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.4 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/7

R

ON(PU)

 @ 0.2 × V

DDQ

0.9 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.4 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/7

R

ON(PU)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/7

R

ON(PU)

 @ 0.8 × V

DDQ

0.6 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.1 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/7

Note:

1.

˂

T

 = 

T

 - 

T

(@CALIBRATION)



˂

V

 = 

V

DDQ

 - 

V

DDQ(@CALIBRATION)

; and 

V

DD

 = 

V

DDQ

.

Table 44: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity

Change

Min

Max

Unit

dR

ON

dTM

0

1.5

%/°C

dR

ON

dVM

0

0.13

%/mV

dR

ON

dTL

0

1.5

%/°C

dR

ON

dVL

0

0.13

%/mV

dR

ON

dTH

0

1.5

%/°C

dR

ON

dVH

0

0.13

%/mV

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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DDR3L Alternative 40 Ohm Driver

Table 45: DDR3L 40 Ohm Driver Impedance Characteristics

MR1

[5, 1]

R

ON

Resistor

V

OUT

Min

Nom

Max

Units

0, 0



˖

R

ON,40PD

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/6

R

ON,40PU

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/6

Pull-up/pull-down mismatch (MM

PUPD

)

V

IL(AC)

 to V

IH(AC)

–10

N/A

10

%

Notes:

1. Tolerance limits assume RZQ of 240

˖

±1% and are applicable after proper ZQ calibra-

tion has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

V

SSQ

 = 

V

SS

).

Refer to DDR3L 40 Ohm Output Driver Sensitivity (page 70) if either the temperature
or the voltage changes after calibration.

2. Measurement definition for mismatch between pull-up and pull-down (MM

PUPD

). Meas-

ure both R

ON(PU)

 and R

ON(PD)

 at 0.5 × V

DDQ

:

MM

PUPD

 = 

 × 

100

R

ON(PU)

 - R

ON(PD)

R

ON,nom

3. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (T

C

).

A larger maximum limit will result in slightly lower minimum currents.

DDR3L 40 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after I/O calibration, then the tolerance
limits listed in Table 45 can be expected to widen according to Table 46 and Table 47
(page 71).

Table 46: DDR3L 40 Ohm Output Driver Sensitivity Definition

Symbol

Min

Max

Unit

R

ON(PD)

 @ 0.2 × V

DDQ

0.6 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.1 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/6

R

ON(PD)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/6

R

ON(PD)

 @ 0.8 × V

DDQ

0.9 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.4 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/6

R

ON(PU)

 @ 0.2 × V

DDQ

0.9 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.4 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/6

R

ON(PU)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/6

R

ON(PU)

 @ 0.8 × V

DDQ

0.6 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.1 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/6

Note:

1.

˂

T

 = 

T

 - 

T

(@CALIBRATION)



˂

V

 = 

V

DDQ

 - 

V

DDQ(@CALIBRATION)

; and 

V

DD

 = 

V

DDQ

.

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity

Change

Min

Max

Unit

dR

ON

dTM

0

1.5

%/°C

dR

ON

dVM

0

0.15

%/mV

dR

ON

dTL

0

1.5

%/°C

dR

ON

dVL

0

0.15

%/mV

dR

ON

dTH

0

1.5

%/°C

dR

ON

dVH

0

0.15

%/mV

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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Output Characteristics and Operating Conditions

Table 48: DDR3L Single-Ended Output Driver Characteristics

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Output leakage current: DQ are disabled;
0V 

 V

OUT

 

 V

DDQ

; ODT is disabled; ODT is HIGH

I

OZ

–5

5

μA

1

Output slew rate: Single-ended; For rising and falling edges,
measure between V

OL(AC)

 = V

REF

 - 0.09 × V

DDQ

 and V

OH(AC)

 =

V

REF

 + 0.09 × V

DDQ

SRQ

se

1.75

6

V/ns

1, 2, 3, 4

Single-ended DC high-level output voltage

V

OH(DC)

0.8 × V

DDQ

V

1, 2, 5

Single-ended DC mid-point level output voltage

V

OM(DC)

0.5 × V

DDQ

V

1, 2, 5

Single-ended DC low-level output voltage

V

OL(DC)

0.2 × V

DDQ

V

1, 2, 5

Single-ended AC high-level output voltage

V

OH(AC)

V

TT

 + 0.1 × V

DDQ

V

1, 2, 3, 6

Single-ended AC low-level output voltage

V

OL(AC)

V

TT

 - 0.1 × V

DDQ

V

1, 2, 3, 6

Delta R

ON

 between pull-up and pull-down for DQ/DQS

MM

PUPD

–10

10

%

1, 7

Test load for AC timing and output slew rates

Output to V

TT

 (V

DDQ

/2) via 25

˖

 resistor

3

Notes:

1. RZQ of 240

˖

±1% with RZQ/7 enabled (default 34

˖

 driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

;

V

SSQ

 = 

V

SS

).

2.

V

TT

 = 

V

DDQ

/2.

3. See Figure 31 (page 75) for the test load configuration.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from

HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching in the opposite direction. For all other DQ signal switch-
ing combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.

5. See Figure 28 (page 66) for IV curve linearity. Do not use AC test load.
6. See Slew Rate Definitions for Single-Ended Output Signals (page 75) for output slew

rate.

7. See Figure 28 (page 66) for additional information.
8. See Figure 29 (page 73) for an example of a single-ended output signal.

4Gb: x4, x8, x16 DDR3L SDRAM

Output Characteristics and Operating Conditions

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Figure 29: DQ Output Signal

V

OH(AC)

MIN output

MAX output

V

OL(AC)

 

Table 49: DDR3L Differential Output Driver Characteristics

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Output leakage current: DQ are disabled;
0V 

 V

OUT

 

 V

DDQ

; ODT is disabled; ODT is HIGH

I

OZ

–5

5

μA

1

DDR3L Output slew rate: Differential; For rising and fall-
ing edges, measure between V

OL,diff(AC)

 = –0.18 × V

DDQ

and V

OH,diff(AC)

 = 0.18 × V

DDQ

SRQ

diff

3.5

12

V/ns

1

Differential high-level output voltage

V

OH,diff(AC)

+0.2 × V

DDQ

V

1, 4

Differential low-level output voltage

V

OL,diff(AC)

–0.2 × V

DDQ

V

1, 4

Delta Ron between pull-up and pull-down for DQ/DQS

MM

PUPD

–10

10

%

1, 5

Test load for AC timing and output slew rates

Output to V

TT

 (V

DDQ

/2) via 25

˖

 resistor

3

Notes:

1. RZQ of 240

˖

±1% with RZQ/7 enabled (default 34

˖

 driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

;

V

SSQ

 = 

V

SS

).

2.

V

REF

 = 

V

DDQ

/2; slew rate @ 5 V/ns, interpolate for faster slew rate.

3. See Figure 31 (page 75) for the test load configuration.
4. See Table 52 (page 77) for the output slew rate.
5. See Table 38 (page 67) for additional information.
6. See Figure 30 (page 74) for an example of a differential output signal.

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Table 50: DDR3L Differential Output Driver Characteristics V

OX(AC)

All voltages are referenced to V

SS

Parameter/

Condition

Symbol

DDR3L- 800/1066/1333 DQS/DQS# Differential Slew Rate

Unit

3.5V/ns

4V/ns

5V/ns

6V/ns

7V/ns

8V/ns

9V/ns

10V/ns

12V/ns

Output differential
crosspoint voltage

V

OX(AC)

Max

115

130

135

195

205

205

205

205

205

mV

Min

–115

–130

–135

–195

–205

–205

–205

–205

–205

mV

Parameter/

Condition

Symbol

DDR3L-1600/1866/2133 DQS/DQS# Differential Slew Rate

Unit

3.5V/ns

4V/ns

5v/ns

6V/ns

7V/ns

8V/ns

9V/ns

10V/ns

12V/ns

Output differential

crosspoint voltage

V

OX(AC)

Max

90

105

135

155

180

205

205

205

205

mV

Min

–90

–105

–135

–155

–180

–205

–205

–205

–205

mV

Notes:

1. RZQ of 240

˖

±1% with RZQ/7 enabled (default 34

˖

 driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

;

V

SSQ

 = 

V

SS

).

2. See Figure 31 (page 75) for the test load configuration.
3. See Figure 30 (page 74) for an example of a differential output signal.
4. For a differential slew rate between the list values, the V

OX(AC)

 value may be obtained

by linear interpolation.

Figure 30: Differential Output Signal

V

OH

MIN output

MAX output

V

OL

V

OX(AC)max

V

OX(AC)min

X

X

X

X

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Reference Output Load

Figure 31 (page 75) represents the effective reference load of 25

ȍ

 used in defining the

relevant device AC timing parameters (except ODT reference timing) as well as the out-
put slew rate measurements. It is not intended to be a precise representation of a partic-
ular system environment or a depiction of the actual load presented by a production
tester. System designers should use IBIS or other simulation tools to correlate the tim-
ing reference load to a system environment.

Figure 31: Reference Output Load for AC Timing and Output Slew Rate

Timing reference point

DQ

DQS

DQS#

DUT

V

REF

V

TT

 = V

DDQ

/2

V

DDQ

/2

ZQ

RZQ = 240

ȍ

V

SS

 

R

TT

 = 25

ȍ

Slew Rate Definitions for Single-Ended Output Signals

The single-ended output driver is summarized in Table 48 (page 72). With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between V

OL(AC)

 and V

OH(AC)

 for single-ended signals.

Table 51: Single-Ended Output Slew Rate Definition

Single-Ended Output Slew

Rates (Linear Signals)

Measured

Calculation

Output

Edge

From

To

DQ

Rising

V

OL(AC)

V

OH(AC)

V

OH(AC)

 - V

OL(AC)

ǻ

TR

se

Falling

V

OH(AC)

V

OL(AC)

V

OH(AC)

 - V

OL(AC)

ǻ

TF

se

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Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals

V

OH(AC)

V

OL(AC)

V

TT

ǻ

TF

se

ǻ

TR

se

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Slew Rate Definitions for Differential Output Signals

The differential output driver is summarized in Table 49 (page 73). With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between V

OL(AC)

 and V

OH(AC)

 for differential signals.

Table 52: Differential Output Slew Rate Definition

Differential Output Slew

Rates (Linear Signals)

Measured

Calculation

Output

Edge

From

To

DQS, DQS#

Rising

V

OL,diff(AC)

V

OH,diff(AC)

V

OH,diff(AC)

 - V

OL,diff(AC)

ǻ

TR

diff

Falling

V

OH,diff(AC)

V

OL,diff(AC)

V

OH,diff(AC)

 - V

OL,diff(AC)

ǻ

TF

diff

Figure 33: Nominal Differential Output Slew Rate Definition for DQS, DQS#

ǻ

TR

diff

ǻ

TF

diff

V

OH,diff(AC)

V

OL,diff(AC)

0

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Speed Bin Tables

Table 53: DDR3L-1066 Speed Bins

DDR3L-1066 Speed Bin

-187E

-187

Unit

Notes

CL-

t

RCD-

t

RP

7-7-7

8-8-8

Parameter

Symbol

Min

Max

Min

Max

Internal READ command to first data

t

AA

13.125

15

ns

 

ACTIVATE to internal READ or WRITE delay
time

t

RCD

13.125

15

ns

 

PRECHARGE command period

t

RP

13.125

15

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command
period

t

RC

50.625

52.5

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

37.5

9 x 

t

REFI

37.5

9 x 

t

REFI

ns

1

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

3.0

3.3

ns

2

CWL = 6

t

CK (AVG)

Reserved

Reserved

ns

3

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

2.5

3.3

ns

2

CWL = 6

t

CK (AVG)

Reserved

Reserved

ns

3

CL = 7

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

3

CWL = 6

t

CK (AVG)

1.875

<2.5

Reserved

ns

2, 3

CL = 8

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

3

CWL = 6

t

CK (AVG)

1.875

<2.5

1.875

<2.5

ns

2

Supported CL settings

5, 6, 7, 8

5, 6, 8

CK

 

Supported CWL settings

5, 6

5, 6

CK

 

Notes:

1.

t

REFI depends on T

OPER

.

2. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

3. Reserved settings are not allowed.

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Table 54: DDR3L-1333 Speed Bins

DDR3L-1333 Speed Bin

-15E

1

-15

2

Unit

Notes

CL-

t

RCD-

t

RP

9-9-9

10-10-10

Parameter

Symbol

Min

Max

Min

Max

Internal READ command to first data

t

AA

13.5

15

ns

 

ACTIVATE to internal READ or WRITE delay
time

t

RCD

13.5

15

ns

 

PRECHARGE command period

t

RP

13.5

15

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command
period

t

RC

49.5

51

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

36

9 x 

t

REFI

36

9 x 

t

REFI

ns

3

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

3.0

3.3

ns

4

CWL = 6, 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

2.5

3.3

ns

4

CWL = 6

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 7

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 6

t

CK (AVG)

1.875

<2.5

Reserved

ns

4, 5

CWL = 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 8

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 6

t

CK (AVG)

1.875

<2.5

1.875

<2.5

ns

4

CWL = 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 9

CWL = 5, 6

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 7

t

CK (AVG)

1.5

<1.875

Reserved

ns

4, 5

CL = 10

CWL = 5, 6

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 7

t

CK (AVG)

1.5

<1.875

1.5

<1.875

ns

4

Supported CL settings

5, 6, 7, 8, 9, 10

5, 6, 8, 10

CK

 

Supported CWL settings

5, 6, 7

5, 6, 7

CK

 

Notes:

1. The -15E speed grade is backward compatible with 1066, CL = 7 (-187E).
2. The -15 speed grade is backward compatible with 1066, CL = 8 (-187).
3.

t

REFI depends on T

OPER

.

4. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

5. Reserved settings are not allowed.

4Gb: x4, x8, x16 DDR3L SDRAM

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Table 55: DDR3L-1600 Speed Bins

DDR3L-1600 Speed Bin

-125

1

Unit

Notes

CL-

t

RCD-

t

RP

11-11-11

Parameter

Symbol

Min

Max

Internal READ command to first data

t

AA

13.75

ns

 

ACTIVATE to internal READ or WRITE delay time

t

RCD

13.75

ns

 

PRECHARGE command period

t

RP

13.75

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command period

t

RC

48.75

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

35

9 x 

t

REFI

ns

2

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

ns

3

CWL = 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

ns

3

CWL = 6

t

CK (AVG)

Reserved

ns

4

CWL = 7, 8

t

CK (AVG)

Reserved

ns

4

CL = 7

CWL = 5

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 8

CWL = 5

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 9

CWL = 5, 6

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 10

CWL = 5, 6

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 11

CWL = 5, 6, 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

1.25

<1.5

ns

3

Supported CL settings

5, 6, 7, 8, 9, 10, 11

CK

 

Supported CWL settings

5, 6, 7, 8

CK

 

Notes:

1. The -125 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7

(-187E).

2.

t

REFI depends on T

OPER

.

3. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

4Gb: x4, x8, x16 DDR3L SDRAM

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Table 56: DDR3L-1866 Speed Bins

DDR3L-1866 Speed Bin

-107

1

Unit

Notes

CL-

t

RCD-

t

RP

13-13-13

Parameter

Symbol

Min

Max

Internal READ command to first data

t

AA

13.91

20

  

ACTIVATE to internal READ or WRITE delay time

t

RCD

13.91

ns

 

PRECHARGE command period

t

RP

13.91

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command period

t

RC

47.91

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

34

9 x 

t

REFI

ns

2

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 7

CWL = 5, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CL = 8

CWL = 5, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CL = 9

CWL = 5, 6, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CL = 10

CWL = 5, 6, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 11

CWL = 5, 6, 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

1.25

<1.5

ns

3

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 12

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 13

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

1.07

<1.25

ns

3

Supported CL settings

5, 6, 7, 8, 9, 10, 11, 13

CK

 

Supported CWL settings

5, 6, 7, 8, 9

CK

 

Notes:

1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9

(-15E) and 1066, CL = 7 (-187E).

2.

t

REFI depends on T

OPER

.

3. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

4Gb: x4, x8, x16 DDR3L SDRAM

Speed Bin Tables

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Table 57: DDR3L-2133 Speed Bins

DDR3L-2133 Speed Bin

-093

1

Unit

Notes

CL-

t

RCD-

t

RP

14-14-14

Parameter

Symbol

Min

Max

Internal READ command to first data

t

AA

13.09

20

  

ACTIVATE to internal READ or WRITE delay time

t

RCD

13.09

ns

 

PRECHARGE command period

t

RP

13.09

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command period

t

RC

46.09

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

33

9 x 

t

REFI

ns

2

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 7

CWL = 5, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CL = 8

CWL = 5, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CL = 9

CWL = 5, 6, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CL = 10

CWL = 5, 6, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 11

CWL = 5, 6, 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

1.25

<1.5

ns

3

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 12

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 13

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

1.07

<1.25

ns

3

CL = 14

CWL = 5, 6, 7, 8, 9

t

CK (AVG)

Reserved

Reserved

ns

4

CWL = 10

t

CK (AVG)

0.938

<1.07

ns

3

Supported CL settings

5, 6, 7, 8, 9, 10, 11, 13, 14

CK

 

Supported CWL settings

5, 6, 7, 8, 9

CK

 

Notes:

1. The -093 speed grade is backward compatible with 1866, CL = 13 (-107) , 1600, CL = 11

(-125) , 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E).

2.

t

REFI depends on T

OPER

.

3. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

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Speed Bin Tables

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Electrical Characteristics and AC Operating Conditions

Table 58: Electrical Characteristics and AC Operating Conditions

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Clock Timing

Clock period average:
DLL disable mode

T

 85°C

t

CK

(DLL_DIS)

8

7800

8

7800

8

7800

8

7800

ns

9, 42

T

C

 = >85°C to 95°C

8

3900

8

3900

8

3900

8

3900

ns

42

Clock period average: DLL enable mode

t

CK (AVG)

See Speed Bin Tables for 

t

CK range allowed

ns

10, 11

High pulse width average

t

CH (AVG)

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

CK

12

Low pulse width average

t

CL (AVG)

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

CK

12

Clock period jitter

DLL locked

t

JITper

–100

100

–90

90

–80

80

–70

70

ps

13

DLL locking

t

JITper,lck

–90

90

–80

80

–70

70

–60

60

ps

13

Clock absolute period

t

CK (ABS)

MIN = 

t

CK (AVG) MIN + 

t

JITper MIN; MAX = 

t

CK (AVG) MAX + 

t

JITper

MAX

ps

 

Clock absolute high pulse width

t

CH (ABS)

0.43

0.43

0.43

0.43

t

CK

(AVG)

14

Clock absolute low pulse width

t

CL (ABS)

0.43

0.43

0.43

0.43

t

CK

(AVG)

15

Cycle-to-cycle jitter

DLL locked

t

JITcc

200

180

160

140

ps

16

DLL locking

t

JITcc,lck

180

160

140

120

ps

16

Cumulative error across 2 cycles

t

ERR2per

–147

147

–132

132

–118

118

–103

103

ps

17

3 cycles

t

ERR3per

–175

175

–157

157

–140

140

–122

122

ps

17

4 cycles

t

ERR4per

–194

194

–175

175

–155

155

–136

136

ps

17

5 cycles

t

ERR5per

–209

209

–188

188

–168

168

–147

147

ps

17

6 cycles

t

ERR6per

–222

222

–200

200

–177

177

–155

155

ps

17

7 cycles

t

ERR7per

–232

232

–209

209

–186

186

–163

163

ps

17

8 cycles

t

ERR8per

–241

241

–217

217

–193

193

–169

169

ps

17

9 cycles

t

ERR9per

–249

249

–224

224

–200

200

–175

175

ps

17

10 cycles

t

ERR10per

–257

257

–231

231

–205

205

–180

180

ps

17

11 cycles

t

ERR11per

–263

263

–237

237

–210

210

–184

184

ps

17

12 cycles

t

ERR12per

–269

269

–242

242

–215

215

–188

188

ps

17

= 13, 14 . . . 49, 50

cycles

t

ERR

n

per

t

ERR

n

per MIN = (1 + 0.68ln[

n

]) × 

t

JITper MIN

t

ERR

n

per MAX = (1 + 0.68ln[

n

]) × 

t

JITper MAX

ps

17

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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4Gb_DDR3L.pdf - Rev

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

DQ Input Timing

Data setup time to
DQS, DQS#

Base (specification)

t

DS

(AC160)

90

40

ps

18, 19, 

44

V

REF

 @ 1 V/ns

250

200

ps

19, 20

Data setup time to
DQS, DQS#

Base (specification)

t

DS

(AC135)

140

90

45

25

ps

18, 19, 

44

V

REF

 @ 1 V/ns

275

250

180

160

ps

19, 20

Data hold time from
DQS, DQS#

Base (specification)

t

DH

(DC90)

160

110

75

55

ps

18, 19

V

REF

 @ 1 V/ns

250

200

165

145

ps

19, 20

Minimum data pulse width

t

DIPW

600

490

400

360

ps

41

DQ Output Timing

DQS, DQS# to DQ skew, per access

t

DQSQ

200

150

125

100

ps

 

DQ output hold time from DQS, DQS#

t

QH

0.38

0.38

0.38

0.38

t

CK

(AVG)

21

DQ Low-Z time from CK, CK#

t

LZDQ

–800

400

–600

300

–500

250

–450

225

ps

22, 23

DQ High-Z time from CK, CK#

t

HZDQ

400

300

250

225

ps

22, 23

DQ Strobe Input Timing

DQS, DQS# rising to CK, CK# rising

t

DQSS

–0.25

0.25

–0.25

0.25

–0.25

0.25

–0.27

0.27

CK

25

DQS, DQS# differential input low pulse width

t

DQSL

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK

 

DQS, DQS# differential input high pulse
width

t

DQSH

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK

 

DQS, DQS# falling setup to CK, CK# rising

t

DSS

0.2

0.2

0.2

0.18

CK

25

DQS, DQS# falling hold from CK, CK# rising

t

DSH

0.2

0.2

0.2

0.18

CK

25

DQS, DQS# differential WRITE preamble

t

WPRE

0.9

0.9

0.9

0.9

CK

 

DQS, DQS# differential WRITE postamble

t

WPST

0.3

0.3

0.3

0.3

CK

 

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK#

t

DQSCK

–400

400

–300

300

–255

255

–225

225

ps

23

DQS, DQS# rising to/from rising CK, CK#
when DLL is disabled

t

DQSCK

(DLL_DIS)

1

10

1

10

1

10

1

10

ns

26

DQS, DQS# differential output high time

t

QSH

0.38

0.38

0.40

0.40

CK

21

DQS, DQS# differential output low time

t

QSL

0.38

0.38

0.40

0.40

CK

21

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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4Gb_DDR3L.pdf - Rev

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, Inc. reserves the right to change products or specifications without notice.

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

DQS, DQS# Low-Z time (RL - 1)

t

LZDQS

–800

400

–600

300

–500

250

–450

225

ps

22, 23

DQS, DQS# High-Z time (RL + BL/2)

t

HZDQS

400

300

250

225

ps

22, 23

DQS, DQS# differential READ preamble

t

RPRE

0.9

Note 24

0.9

Note 24

0.9

Note 24

0.9

Note 24

CK

23, 24

DQS, DQS# differential READ postamble

t

RPST

0.3

Note 27

0.3

Note 27

0.3

Note 27

0.3

Note 27

CK

23, 27

Command and Address Timing

DLL locking time

t

DLLK

512

512

512

512

CK

28

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC160)

215

140

80

60

ps

29, 30, 

44

V

REF

 @ 1 V/ns

375

300

240

220

ps

20, 30

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC135)

365

290

205

185

ps

29, 30, 

44

V

REF

 @ 1 V/ns

500

425

340

320

ps

20, 30

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IH

(DC90

285

210

150

130

ps

29, 30, 

44

V

REF

 @ 1 V/ns

375

300

240

220

ps

20, 30

Minimum CTRL, CMD, ADDR pulse width

t

IPW

900

780

620

560

ps

41

ACTIVATE to internal READ or WRITE delay

t

RCD

See Speed Bin Tables for 

t

RCD

ns

31

PRECHARGE command period

t

RP

See Speed Bin Tables for 

t

RP

ns

31

ACTIVATE-to-PRECHARGE command period

t

RAS

See Speed Bin Tables for 

t

RAS

ns

31, 32

ACTIVATE-to-ACTIVATE command period

t

RC

See Speed Bin Tables for 

t

RC

ns

31, 43

ACTIVATE-to-ACTIVATE
minimum command
period

x4/x8 (1KB page
size)

t

RRD

MIN = greater of

4CK or 10ns

MIN = greater of

4CK or 7.5ns

MIN = greater of

4CK or 6ns

MIN = greater of

4CK or 6ns

CK

31

x16 (2KB page size)

MIN = greater of 4CK or 10ns

MIN = greater of 4CK or 7.5ns

CK

31

Four ACTIVATE
windows

x4/x8 (1KB page
size)

t

FAW

40

37.5

30

30

ns

31

x16 (2KB page size)

50

50

45

40

ns

31

Write recovery time

t

WR

MIN = 15ns; MAX = N/A

ns

31, 32, 

33,34

Delay from start of internal WRITE
transaction to internal READ command

t

WTR

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 34

READ-to-PRECHARGE time

t

RTP

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 32

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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4Gb_DDR3L.pdf - Rev

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

CAS#-to-CAS# command delay

t

CCD

MIN = 4CK; MAX = N/A

CK

 

Auto precharge write recovery + precharge
time

t

DAL

MIN = WR + 

t

RP/

t

CK (AVG); MAX = N/A

CK

 

MODE REGISTER SET command cycle time

t

MRD

MIN = 4CK; MAX = N/A

CK

 

MODE REGISTER SET command update delay

t

MOD

MIN = greater of 12CK or 15ns; MAX = N/A

CK

 

MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit

t

MPRR

MIN = 1CK; MAX = N/A

CK

 

Calibration Timing

ZQCL command: Long
calibration time

POWER-UP and RE-
SET operation

t

ZQinit

512

512

512

512

CK

 

Normal operation

t

ZQoper

256

256

256

256

CK

 

ZQCS command: Short calibration time

t

ZQCS

64

64

64

64

CK

 

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command

t

XPR

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Begin power supply ramp to power supplies
stable

t

VDDPR

MIN = N/A; MAX = 200

ms

 

RESET# LOW to power supplies stable

t

RPS

MIN = 0; MAX = 200

ms

 

RESET# LOW to I/O and R

TT

 High-Z

t

IOZ

MIN = N/A; MAX = 20

ns

35

Refresh Timing

REFRESH-to-ACTIVATE or REFRESH
command period

t

RFC – 1Gb

MIN = 110; MAX = 70,200

ns

 

t

RFC – 2Gb

MIN = 160; MAX = 70,200

ns

 

t

RFC – 4Gb

MIN = 260; MAX = 70,200

ns

 

t

RFC – 8Gb

MIN = 350; MAX = 70,200

ns

 

Maximum refresh
period

T

C

 

 85°C

64 (1X)

ms

36

T

C

 > 85°C and 

95°C

32 (2X)

ms

36

T

C

 > 95°C and 

105°C

16 (4X)

ms

36

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Maximum average
periodic refresh

T

C

 

 85°C

t

REFI

7.8 (64ms/8192)

μs

36

T

C

 > 85°C and 

95°C

3.9 (32ms/8192)

μs

36

T

C

 > 95°C and 

105°C

1.95 (16ms/8192)

μs

36

Self Refresh Timing

Exit self refresh to commands not requiring a
locked DLL

t

XS

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Exit self refresh to commands requiring a
locked DLL

t

XSDLL

MIN = 

t

DLLK (MIN); MAX = N/A

CK

28

Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing

t

CKESR

MIN = 

t

CKE (MIN) + CK; MAX = N/A

CK

 

Valid clocks after self refresh entry or power-
down entry

t

CKSRE

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Valid clocks before self refresh exit,
power-down exit, or reset exit

t

CKSRX

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Power-Down Timing

CKE MIN pulse width

t

CKE (MIN)

Greater of 3CK

or 7.5ns

Greater of 3CK

or 5.625ns

Greater of 3CK

or 5.625ns

Greater of 3CK

or 5ns

CK

 

Command pass disable delay

t

CPDED

MIN = 1; MAX = N/A

CK

 

Power-down entry to power-down exit tim-
ing

t

PD

MIN = 

t

CKE (MIN); MAX = 9 * tREFI

CK

 

Begin power-down period prior to CKE
registered HIGH

t

ANPD

WL - 1CK

CK

 

Power-down entry period: ODT either
synchronous or asynchronous

PDE

Greater of 

t

ANPD or 

t

RFC - REFRESH command to CKE LOW time

CK

 

Power-down exit period: ODT either
synchronous or asynchronous

PDX

t

ANPD + 

t

XPDLL

CK

 

Power-Down Entry Minimum Timing

ACTIVATE command to power-down entry

t

ACTPDEN

MIN = 1

CK

 

PRECHARGE/PRECHARGE ALL command to
power-down entry

t

PRPDEN

MIN = 1

CK

 

REFRESH command to power-down entry

t

REFPDEN

MIN = 1

CK

37

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

MRS command to power-down entry

t

MRSPDEN

MIN = 

t

MOD (MIN)

CK

 

READ/READ with auto precharge command
to power-down entry

t

RDPDEN

MIN = RL + 4 + 1

CK

 

WRITE command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRPDEN

MIN = WL + 4 + 

t

WR/

t

CK (AVG)

CK

 

BC4MRS

t

WRPDEN

MIN = WL + 2 + 

t

WR/

t

CK (AVG)

CK

 

WRITE with auto
precharge command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRAP-

DEN

MIN = WL + 4 + WR + 1

CK

 

BC4MRS

t

WRAP-

DEN

MIN = WL + 2 + WR + 1

CK

 

Power-Down Exit Timing

DLL on, any valid command, or DLL off to
commands not requiring locked DLL

t

XP

MIN = greater of 3CK or 7.5ns;

MAX = N/A

MIN = greater of 3CK or 6ns;

MAX = N/A

CK

 

Precharge power-down with DLL off to
commands requiring a locked DLL

t

XPDLL

MIN = greater of 10CK or 24ns; MAX = N/A

CK

28

ODT Timing

R

TT

 synchronous turn-on delay

ODTLon

CWL + AL - 2CK

CK

38

R

TT

 synchronous turn-off delay

ODTLoff

CWL + AL - 2CK

CK

40

R

TT

 turn-on from ODTL on reference

t

AON

–400

400

–300

300

–250

250

–225

225

ps

23, 38

R

TT

 turn-off from ODTL off reference

t

AOF

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

CK

39, 40

Asynchronous R

TT

 turn-on delay

(power-down with DLL off)

t

AONPD

MIN = 2; MAX = 8.5

ns

38

Asynchronous R

TT

 turn-off delay

(power-down with DLL off)

t

AOFPD

MIN = 2; MAX = 8.5

ns

40

ODT HIGH time with WRITE command and
BL8

ODTH8

MIN = 6; MAX = N/A

CK

 

ODT HIGH time without WRITE command or
with WRITE command and BC4

ODTH4

MIN = 4; MAX = N/A

CK

 

Dynamic ODT Timing

R

TT,nom

-to-R

TT(WR)

 change skew

ODTLcnw

WL - 2CK

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BC4

ODTLcwn4

4CK + ODTLoff

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BL8

ODTLcwn8

6CK + ODTLoff

CK

 

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

R

TT

 dynamic change skew

t

ADC

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

CK

39

Write Leveling Timing

First DQS, DQS# rising edge

t

WLMRD

40

40

40

40

CK

 

DQS, DQS# delay

t

WLDQSEN

25

25

25

25

CK

 

Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing

t

WLS

325

245

195

165

ps

 

Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing

t

WLH

325

245

195

165

ps

 

Write leveling output delay

t

WLO

0

9

0

9

0

9

0

7.5

ns

 

Write leveling output error

t

WLOE

0

2

0

2

0

2

0

2

ns

 

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Notes:

1. AC timing parameters are valid from specified T

C

 MIN to T

C

 MAX values.

2. All voltages are referenced to V

SS

.

3. Output timings are only valid for R

ON34

 output buffer selection.

4. The unit 

t

CK (AVG) represents the actual 

t

CK (AVG) of the input clock under operation.

The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.

5. AC timing and I

DD

 tests may use a V

IL

-to-V

IH

 swing of up to 900mV in the test environ-

ment, but input timing is still referenced to V

REF

 (except 

t

IS, 

t

IH, 

t

DS, and 

t

DH use the

AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between V

IL(AC)

 and V

IH(AC)

.

6. All timings that use time-based values (ns, μs, ms) should use 

t

CK (AVG) to determine the

correct number of clocks (Table 58 (page 83) uses CK or 

t

CK [AVG] interchangeably). In

the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.

7. Strobe or DQS

diff

 refers to the DQS and DQS# differential crossing point when DQS is

the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates.

The actual test load may be different. The output signal voltage reference point is
V

DDQ

/2 for single-ended signals and the crossing point for differential signals (see Figure

31 (page 75)).

9. When operating in DLL disable mode, Micron does not warrant compliance with normal

mode timings or functionality.

10. The clock’s 

t

CK (AVG) is the average clock over any 200 consecutive clocks and 

t

CK (AVG)

MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.

11. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of 

t

CK (AVG) as a long-term jitter component; however, the spread

spectrum may not use a clock rate below 

t

CK (AVG) MIN.

12. The clock’s 

t

CH (AVG) and 

t

CL (AVG) are the average half clock period over any 200 con-

secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.

13. The period jitter (

t

JITper) is the maximum deviation in the clock period from the average

or nominal clock. It is allowed in either the positive or negative direction.

14.

t

CH (ABS) is the absolute instantaneous clock high pulse width as measured from one

rising edge to the following falling edge.

15.

t

CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-

ing edge to the following rising edge.

16. The cycle-to-cycle jitter 

t

JITcc is the amount the clock period can deviate from one cycle

to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.

17. The cumulative jitter error 

t

ERRnper, where 

n

 is the number of clocks between 2 and 50,

is the amount of clock time allowed to accumulate consecutively away from the average
clock over 

n

 number of clock cycles.

18.

t

DS (base) and 

t

DH (base) values are for a single-ended 1 V/ns slew rate DQs and 2 V/ns

slew rate differential DQS, DQS#; when DQ single-ended slew rate is 2V/ns, the DQS dif-
ferential slew rate is 4V/ns.

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19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-

tion edge to its respective data strobe signal (DQS, DQS#) crossing.

20. The setup and hold times are listed converting the base specification values (to which

derating tables apply) to V

REF

 when the slew rate is 1 V/ns. These values, with a slew rate

of 1 V/ns, are for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated

by the actual 

t

JITper (larger of 

t

JITper (MIN) or 

t

JITper (MAX) of the input clock (output

deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-

rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting 

t

ERR10per (MAX): 

t

DQSCK

(MIN), 

t

LZDQS (MIN), 

t

LZDQ (MIN), and 

t

AON (MIN). The following parameters are re-

quired to be derated by subtracting 

t

ERR10per (MIN): 

t

DQSCK (MAX), 

t

HZ (MAX), 

t

LZDQS

(MAX), 

t

LZDQ MAX, and 

t

AON (MAX). The parameter 

t

RPRE (MIN) is derated by subtract-

ing 

t

JITper (MAX), while 

t

RPRE (MAX) is derated by subtracting 

t

JITper (MIN).

24. The maximum preamble is bound by 

t

LZDQS (MAX).

25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-

spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.

26. The 

t

DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.

27. The maximum postamble is bound by 

t

HZDQS (MAX).

28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-

mands. In addition, after any change of latency 

t

XPDLL, timing must be met.

29.

t

IS (base) and 

t

IH (base) values are for a single-ended 1 V/ns control/command/address

slew rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its

respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.

31. For these parameters, the DDR3L SDRAM device supports 

t

n

PARAM (

n

CK) = RU(

t

PARAM

[ns]/

t

CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-

ple, the device will support 

t

n

RP (

n

CK) = RU(

t

RP/

t

CK[AVG]) if all input clock jitter specifi-

cations are met. This means that for DDR3-800 6-6-6, of which 

t

RP = 5ns, the device will

support 

t

n

RP = RU(

t

RP/

t

CK[AVG]) = 6 as long as the input clock jitter specifications are

met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.

32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-

ternal PRECHARGE command until 

t

RAS (MIN) has been satisfied.

33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for 

t

WR.

34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL

• For BC4 (OTF): Rising clock edge four clock cycles after WL

• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL

35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in

High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.

36. The refresh period is 64ms when T

C

 is less than or equal to 85°C. This equates to an aver-

age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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least once every 70.3μs. When T

C

 is greater than 85°C, but less the 95°C, the refresh peri-

od is 32ms. When T

C

 is greater than 95°C, but less the 105°C, the refresh period is 16ms.

37. Although CKE is allowed to be registered LOW after a REFRESH command when

t

REFPDEN (MIN) is satisfied, there are cases where additional time such as 

t

XPDLL (MIN)

is required.

38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to

turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 24 (page 63). This output load is used for ODT timings
(see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-
mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.

39. Half-clock output parameters must be derated by the actual 

t

ERR10per and 

t

JITdty when

input clock jitter is present. This results in each parameter becoming larger. The parame-
ters 

t

ADC (MIN) and

 t

AOF (MIN) are each required to be derated by subtracting both

t

ERR10per (MAX) and 

t

JITdty (MAX). The parameters 

t

ADC (MAX) and 

t

AOF (MAX) are

required to be derated by subtracting both 

t

ERR10per (MAX) and 

t

JITdty (MAX).

40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT

turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31
(page 75)).

41. Pulse width of a input signal is defined as the width between the first crossing of

V

REF(DC)

 and the consecutive crossing of V

REF(DC)

.

42. Should the clock rate be larger than 

t

RFC (MIN), an AUTO REFRESH command should

have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.

43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.

44. When two V

IH(AC)

 values (and two corresponding V

IL(AC)

 values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
V

IH(AC)

 value may be used for address/command inputs and the other V

IH(AC)

 value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC175),min

 and

V

IH(AC150),min

 (corresponding V

IL(AC175),min

 and V

IL(AC150),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC175),min

 with 

t

IS(AC175) of 200ps or V

IH(AC150),min

with 

t

IS(AC150) of 350ps; independently, the data inputs must use either V

IH(AC175),min

with 

t

DS(AC175) of 75ps or V

IH(AC150),min

 with 

t

DS(AC150) of 125ps.

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Electrical Characteristics and AC Operating Conditions

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Electrical Characteristics and AC Operating Conditions

Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Clock Timing

Clock period average:
DLL disable mode

T

= 0°C to 85°C

t

CK

(DLL_DIS)

8

7800

8

7800

ns

9, 42

T

C

 = >85°C to 95°C

8

3900

8

3900

ns

42

Clock period average: DLL enable mode

t

CK (AVG)

See Speed Bin Tables for 

t

CK range allowed ns

10, 11

High pulse width average

t

CH (AVG)

0.47

0.53

0.47

0.53

CK

12

Low pulse width average

t

CL (AVG)

0.47

0.53

0.47

0.53

CK

12

Clock period jitter

DLL locked

t

JITper

–60

60

–50

50

ps

13

DLL locking

t

JITper,lck

–50

50

–40

40

ps

13

Clock absolute period

t

CK (ABS)

MIN = 

t

CK (AVG) MIN +

t

JITper MIN; MAX =

t

CK (AVG) MAX +

t

JITper MAX ps

 

Clock absolute high pulse width

t

CH (ABS)

0.43

0.43

t

CK

(AVG)

14

Clock absolute low pulse width

t

CL (ABS)

0.43

0.43

t

CK

(AVG)

15

Cycle-to-cycle jitter

DLL locked

t

JITcc

120

120

ps

16

DLL locking

t

JITcc,lck

100

100

ps

16

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Cumulative error across 2 cycles

t

ERR2per

–88

88

–74

74

ps

17

3 cycles

t

ERR3per

–105

105

–87

87

ps

17

4 cycles

t

ERR4per

–117

117

–97

97

ps

17

5 cycles

t

ERR5per

–126

126

–105

105

ps

17

6 cycles

t

ERR6per

–133

133

–111

111

ps

17

7 cycles

t

ERR7per

–139

139

–116

116

ps

17

8 cycles

t

ERR8per

–145

145

–121

121

ps

17

9 cycles

t

ERR9per

–150

150

–125

125

ps

17

10 cycles

t

ERR10per

–154

154

–128

128

ps

17

11 cycles

t

ERR11per

–158

158

–132

132

ps

17

12 cycles

t

ERR12per

–161

161

–134

134

ps

17

= 13, 14 . . . 49, 50

cycles

t

ERR

n

per

t

ERR

n

per MIN = (1 + 0.68ln[

n

]) × 

t

JITper MIN

t

ERR

n

per MAX = (1 + 0.68ln[

n

]) × 

t

JITper MAX

ps

17

DQ Input Timing

Data setup time to
DQS, DQS#

Base (specification)
@ 2 V/ns

t

DS

(AC130)

70

55

ps

18, 19

V

REF

 @ 2 V/ns

135

120.5

ps

19, 20

Data hold time from
DQS, DQS#

Base (specification)
@ 2 V/ns

t

DH

(DC90)

75

60

ps

18, 19

V

REF

 @ 2 V/ns

110

105

ps

19, 20

Minimum data pulse width

t

DIPW

320

280

ps

41

DQ Output Timing

DQS, DQS# to DQ skew, per access

t

DQSQ

85

75

ps

 

DQ output hold time from DQS, DQS#

t

QH

0.38

0.38

t

CK

(AVG)

21

DQ Low-Z time from CK, CK#

t

LZDQ

–390

195

–360

180

ps

22, 23

DQ High-Z time from CK, CK#

t

HZDQ

195

180

ps

22, 23

DQ Strobe Input Timing

DQS, DQS# rising to CK, CK# rising

t

DQSS

–0.27

0.27

–0.27

0.27

CK

25

DQS, DQS# differential input low pulse width

t

DQSL

0.45

0.55

0.45

0.55

CK

 

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

DQS, DQS# differential input high pulse
width

t

DQSH

0.45

0.55

0.45

0.55

CK

 

DQS, DQS# falling setup to CK, CK# rising

t

DSS

0.18

0.18

CK

25

DQS, DQS# falling hold from CK, CK# rising

t

DSH

0.18

0.18

CK

25

DQS, DQS# differential WRITE preamble

t

WPRE

0.9

0.9

CK

 

DQS, DQS# differential WRITE postamble

t

WPST

0.3

0.3

CK

 

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK#

t

DQSCK

–195

195

–180

180

ps

23

DQS, DQS# rising to/from rising CK, CK#
when DLL is disabled

t

DQSCK

(DLL_DIS)

1

10

1

10

ns

26

DQS, DQS# differential output high time

t

QSH

0.40

0.40

CK

21

DQS, DQS# differential output low time

t

QSL

0.40

0.40

CK

21

DQS, DQS# Low-Z time (RL - 1)

t

LZDQS

–390

195

–360

180

ps

22, 23

DQS, DQS# High-Z time (RL + BL/2)

t

HZDQS

195

180

ps

22, 23

DQS, DQS# differential READ preamble

t

RPRE

0.9

Note 24

0.9

Note 24

CK

23, 24

DQS, DQS# differential READ postamble

t

RPST

0.3

Note 27

0.3

Note 27

CK

23, 27

Command and Address Timing

DLL locking time

t

DLLK

512

512

CK

28

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC135)

65

60

ps

29, 30, 

44

V

REF

 @ 1 V/ns

200

195

ps

20, 30

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC125)

150

135

ps

29, 30, 

44

V

REF

 @ 1 V/ns

275

260

ps

20, 30

CTRL, CMD, ADDR hold
from CK,CK#

Base (specification)

t

IH

(DC90)

110

105

ps

29, 30

V

REF

 @ 1 V/ns

200

195

ps

20, 30

Minimum CTRL, CMD, ADDR pulse width

t

IPW

535

470

ps

41

ACTIVATE to internal READ or WRITE delay

t

RCD

See Speed Bin Tables for 

t

RCD

ns

31

PRECHARGE command period

t

RP

See Speed Bin Tables for 

t

RP

ns

31

ACTIVATE-to-PRECHARGE command period

t

RAS

See Speed Bin Tables for 

t

RAS

ns

31, 32

ACTIVATE-to-ACTIVATE command period

t

RC

See Speed Bin Tables for 

t

RC

ns

31, 43

4Gb: x4, x8, x16 DDR3L SDRAM

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

ACTIVATE-to-ACTIVATE
minimum command pe-
riod

1KB page size

t

RRD

MIN = greater of 4CK or 5ns

CK

31

2KB page size

MIN = greater of 4CK or 6ns

CK

31

Four ACTIVATE
windows

1KB page size

t

FAW

27

25

ns

31

2KB page size

35

35

ns

31

Write recovery time

t

WR

MIN = 15ns; MAX = N/A

ns

31, 32, 

33

Delay from start of internal WRITE transac-
tion to internal READ command

t

WTR

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 34

READ-to-PRECHARGE time

t

RTP

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 32

CAS#-to-CAS# command delay

t

CCD

MIN = 4CK; MAX = N/A

CK

 

Auto precharge write recovery + precharge
time

t

DAL

MIN = WR + 

t

RP/

t

CK (AVG); MAX = N/A

CK

 

MODE REGISTER SET command cycle time

t

MRD

MIN = 4CK; MAX = N/A

CK

 

MODE REGISTER SET command update delay

t

MOD

MIN = greater of 12CK or 15ns; MAX = N/A

CK

 

MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit

t

MPRR

MIN = 1CK; MAX = N/A

CK

 

Calibration Timing

ZQCL command: Long
calibration time

POWER-UP and RE-
SET operation

t

ZQinit

MIN = N/A

MAX = MAX(512nCK, 640ns)

CK

 

Normal operation

t

ZQoper

MIN = N/A

MAX = max(256nCK, 320ns)

CK

 

ZQCS command: Short calibration time

MIN = N/A

MAX = max(64nCK, 80ns) 

t

ZQCS

CK

 

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command

t

XPR

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Begin power supply ramp to power supplies
stable

t

VDDPR

MIN = N/A; MAX = 200

ms

 

RESET# LOW to power supplies stable

t

RPS

MIN = 0; MAX = 200

ms

 

RESET# LOW to I/O and R

TT

 High-Z

t

IOZ

MIN = N/A; MAX = 20

ns

35

Refresh Timing

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

REFRESH-to-ACTIVATE or REFRESH
command period

t

RFC – 1Gb

MIN = 110; MAX = 70,200

ns

 

t

RFC – 2Gb

MIN = 160; MAX = 70,200

ns

 

t

RFC – 4Gb

MIN = 260; MAX = 70,200

ns

 

t

RFC – 8Gb

MIN = 350; MAX = 70,200

ns

 

Maximum refresh
period

T

C

 

 85°C

64 (1X)

ms

36

T

C

 > 85°C and 

95°C

32 (2X)

ms

36

T

C

 > 95°C and 

105°C

16 (4X)

ms

36

Maximum average
periodic refresh

T

C

 

 85°C

t

REFI

7.8 (64ms/8192)

μs

36

T

C

 > 85°C and 

95°C

3.9 (32ms/8192)

μs

36

T

C

 > 95°C and 

105°C

1.95 (16ms/8192)

μs

36

Self Refresh Timing

Exit self refresh to commands not requiring a
locked DLL

t

XS

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Exit self refresh to commands requiring a
locked DLL

t

XSDLL

MIN = 

t

DLLK (MIN);

MAX = N/A

CK

28

Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing

t

CKESR

MIN = 

t

CKE (MIN) + CK; MAX = N/A

CK

 

Valid clocks after self refresh entry or power-
down entry

t

CKSRE

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Valid clocks before self refresh exit,
power-down exit, or reset exit

t

CKSRX

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Power-Down Timing

CKE MIN pulse width

t

CKE (MIN)

Greater of 3CK or 5ns

CK

 

Command pass disable delay

t

CPDED

MIN = 2;

MAX = N/A

CK

 

Power-down entry to power-down exit tim-
ing

t

PD

MIN = 

t

CKE (MIN);

MAX = 9 * tREFI

CK

 

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Begin power-down period prior to CKE
registered HIGH

t

ANPD

WL - 1CK

CK

 

Power-down entry period: ODT either
synchronous or asynchronous

PDE

Greater of 

t

ANPD or 

t

RFC - REFRESH command to CKE LOW time

CK

 

Power-down exit period: ODT either
synchronous or asynchronous

PDX

t

ANPD + 

t

XPDLL

CK

 

Power-Down Entry Minimum Timing

ACTIVATE command to power-down entry

t

ACTPDEN

MIN = 2

CK

 

PRECHARGE/PRECHARGE ALL command to
power-down entry

t

PRPDEN

MIN = 2

CK

 

REFRESH command to power-down entry

t

REFPDEN

MIN = 2

CK

37

MRS command to power-down entry

t

MRSPDEN

MIN = 

t

MOD (MIN)

CK

 

READ/READ with auto precharge command
to power-down entry

t

RDPDEN

MIN = RL + 4 + 1

CK

 

WRITE command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRPDEN

MIN = WL + 4 +

t

WR/

t

CK (AVG)

CK

 

BC4MRS

t

WRPDEN

MIN = WL + 2 +

t

WR/

t

CK (AVG)

CK

 

WRITE with auto pre-
charge command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRAP-

DEN

MIN = WL + 4 + WR + 1

CK

 

BC4MRS

t

WRAP-

DEN

MIN = WL + 2 + WR + 1

CK

 

Power-Down Exit Timing

DLL on, any valid command, or DLL off to
commands not requiring locked DLL

t

XP

MIN = greater of 3CK or 6ns;

MAX = N/A

CK

 

Precharge power-down with DLL off to
commands requiring a locked DLL

t

XPDLL

MIN = greater of 10CK or 24ns; MAX = N/A

CK

28

ODT Timing

R

TT

 synchronous turn-on delay

ODTL on

CWL + AL - 2CK

CK

38

R

TT

 synchronous turn-off delay

ODTL off

CWL + AL - 2CK

CK

40

R

TT

 turn-on from ODTL on reference

t

AON

–195

195

–180

180

ps

23, 38

R

TT

 turn-off from ODTL off reference

t

AOF

0.3

0.7

0.3

0.7

CK

39, 40

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Asynchronous R

TT

 turn-on delay

(power-down with DLL off)

t

AONPD

MIN = 2; MAX = 8.5

ns

38

Asynchronous R

TT

 turn-off delay

(power-down with DLL off)

t

AOFPD

MIN = 2; MAX = 8.5

ns

40

ODT HIGH time with WRITE command and
BL8

ODTH8

MIN = 6; MAX = N/A

CK

 

ODT HIGH time without WRITE command or
with WRITE command and BC4

ODTH4

MIN = 4; MAX = N/A

CK

 

Dynamic ODT Timing

R

TT,nom

-to-R

TT(WR)

 change skew

ODTLcnw

WL - 2CK

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BC4

ODTLcwn4

4CK + ODTLoff

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BL8

ODTLcwn8

6CK + ODTLoff

CK

 

R

TT

 dynamic change skew

t

ADC

0.3

0.7

0.3

0.7

CK

39

Write Leveling Timing

First DQS, DQS# rising edge

t

WLMRD

40

40

CK

 

DQS, DQS# delay

t

WLDQSEN

25

25

CK

 

Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing

t

WLS

140

125

ps

 

Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing

t

WLH

140

125

ps

 

Write leveling output delay

t

WLO

0

7.5

0

7

ns

 

Write leveling output error

t

WLOE

0

2

0

2

ns

 

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Notes:

1. AC timing parameters are valid from specified T

C

 MIN to T

C

 MAX values.

2. All voltages are referenced to V

SS

.

3. Output timings are only valid for R

ON34

 output buffer selection.

4. The unit 

t

CK (AVG) represents the actual 

t

CK (AVG) of the input clock under operation.

The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.

5. AC timing and I

DD

 tests may use a V

IL

-to-V

IH

 swing of up to 900mV in the test environ-

ment, but input timing is still referenced to V

REF

 (except 

t

IS, 

t

IH, 

t

DS, and 

t

DH use the

AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
(DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in
the range between V

IL(AC)

 and V

IH(AC)

.

6. All timings that use time-based values (ns, μs, ms) should use 

t

CK (AVG) to determine the

correct number of clocks (Table 59 (page 93) uses CK or 

t

CK [AVG] interchangeably). In

the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.

7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is

the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates.

The actual test load may be different. The output signal voltage reference point is
V

DDQ

/2 for single-ended signals and the crossing point for differential signals (see Figure

31 (page 75)).

9. When operating in DLL disable mode, Micron does not warrant compliance with normal

mode timings or functionality.

10. The clock’s 

t

CK (AVG) is the average clock over any 200 consecutive clocks and 

t

CK (AVG)

MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.

11. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of 

t

CK (AVG) as a long-term jitter component; however, the spread

spectrum may not use a clock rate below 

t

CK (AVG) MIN.

12. The clock’s 

t

CH (AVG) and 

t

CL (AVG) are the average half clock period over any 200 con-

secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.

13. The period jitter (

t

JITper) is the maximum deviation in the clock period from the average

or nominal clock. It is allowed in either the positive or negative direction.

14.

t

CH (ABS) is the absolute instantaneous clock high pulse width as measured from one

rising edge to the following falling edge.

15.

t

CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-

ing edge to the following rising edge.

16. The cycle-to-cycle jitter 

t

JITcc is the amount the clock period can deviate from one cycle

to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.

17. The cumulative jitter error 

t

ERRnper, where 

n

 is the number of clocks between 2 and 50,

is the amount of clock time allowed to accumulate consecutively away from the average
clock over 

n

 number of clock cycles.

18.

t

DS (base) and 

t

DH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at

2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#; when
DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns.

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19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-

tion edge to its respective data strobe signal (DQS, DQS#) crossing.

20. The setup and hold times are listed converting the base specification values (to which

derating tables apply) to V

REF

 when the slew rate is 1 V/ns (DQs are at 2V/ns for

DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns
for DDR3-1866 and DDR3-2133), are for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated

by the actual 

t

JITper (larger of 

t

JITper (MIN) or 

t

JITper (MAX) of the input clock (output

deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-

rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting 

t

ERR10per (MAX): 

t

DQSCK

(MIN), 

t

LZDQS (MIN), 

t

LZDQ (MIN), and 

t

AON (MIN). The following parameters are re-

quired to be derated by subtracting 

t

ERR10per (MIN): 

t

DQSCK (MAX), 

t

HZ (MAX), 

t

LZDQS

(MAX), 

t

LZDQ (MAX), and 

t

AON (MAX). The parameter 

t

RPRE (MIN) is derated by sub-

tracting 

t

JITper (MAX), while 

t

RPRE (MAX) is derated by subtracting 

t

JITper (MIN).

24. The maximum preamble is bound by 

t

LZDQS (MAX).

25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-

spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.

26. The 

t

DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.

27. The maximum postamble is bound by 

t

HZDQS (MAX).

28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-

mands. In addition, after any change of latency 

t

XPDLL, timing must be met.

29.

t

IS (base) and 

t

IH (base) values are for a single-ended 1 V/ns control/command/address

slew rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its

respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.

31. For these parameters, the DDR3L SDRAM device supports 

t

n

PARAM (

n

CK) = RU(

t

PARAM

[ns]/

t

CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-

ple, the device will support 

t

n

RP (

n

CK) = RU(

t

RP/

t

CK[AVG]) if all input clock jitter specifi-

cations are met. This means that for DDR3-800 6-6-6, of which 

t

RP = 5ns, the device will

support 

t

n

RP = RU(

t

RP/

t

CK[AVG]) = 6 as long as the input clock jitter specifications are

met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.

32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-

ternal PRECHARGE command until 

t

RAS (MIN) has been satisfied.

33. When operating in DLL disable mode, the greater of 5CK or 15ns is satisfied for 

t

WR.

34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL

• For BC4 (OTF): Rising clock edge four clock cycles after WL

• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL

35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in

High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.

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36. The refresh period is 64ms when T

C

 is less than or equal to 85°C. This equates to an aver-

age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at
least once every 70.3μs. When T

C

 is greater than 85°C, but less the 95°C, the refresh peri-

od is 32ms. When T

C

 is greater than 95°C, but less the 105°C, the refresh period is 16ms.

37. Although CKE is allowed to be registered LOW after a REFRESH command when

t

REFPDEN (MIN) is satisfied, there are cases where additional time such as 

t

XPDLL (MIN)

is required.

38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to

turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 24 (page 63). This output load is used for ODT timings
(see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-
mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.

39. Half-clock output parameters must be derated by the actual 

t

ERR10per and 

t

JITdty when

input clock jitter is present. This results in each parameter becoming larger. The parame-
ters 

t

ADC (MIN) and

 t

AOF (MIN) are each required to be derated by subtracting both

t

ERR10per (MAX) and 

t

JITdty (MAX). The parameters 

t

ADC (MAX) and 

t

AOF (MAX) are

required to be derated by subtracting both 

t

ERR10per (MAX) and 

t

JITdty (MAX).

40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT

turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31
(page 75)).

41. Pulse width of a input signal is defined as the width between the first crossing of

V

REF(DC)

 and the consecutive crossing of V

REF(DC)

.

42. Should the clock rate be larger than 

t

RFC (MIN), an AUTO REFRESH command should

have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.

43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.

44. When two V

IH(AC)

 values (and two corresponding V

IL(AC)

 values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
V

IH(AC)

 value may be used for address/command inputs and the other V

IH(AC)

 value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC175),min

 and

V

IH(AC150),min

 (corresponding V

IL(AC175),min

 and V

IL(AC150),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC175),min

 with 

t

IS(AC175) of 200ps or V

IH(AC150),min

with 

t

IS(AC150) of 350ps; independently, the data inputs must use either V

IH(AC175),min

with 

t

DS(AC175) of 75ps or V

IH(AC150),min

 with 

t

DS(AC150) of 125ps.

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Command and Address Setup, Hold, and Derating

The total 

t

IS (setup time) and 

t

IH (hold time) required is calculated by adding the data

sheet 

t

IS (base) and 

t

IH (base) values (see Table 60; values come from the Electrical

Characteristics and AC Operating Conditions table) to the 

ǻ

t

IS and 

ǻ

t

IH derating values

(see Table 61 (page 104), Table 62 (page 104) or Table 63 (page 104)) respectively. Ex-
ample: 

t

IS (total setup time) = 

t

IS (base) + 

ǻ

t

IS. For a valid transition, the input signal

has to remain above/below V

IH(AC)

/V

IL(AC)

 for some time 

t

VAC (see Table 64 (page 105)).

Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V

IH(AC)

/V

IL(AC)

 at the time of the rising clock transi-

tion), a valid input signal is still required to complete the transition and to reach
V

IH(AC)

/V

IL(AC)

 (see Figure 15 (page 53) for input signal requirements). For slew rates that

fall between the values listed in Table 61 (page 104) and Table 63 (page 104), the derat-
ing values may be obtained by linear interpolation.

Setup (

t

IS) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

REF(DC)

 and the first crossing of V

IH(AC)min

. Setup (

t

IS) nominal slew rate

for a falling signal is defined as the slew rate between the last crossing of V

REF(DC)

 and

the first crossing of V

IL(AC)max

. If the actual signal is always earlier than the nominal slew

rate line between the shaded V

REF(DC)

-to-AC region, use the nominal slew rate for derat-

ing value (see Figure 34 (page 106)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded V

REF(DC)

-to-AC region, the slew rate of a tangent

line to the actual signal from the AC level to the DC level is used for derating value (see 
Figure 36 (page 108)).

Hold (

t

IH) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

IL(DC)max

 and the first crossing of V

REF(DC)

. Hold (

t

IH) nominal slew rate

for a falling signal is defined as the slew rate between the last crossing of V

IH(DC)min

 and

the first crossing of V

REF(DC)

. If the actual signal is always later than the nominal slew

rate line between the shaded DC-to-V

REF(DC)

 region, use the nominal slew rate for derat-

ing value (see Figure 35 (page 107)). If the actual signal is earlier than the nominal slew
rate line anywhere between the shaded DC-to-V

REF(DC)

 region, the slew rate of a tangent

line to the actual signal from the DC level to the V

REF(DC)

 level is used for derating value

(see Figure 37 (page 109)).

Table 60: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based

Symbol

800

1066

1333

1600

1866

2133

Unit

Reference

t

IS(base, AC160)

215

140

80

60

ps

V

IH(AC)

/V

IL(AC)

t

IS(base, AC135)

365

290

205

185

65

60

ps

V

IH(AC)

/V

IL(AC)

t

IS(base, AC125)

150

135

ps

V

IH(AC)

/V

IL(AC)

t

IH(base, DC90)

285

210

150

130

110

105

ps

V

IH(DC)

/V

IL(DC)

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Table 61: DDR3L-800/1066 Derating Values 

t

IS/

t

IH – AC160/DC90-Based

˂

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

2.0

80

45

80

45

80

45

88

53

96

61

104

69

112

79

120

95

1.5

53

30

53

30

53

30

61

38

69

46

77

54

85

64

93

80

1.0

0

0

0

0

0

0

8

8

16

16

24

24

32

34

40

50

0.9

–1

–3

–1

–3

–1

–3

7

5

15

13

23

21

31

31

39

47

0.8

–3

–8

–3

–8

–3

–8

5

1

13

9

21

17

29

27

37

43

0.7

–5

–13

–5

–13

–5

–13

3

–5

11

3

19

11

27

21

35

37

0.6

–8

–20

–8

–20

–8

–20

0

–12

8

–4

16

4

24

14

32

30

0.5

–20

–30

–20

–30

–20

–30

–12

–22

–4

–14

4

–6

12

4

20

20

0.4

–40

–45

–40

–45

–40

–45

–32

–37

–24

–29

–16

–21

–8

–11

0

5

Table 62: DDR3L-800/1066/1333/1600 Derating Values for 

t

IS/

t

IH – AC135/DC90-Based

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

2.0

68

45

68

45

68

45

76

53

84

61

92

69

100

79

108

95

1.5

45

30

45

30

45

30

53

38

61

46

69

54

77

64

85

80

1.0

0

0

0

0

0

0

8

8

16

16

24

24

32

34

40

50

0.9

2

–3

2

–3

2

–3

10

5

18

13

26

21

34

31

42

47

0.8

3

–8

3

–8

3

–8

11

1

19

9

27

17

35

27

43

43

0.7

6

–13

6

–13

6

–13

14

–5

22

3

30

11

38

21

46

37

0.6

9

–20

9

–20

9

–20

17

–12

25

–4

33

4

41

14

49

30

0.5

5

–30

5

–30

5

–30

13

–22

21

–14

29

–6

37

4

45

20

0.4

–3

–45

–3

–45

–3

–45

6

–37

14

–29

22

–21

30

–11

38

5

Table 63: DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

2.0

63

45

63

45

63

45

71

53

79

61

87

69

95

79

103

95

1.5

42

30

42

30

42

30

50

38

58

46

66

54

74

64

82

80

4Gb: x4, x8, x16 DDR3L SDRAM

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Table 63: DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based (Continued)

˂

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

1.0

0

0

0

0

0

0

8

8

16

16

24

24

32

34

40

50

0.9

3

–3

3

–3

3

–3

11

5

19

13

27

21

35

31

43

47

0.8

6

–8

6

–8

6

–8

14

1

22

9

30

17

38

27

46

43

0.7

10

–13

10

–13

10

–13

18

–5

26

3

34

11

42

21

50

37

0.6

16

–20

16

–20

16

–20

24

–12

32

–4

40

4

48

14

56

30

0.5

15

–30

15

–30

15

–30

23

–22

31

–14

39

–6

47

4

55

20

0.4

13

–45

13

–45

13

–45

21

–37

29

–29

37

–21

45

–11

53

5

Table 64: DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL[AC]

) for Valid ADD/CMD

Transition

Slew Rate (V/ns)

DDR3L-800/1066/1333/1600

DDR3L-1866/2133

t

VAC at 160mV (ps)

t

VAC at 135mV (ps)

t

VAC at 135mV (ps)

t

VAC at 125mV (ps)

>2.0

200

213

200

205

2.0

200

213

200

205

1.5

173

190

178

184

1.0

120

145

133

143

0.9

102

130

118

129

0.8

80

111

99

111

0.7

51

87

75

89

0.6

13

55

43

59

0.5

Note 1

10

Note 1

18

<0.5

Note 1

10

Note 1

18

Note:

1. Rising input signal shall become equal to or greater than V

IH(AC)

 level and Falling input

signal shall become equal to or less than V

IL(AC)

 level.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Figure 34: Nominal Slew Rate and 

t

VAC for 

t

IS (Command and Address – Clock)

V

SS

Setup slew rate

rising signal

Setup slew rate

falling signal

¨

TF

¨

TR

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal

slew rate

V

REF

 to AC

region

tVAC

tVAC

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

Nominal

slew rate

V

REF

 to AC

region

V

REF(DC)

 - V

IL(AC)max

¨

TF

V

IH(AC)min

 - V

REF(DC)

¨

TR

Note:

1. The clock and the strobe are drawn on different time scales.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Figure 35: Nominal Slew Rate for 

t

IH (Command and Address – Clock)

V

SS

Hold slew rate

falling signal

Hold slew rate

rising signal 

ǻ

TR

ǻ

TF

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal

slew rate

DC to V

REF

region

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

DC to V

REF

region

Nominal

slew rate

V

REF(DC)

 - V

IL(DC)max

ǻ

TR

V

IH(DC)min

 - V

REF(DC)

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Figure 36: Tangent Line for 

t

IS (Command and Address – Clock)

V

SS

Setup slew rate

rising signal

Setup slew rate

falling signal =

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Tangent

line

V

REF

 to AC

region

Nominal

line

tVAC

tVAC

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

V

REF

 to AC

region

Tangent

line

Nominal

line

Tangent line (V

IH(DC)min

 - V

REF(DC)

)

Tangent line (V

REF(DC)

 - V

IL(AC)max

)

¨

TR

¨

TR

¨

TF

¨

TF

Note:

1. The clock and the strobe are drawn on different time scales.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Figure 37: Tangent Line for 

t

IH (Command and Address – Clock)

V

SS

Hold slew rate

falling signal =

V

DDQ

 V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL( DC)max

V

IL( AC)max

Tangen t

line

DC to V

REF

region

Hold slew rate

rising signal

=

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

DC to V

REF

region

Tangen t

line

Nominal

line

Nominal

line

Tangent line (V

REF(DC)

 - V

IL(DC)max

)

Tangent line (V

IH(DC)min

 - V

REF(DC)

)

ǻ

TR

ǻ

TR

ǻ

TR

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Data Setup, Hold, and Derating

The total 

t

DS (setup time) and 

t

DH (hold time) required is calculated by adding the data

sheet 

t

DS (base) and 

t

DH (base) values (see Table 65 (page 110); values come from the

Electrical Characteristics and AC Operating Conditions table) to the 

ǻ

t

DS and 

ǻ

t

DH de-

rating values (see Table 66 (page 111), Table 67 (page 111), or Table 68 (page 112)) re-
spectively. Example: 

t

DS (total setup time) = 

t

DS (base) + 

ǻ

t

DS. For a valid transition, the

input signal has to remain above/below V

IH(AC)

/V

IL(AC)

 for some time 

t

VAC (see Table 69

(page 113)).

Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V

IH(AC)

/V

IL(AC)

) at the time of the rising clock transi-

tion), a valid input signal is still required to complete the transition and to reach
V

IH

/V

IL(AC)

. For slew rates that fall between the values listed in Table 66 (page 111), Ta-

ble 67 (page 111), or Table 68 (page 112), the derating values may obtained by linear
interpolation.

Setup (

t

DS) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

REF(DC)

 and the first crossing of V

IH(AC)min

. Setup (

t

DS) nominal slew

rate for a falling signal is defined as the slew rate between the last crossing of V

REF(DC)

and the first crossing of V

IL(AC)max

. If the actual signal is always earlier than the nominal

slew rate line between the shaded V

REF(DC)

-to-AC region, use the nominal slew rate for

derating value (see Figure 38 (page 114)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded V

REF(DC)

-to-AC region, the slew rate of a

tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 40 (page 116)).

Hold (

t

DH) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

IL(DC)max

 and the first crossing of V

REF(DC)

. Hold (

t

DH) nominal slew

rate for a falling signal is defined as the slew rate between the last crossing of V

IH(DC)min

and the first crossing of V

REF(DC)

. If the actual signal is always later than the nominal

slew rate line between the shaded DC-to-V

REF(DC)

 region, use the nominal slew rate for

derating value (see Figure 39 (page 115)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-V

REF(DC)

 region, the slew rate of a

tangent line to the actual signal from the DC-to-V

REF(DC)

 region is used for derating val-

ue (see Figure 41 (page 117)).

Table 65: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based

Symbol

800

1066

1333

1600

1866

2133

Unit

Reference

t

DS (base) AC160

90

40

ps

V

IH(AC)

/V

IL(AC)

t

DS (base) AC135

140

90

45

25

ps

t

DS (base) AC130

-

-

-

-

70

55

ps

t

DH (base) DC90

160

110

75

55

ps

t

DH (base) DC90

75

60

ps

Slew Rate Referenced

1

1

1

1

2

2

V/ns

4Gb: x4, x8, x16 DDR3L SDRAM

Data Setup, Hold, and Derating

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Table 66: DDR3L Derating Values for 

t

DS/

t

DH – AC160/DC90-Based

˂

˂

t

DS, 

˂

t

DH Derating (ps) – AC/DC-Based

DQ Slew

Rate V/ns

DQS, DQS# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

2.0

80

45

80

45

80

45

 

 

 

 

 

 

 

 

 

 

1.5

53

30

53

30

53

30

61

38

 

 

 

 

 

 

 

 

1.0

0

0

0

0

0

0

8

8

16

16

 

 

 

 

 

 

0.9

 

 –1

–3

–1

–3

7

5

15

13

23

21

 

 

 

 

0.8

 

 

 

 –3

–8

5

1

13

9

21

17

29

27

 

 

0.7

 

 

 

 

 

 –3

–5

11

3

19

11

27

21

35

37

0.6

 

 

 

 

 

 

 

 8

–4

16

4

24

14

32

30

0.5

 

 

 

 

 

 

 

 

 

 

4

6

12

4

20

20

0.4

 

 

 

 

 

 

 

 

 

 

 

 –8

–11

0

5

Table 67: DDR3L Derating Values for 

t

DS/

t

DH – AC135/DC90-Based

˂

t

DS, 

˂

t

DH Derating (ps) – AC/DC-Based

DQ Slew

Rate V/ns

DQS, DQS# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

2.0

68

45

68

45

68

45

 

 

 

 

 

 

 

 

 

 

1.5

45

30

45

30

45

30

53

38

 

 

 

 

 

 

 

 

1.0

0

0

0

0

0

0

8

8

16

16

 

 

 

 

 

 

0.9

 

 

2

–3

2

–3

10

5

18

13

26

21

 

 

 

 

0.8

 

 

 

 3

–8

11

1

19

9

27

17

35

27

 

 

0.7

 

 

 

 

 

 14

–5

22

3

30

11

38

21

46

37

0.6

 

 

 

 

 

 

 

 25

–4

33

4

41

14

49

30

0.5

 

 

 

 

 

 

 

 

 

 39

–6

37

4

45

20

0.4

 

 

 

 

 

 

 

 

 

 

 

 30

–11

38

5

4Gb: x4, x8, x16 DDR3L SDRAM

Data Setup, Hold, and Derating

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Table 68: DDR3L Derating Values for 

t

DS/

t

DH – AC130/DC90-Based at 2V/ns

Shaded cells indicate slew rate combinations not supported

˂

˂

t

DS, 

˂

t

DH Derating (ps) – AC/DC-Based

DQ Slew Rate V/ns

DQS, DQS# Differential Slew Rate

8.0 V/ns

7.0 V/ns

6.0 V/ns

5.0 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

4.0

33

23

33

23

33

23

3.5

28

19

28

19

28

19

28

19

3.0

22

15

22

15

22

15

22

15

22

15

2.5

13

9

13

9

13

9

13

9

13

9

2.0

0

0

0

0

0

0

0

0

0

0

1.5

–22

–15

–22

–15

–22

–15

–22

–15

–14

–7

1.0

–65

–45

–65

–45

–65

–45

–57

–37

–49

–29

0.9

–62

–48

–62

–48

–54

–40

–46

–32

–38

–24

0.8

–61

–53

–53

–45

–45

–37

–37

–29

–29

–19

0.7

–49

–50

–41

-42

–33

–34

–25

–24

–17

–8

0.6

–37

-49

–29

–41

–21

–31

–13

–15

0.5

–31

–51

–23

–41

–15

–25

0.4

–28

–56

–20

–40

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Table 69: DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL(AC)

) for Valid DQ Transition

Slew Rate (V/ns)

DDR3L-800/1066 160mV

(ps) min

DDR3L-800/1066/1333

135mV (ps) min

DDR3L-1866/2133

130mV (ps) min

>2.0

165

113

95

2.0

165

113

95

1.5

138

90

73

1.0

85

45

30

0.9

67

30

16

0.8

45

11

Note 1

0.7

16

Note 1

0.6

Note 1

Note 1

0.5

Note 1

Note 1

<0.5

Note 1

Note 1

Note:

1. Rising input signal shall become equal to or greater than V

IH(AC)

 level and Falling input

signal shall become equal to or less than V

IL(AC)

 level.

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Figure 38: Nominal Slew Rate and 

t

VAC for 

t

DS (DQ – Strobe)

V

SS

Setup slew rate
rising signal

Setup slew rate
falling signal

ǻ

TF

ǻ

TR

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal

slew rate

V

REF

 to AC

 region

tVAC

tVAC

tDH

tDS

DQS

DQS#

tDH

tDS

CK#

CK

V

REF

 to AC

 region

Nominal

slew rate

V

IH(AC)min

 - V

REF(DC)

ǻ

TR

V

REF(DC)

 - V

IL(AC)max

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

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Figure 39: Nominal Slew Rate for 

t

DH (DQ – Strobe)

V

SS

Hold slew rate
falling signal

Hold slew rate
rising signal

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal 

slew rate

DC to V

REF

region

tDH

tDS

DQS

DQS#

tDH

tDS

CK#

CK

DC to V

REF

region

Nominal 

slew rate

V

REF(DC)

 - V

IL(DC)max

V

IL(DC)min

 - V

REF(DC)

ǻ

TR

ǻ

TF

ǻ

TF

ǻ

TR

Note:

1. The clock and the strobe are drawn on different time scales.

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Figure 40: Tangent Line for 

t

DS (DQ – Strobe)

V

SS

Setup slew rate

rising signal

Setup slew rate

falling signal =

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Tangent

line

V

REF

 to AC

region

Nominal

line

tVAC

tVAC

tDH

tDS

DQS

DQS#

tDH

tDS

CK#

CK

V

REF

 to AC

region

Tangent

line

Nominal

line

Tangent line (V

REF(DC)

 - V

IL(AC)max

)

Tangent line (V

IH(AC)min

 - V

REF(DC)

)

ǻ

TR

ǻ

TR

ǻ

TF

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

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Figure 41: Tangent Line for 

t

DH (DQ – Strobe)

V

SS

Hold slew rate

falling signal

ǻ

TF

ǻ

TR

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Tangent

line

DC to V

REF

region

Hold slew rate

rising signal

=

DQS

DQS#

CK#

CK

DC to V

REF

region

Tangent

line

Nominal

line

Nominal

line

Tangent line (V

IH(DC)min

 - V

REF(DC)

)

ǻ

TF

Tangent line (V

REF(DC)

 - V

IL(DC)max

)

ǻ

TR

tDS

tDH

tDS

tDH

Note:

1. The clock and the strobe are drawn on different time scales.

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Commands – Truth Tables

Table 70: Truth Table – Command

Notes 1–5 apply to the entire table

Function

Symbol

CKE

CS# RAS# CAS# WE#

BA

[2:0]

A

n

A12

A10

A[11,

9:0]

Notes

Prev.

Cycle

Next

Cycle

MODE REGISTER SET

MRS

H

H

L

L

L

L

BA

OP code

 

REFRESH

REF

H

H

L

L

L

H

V

V

V

V

V

 

Self refresh entry

SRE

H

L

L

L

L

H

V

V

V

V

V

6

Self refresh exit

SRX

L

H

H

V

V

V

V

V

V

V

V

6, 7

L

H

H

H

Single-bank PRECHARGE

PRE

H

H

L

L

H

L

BA

V

V

L

V

 

PRECHARGE all banks

PREA

H

H

L

L

H

L

V

V

H

V

 

Bank ACTIVATE

ACT

H

H

L

L

H

H

BA

Row address (RA)

 

WRITE

BL8MRS,
BC4MRS

WR

H

H

L

H

L

L

BA

RFU

V

L

CA

8

BC4OTF

WRS4

H

H

L

H

L

L

BA

RFU

L

L

CA

8

BL8OTF

WRS8

H

H

L

H

L

L

BA

RFU

H

L

CA

8

WRITE
with auto
precharge

BL8MRS,
BC4MRS

WRAP

H

H

L

H

L

L

BA

RFU

V

H

CA

8

BC4OTF

WRAPS4

H

H

L

H

L

L

BA

RFU

L

H

CA

8

BL8OTF

WRAPS8

H

H

L

H

L

L

BA

RFU

H

H

CA

8

READ

BL8MRS,
BC4MRS

RD

H

H

L

H

L

H

BA

RFU

V

L

CA

8

BC4OTF

RDS4

H

H

L

H

L

H

BA

RFU

L

L

CA

8

BL8OTF

RDS8

H

H

L

H

L

H

BA

RFU

H

L

CA

8

READ
with auto
precharge

BL8MRS,
BC4MRS

RDAP

H

H

L

H

L

H

BA

RFU

V

H

CA

8

BC4OTF

RDAPS4

H

H

L

H

L

H

BA

RFU

L

H

CA

8

BL8OTF

RDAPS8

H

H

L

H

L

H

BA

RFU

H

H

CA

8

NO OPERATION

NOP

H

H

L

H

H

H

V

V

V

V

V

9

Device DESELECTED

DES

H

H

H

X

X

X

X

X

X

X

X

10

Power-down entry

PDE

H

L

L

H

H

H

V

V

V

V

V

6

H

V

V

V

Power-down exit

PDX

L

H

L

H

H

H

V

V

V

V

V

6, 11

H

V

V

V

ZQ CALIBRATION LONG

ZQCL

H

H

L

H

H

L

X

X

X

H

X

12

ZQ CALIBRATION SHORT

ZQCS

H

H

L

H

H

L

X

X

X

L

X

 

Notes:

1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising

edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-
dependent.

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2. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be

held HIGH during any normal operation.

3. The state of ODT does not affect the states described in this table.
4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of

four mode registers.

5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 71 (page 120) for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC

are defined in MR0.

9. The purpose of the NOP command is to prevent the DRAM from registering any unwan-

ted commands. A NOP will not terminate an operation that is executing.

10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initializa-

tion) or ZQoper (ZQCL command after initialization).

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Table 71: Truth Table – CKE

Notes 1–2 apply to the entire table; see Table 70 (page 118) for additional command details

Current State

3

CKE

Command

5

(RAS#, CAS#, WE#, CS#)

Action

5

Notes

Previous Cycle

4

(

n

 - 1)

Present Cycle

4

(

n

)

Power-down

L

L

“Don’t Care”

Maintain power-down

 

L

H

DES or NOP

Power-down exit

 

Self refresh

L

L

“Don’t Care”

Maintain self refresh

 

L

H

DES or NOP

Self refresh exit

 

Bank(s) active

H

L

DES or NOP

Active power-down entry

 

Reading

H

L

DES or NOP

Power-down entry

 

Writing

H

L

DES or NOP

Power-down entry

 

Precharging

H

L

DES or NOP

Power-down entry

 

Refreshing

H

L

DES or NOP

Precharge power-down entry

 

All banks idle

H

L

DES or NOP

Precharge power-down entry

6

H

L

REFRESH

Self refresh

Notes:

1. All states and sequences not shown are illegal or reserved unless explicitly described

elsewhere in this document.

2.

t

CKE (MIN) means CKE must be registered at multiple consecutive positive clock edges.

CKE must remain at the valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of 

t

IS + 

t

CKE (MIN) + 

t

IH.

3. Current state = The state of the DRAM immediately prior to clock edge 

n

.

4. CKE (

n

) is the logic state of CKE at clock edge 

n

; CKE (

n

 - 1) was the state of CKE at the

previous clock edge.

5. COMMAND is the command registered at the clock edge (must be a legal command as

defined in Table 70 (page 118)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.

6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all tim-

ings from previous operations are satisfied. All self refresh exit and power-down exit pa-
rameters are also satisfied.

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Commands

DESELECT

The DESELT (DES) command (CS# HIGH) prevents new commands from being execu-
ted by the DRAM. Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affec-
ted.

ZQ CALIBRATION LONG

The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibra-
tion during a power-up initialization and reset sequence (see Figure 50 (page 137)).
This command may be issued at any time by the controller, depending on the system
environment. The ZQCL command triggers the calibration engine inside the DRAM. Af-
ter calibration is achieved, the calibrated values are transferred from the calibration en-
gine to the DRAM I/O, which are reflected as updated R

ON

 and ODT values.

The DRAM is allowed a timing window defined by either 

t

ZQinit or 

t

ZQoper to perform

a full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter 

t

ZQinit must be satisfied. When initialization is com-

plete, subsequent ZQCL commands require the timing parameter 

t

ZQoper to be satis-

fied.

ZQ CALIBRATION SHORT

The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibra-
tions to account for small voltage and temperature variations. A shorter timing window
is provided to perform the reduced calibration and transfer of values as defined by tim-
ing parameter 

t

ZQCS. A ZQCS command can effectively correct a minimum of 0.5% R

ON

and R

TT

 impedance error within 64 clock cycles, assuming the maximum sensitivities

specified in DDR3L 34 Ohm Output Driver Sensitivity (page 69).

ACTIVATE

The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA[2:0] inputs selects the bank, and the address
provided on inputs A[

n

:0] selects the row. This row remains open (or active) for accesses

until a PRECHARGE command is issued to that bank.

A PRECHARGE command must be issued before opening a different row in the same
bank.

READ

The READ command is used to initiate a burst read access to an active row. The address
provided on inputs A[2:0] selects the starting column address, depending on the burst
length and burst type selected (see Burst Order table for additional information). The
value on input A10 determines whether auto precharge is used. If auto precharge is se-
lected, the row being accessed will be precharged at the end of the READ burst. If auto

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precharge is not selected, the row will remain open for subsequent accesses. The value
on input A12 (if enabled in the mode register) when the READ command is issued de-
termines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted.

Table 72: READ Command Summary

Function

Symbol

CKE

CS# RAS# CAS# WE#

BA

[2:0]

A

n

A12

A10

A[11,

9:0]

Prev.

Cycle

Next

Cycle

READ

BL8MRS,

BC4MRS

RD

H

L

H

L

H

BA

RFU

V

L

CA

BC4OTF

RDS4

H

L

H

L

H

BA

RFU

L

L

CA

BL8OTF

RDS8

H

L

H

L

H

BA

RFU

H

L

CA

READ with
auto
precharge

BL8MRS,

BC4MRS

RDAP

H

L

H

L

H

BA

RFU

V

H

CA

BC4OTF

RDAPS4

H

L

H

L

H

BA

RFU

L

H

CA

BL8OTF

RDAPS8

H

L

H

L

H

BA

RFU

H

H

CA

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether auto
precharge is used. The value on input A12 (if enabled in the MR) when the WRITE com-
mand is issued determines whether BC4 (chop) or BL8 is used.

Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.

Table 73: WRITE Command Summary

Function

Symbol

CKE

CS# RAS# CAS# WE#

BA

[2:0]

A

n

A12

A10

A[11,

9:0]

Prev.

Cycle

Next

Cycle

WRITE

BL8MRS,

BC4MRS

WR

H

L

H

L

L

BA

RFU

V

L

CA

BC4OTF

WRS4

H

L

H

L

L

BA

RFU

L

L

CA

BL8OTF

WRS8

H

L

H

L

L

BA

RFU

H

L

CA

WRITE with
auto
precharge

BL8MRS,

BC4MRS

WRAP

H

L

H

L

L

BA

RFU

V

H

CA

BC4OTF

WRAPS4

H

L

H

L

L

BA

RFU

L

H

CA

BL8OTF

WRAPS8

H

L

H

L

L

BA

RFU

H

H

CA

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PRECHARGE

The PRECHARGE command is used to de-activate the open row in a particular bank or
in all banks. The bank(s) are available for a subsequent row access a specified time (

t

RP)

after the PRECHARGE command is issued, except in the case of concurrent auto pre-
charge. A READ or WRITE command to a different bank is allowed during a concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] se-
lect the bank; otherwise, BA[2:0] are treated as “Don’t Care.”

After a bank is precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A PRECHARGE command is treated as
a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging. However, the precharge period is determined by
the last PRECHARGE command issued to the bank.

REFRESH

The REFRESH command is used during normal operation of the DRAM and is analo-
gous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersis-
tent, so it must be issued each time a refresh is required. The addressing is generated by
the internal refresh controller. This makes the address bits a “Don’t Care” during a RE-
FRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs
(maximum when T

C

 

”

 85°C or 3.9μs maximum when T

C

 

”

 95°C). The REFRESH period

begins when the REFRESH command is registered and ends 

t

RFC (MIN) later.

To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight REFRESH com-
mands can be posted to any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is nine times the
maximum average interval refresh rate. Self refresh may be entered with up to eight RE-
FRESH commands being posted. After exiting self refresh (when entered with posted
REFRESH commands), additional posting of REFRESH commands is allowed to the ex-
tent that the maximum number of cumulative posted REFRESH commands (both pre-
and post-self refresh) does not exceed eight REFRESH commands.

At any given time, a maximum of 16 REFRESH commands can be issued within
2 x 

t

REFI.

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Figure 42: Refresh Mode

NOP

1

NOP

1

NOP

1

PRE

RA

Bank(s)

3

BA

REF

NOP

5

REF

2

NOP

5

ACT

NOP

5

One bank

All banks

t

CK

t

CH

t

CL

RA

t

RFC

2

t

RP

t

RFC (MIN)

T0

T1

T2

T3

T4

Ta0

Tb0

Ta1

Tb1

Tb2

Don’t Care

Indicates break
in time scale

Valid

5

Valid

5

Valid

5

CK

CK#

Command

CKE

Address

A10

BA[2:0]

DQ

4

DM

4

DQS, DQS#

4

Notes:

1. NOP commands are shown for ease of illustration; other valid commands may be possi-

ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 187)).

2. The second REFRESH is not required, but two back-to-back REFRESH commands are

shown.

3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one

bank is active (must precharge all active banks).

4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until 

t

RFC

(MIN) is satisfied.

SELF REFRESH

The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without ex-
ternal clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous oper-
ating range (see Input Clock Frequency Change (page 129)). All power supply inputs
(including V

REFCA

 and V

REFDQ

) must be maintained at valid levels upon entry/exit and

during self refresh mode operation. V

REFDQ

 may float or not drive V

DDQ

/2 while in self

refresh mode under the following conditions:

• V

SS

 < V

REFDQ

 < V

DD

 is maintained

• V

REFDQ

 is valid and stable prior to CKE going back HIGH

• The first WRITE operation may not occur earlier than 512 clocks after V

REFDQ

 is valid

• All other self refresh mode exit timing requirements are met

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Commands

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DLL Disable Mode

If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode, with a few notable exceptions:

• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS

WRITE latency (CWL = 6).

• DLL disable mode affects the read data clock-to-data strobe relationship (

t

DQSCK),

but not the read data-to-data strobe relationship (

t

DQSQ, 

t

QH). Special attention is

required to line up the read data with the controller time domain when the DLL is dis-
abled.

• In normal operation (DLL on), 

t

DQSCK starts from the rising clock edge AL + CL

cycles after the READ command. In DLL disable mode, 

t

DQSCK starts AL + CL - 1 cy-

cles after the READ command. Additionally, with the DLL disabled, the value of

t

DQSCK could be larger than 

t

CK.

The ODT feature (including dynamic ODT) is not supported during DLL disable mode.
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming R

TT,nom

 MR1[9, 6, 2] and R

TT(WR)

 MR2[10, 9] to 0 while in the DLL disable

mode.

Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (

t

CK [AVG] MAX

and 

t

CK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross this

clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh:

1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT

is turned off, and R

TT,nom

 and R

TT(WR)

 are High-Z), set MR1[0] to 1 to disable the

DLL.

2. Enter self refresh mode after 

t

MOD has been satisfied.

3. After 

t

CKSRE is satisfied, change the frequency to the desired clock rate.

4. Self refresh may be exited when the clock is stable with the new frequency for

t

CKSRX. After 

t

XS is satisfied, update the mode registers with appropriate values.

5. The DRAM will be ready for its next command in the DLL disable mode after the

greater of 

t

MRD or 

t

MOD has been satisfied. A ZQCL command should be issued

with appropriate timings met.

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Commands

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Figure 43: DLL Enable Mode to DLL Disable Mode

Command

T0

T1

Ta0

Ta1

Tb0

Tc0

Td0

Td1

Te0

Te1

Tf0

CK

CK#

ODT

9

Valid

1

Don’t Care

Valid1

SRE

3

NOP

MRS

2

NOP

SRX

4

MRS

5

Valid

1

NOP

NOP

Indicates break
in time scale

t

MOD

t

CKSRE

t

MOD

t

XS

t

CKESR 

CKE

t

CKSRX

8

7

6

Notes:

1. Any valid command.
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R

TT

 is in the High-Z state.

7. Change frequency.
8. Clock must be stable 

t

CKSRX.

9. Static LOW in the case that R

TT,nom

 or R

TT(WR)

 is enabled; otherwise, static LOW or HIGH.

A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 44 (page 127)).

1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT

is turned off, and R

TT,nom

 and R

TT(WR)

 are High-Z), enter self refresh mode.

2. After 

t

CKSRE is satisfied, change the frequency to the new clock rate.

3. Self refresh may be exited when the clock is stable with the new frequency for

t

CKSRX. After 

t

XS is satisfied, update the mode registers with the appropriate val-

ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait 

t

MRD, then set MR0[8]

to 1 to enable DLL RESET.

4. After another 

t

MRD delay is satisfied, update the remaining mode registers with

the appropriate values.

5. The DRAM will be ready for its next command in the DLL enable mode after the

greater of 

t

MRD or 

t

MOD has been satisfied. However, before applying any com-

mand or function requiring a locked DLL, a delay of 

t

DLLK after DLL RESET must

be satisfied. A ZQCL command should be issued with the appropriate timings
met.

4Gb: x4, x8, x16 DDR3L SDRAM

Commands

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Figure 44: DLL Disable Mode to DLL Enable Mode

CKE

T0

Ta0

Ta1

Tb0

Tc0

Tc1

Td0

Te0

Tf0

Tg0

CK

CK#

ODT

10

SRE

1

NOP

Command

NOP

SRX

2

MRS

3

MRS

4

MRS

5

Valid

6

Valid

Don’t Care

Indicates break
in time scale

t

CKSRE

t

CKSRX

9

8

7

t

XS

t

MRD

t

MRD

t

CKESR 

ODTLoff + 1 × 

t

CK

Th0

t

DLLK

Notes:

1. Enter SELF REFRESH.
2. Exit SELF REFRESH.
3. Wait 

t

XS, then set MR1[0] to 0 to enable DLL.

4. Wait 

t

MRD, then set MR0[8] to 1 to begin DLL RESET.

5. Wait 

t

MRD, update registers (CL, CWL, and write recovery may be necessary).

6. Wait 

t

MOD, any valid command.

7. Starting with the idle state.
8. Change frequency.
9. Clock must be stable at least 

t

CKSRX.

10. Static LOW in the case that R

TT,nom

 or R

TT(WR)

 is enabled; otherwise, static LOW or HIGH.

The clock frequency range for the DLL disable mode is specified by the parameter 

t

CK

(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.

DLL disable mode will affect the read data clock to data strobe relationship (

t

DQSCK)

but not the data strobe to data relationship (

t

DQSQ, 

t

QH). Special attention is needed to

line up read data to the controller time domain.

Compared to the DLL on mode where 

t

DQSCK starts from the rising clock edge AL + CL

cycles after the READ command, the DLL disable mode 

t

DQSCK starts AL + CL - 1 cycles

after the READ command.

WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.

4Gb: x4, x8, x16 DDR3L SDRAM

Commands

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Figure 45: DLL Disable 

t

DQSCK

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

Don’t Care

Transitioning Data

Valid

NOP

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

Address

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

DQ BL8 DLL on

DQS, DQS# DLL on

DQ BL8 DLL disable

DQS, DQS# DLL off

DQ BL8 DLL disable

DQS, DQS# DLL off

RL = AL + CL = 6 (CL = 6, AL = 0)

CL = 6 

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

t

DQSCK (DLL_DIS) MIN

t

DQSCK (DLL_DIS) MAX

RL (DLL_DIS) = AL + (CL - 1) = 5 

Table 74: READ Electrical Characteristics, DLL Disable Mode

Parameter

Symbol

Min

Max

Unit

Access window of DQS from CK, CK#

t

DQSCK (DLL_DIS)

1

10

ns

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Commands

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Input Clock Frequency Change

When the DDR3 SDRAM is initialized, the clock must be stable during most normal
states of operation. This means that after the clock frequency has been set to the stable
state, the clock period is not allowed to deviate, except for what is allowed by the clock
jitter and spread spectrum clocking (SSC) specifications.

The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. It is illegal to
change the clock frequency outside of those two modes. For the self refresh mode con-
dition, when the DDR3 SDRAM has been successfully placed into self refresh mode and

t

CKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the

clock becomes a “Don’t Care,” changing the clock frequency is permissible if the new
clock frequency is stable prior to 

t

CKSRX. When entering and exiting self refresh mode

for the sole purpose of changing the clock frequency, the self refresh entry and exit
specifications must still be met.

The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or R

TT,nom

 and R

TT(WR)

 must be disabled via MR1 and MR2. This ensures

R

TT,nom

 and R

TT(WR)

 are in an off state prior to entering precharge power-down mode,

and CKE must be at a logic LOW. A minimum of 

t

CKSRE must occur after CKE goes LOW

before the clock frequency can change. The DDR3 SDRAM input clock frequency is al-
lowed to change only within the minimum and maximum operating frequency speci-
fied for the particular speed grade (

t

CK [AVG] MIN to 

t

CK [AVG] MAX). During the input

clock frequency change, CKE must be held at a stable LOW level. When the input clock
frequency is changed, a stable clock must be provided to the DRAM 

t

CKSRX before pre-

charge power-down may be exited. After precharge power-down is exited and 

t

XP has

been satisfied, the DLL must be reset via the MRS. Depending on the new clock fre-
quency, additional MRS commands may need to be issued. During the DLL lock time,
R

TT,nom

 and R

TT(WR)

 must remain in an off state. After the DLL lock time, the DRAM is

ready to operate with a new clock frequency.

4Gb: x4, x8, x16 DDR3L SDRAM

Input Clock Frequency Change

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Figure 46: Change Frequency During Precharge Power-Down

CK

CK#

Command

NOP

NOP

NOP

Address

CKE

DQ

DM

DQS, DQS#

NOP

t

CK

Enter precharge

power-down mode

Exit precharge

power-down mode

T0

T1

Ta0

Tc0

Tb0

T2

Don’t Care

t

CKE

t

XP

MRS

DLL RESET

Valid

Valid

NOP

t

CH

t

IH

t

IS

t

CL

Tc1

Td0

Te1

Td1

t

CKSRE

t

CH

b

t

CL

b

t

CK

b

t

CH

b

t

CL

b

t

CK

b

t

CH

b

t

CL

b

t

CK

b

t

CPDED

ODT

NOP

Te0

Previous clock frequency

New clock frequency

Frequency

change

Indicates break
in time scale

t

IH

t

IS

t

IH

t

IS

t

DLLK

t

AOFPD/

t

AOF

t

CKSRX

High-Z

High-Z

Notes:

1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2.

t

AOFPD and 

t

AOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-

tion (ODT) (page 197)for exact requirements).

3. If the R

TT,nom

 feature was enabled in the mode register prior to entering precharge

power-down mode, the ODT signal must be continuously registered LOW, ensuring R

TT

is in an off state. If the R

TT,nom

 feature was disabled in the mode register prior to enter-

ing precharge power-down mode, R

TT

 will remain in the off state. The ODT signal can

be registered LOW or HIGH in this case.

4Gb: x4, x8, x16 DDR3L SDRAM

Input Clock Frequency Change

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Write Leveling

For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topolo-
gy for the commands, addresses, control signals, and clocks. Write leveling is a scheme
for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK rela-
tionship at the DRAM with a simple feedback feature provided by the DRAM. Write lev-
eling is generally used as part of the initialization process, if required. For normal
DRAM operation, this feature must be disabled. This is the only DRAM operation where
the DQS functions as an input (to capture the incoming clock) and the DQ function as
outputs (to report the state of the clock). Note that nonstandard ODT schemes are re-
quired.

The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established by
this procedure helps ensure 

t

DQSS, 

t

DSS, and 

t

DSH specifications in systems that use

fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this
procedure is shown in Figure 47.

Figure 47: Write Leveling Concept

CK

CK#

Source

Differential DQS

Differential DQS

Differential DQS

DQ

DQ

CK

CK#

Destination

Destination

Push DQS to capture 

0–1 transition

T0

T1

T2

T3

T4

T5

T6

T7

T0

T1

T2

T3

T4

T5

T6

Tn

CK

CK#

T0

T1

T2

T3

T4

T5

T6

Tn

Don’t Care

1

1

0

0

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the
lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS
and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a
x16 enable each byte lane to be leveled independently.

The write leveling mode register interacts with other mode registers to correctly config-
ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-
ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst
length, and so forth need to be selected as well. This interaction is shown in Table 75. It
should also be noted that when the outputs are enabled during write leveling mode, the
DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write
leveling mode, only the DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the ODT ball.

Table 75: Write Leveling Matrix

Note 1 applies to the entire table

MR1[7]

MR1[12]

MR1[2, 6, 9]

DRAM

ODT Ball

DRAM

R

TT,nom

DRAM State

Case Notes

Write

Leveling

Output

Buffers

R

TT,nom

Value

DQS

DQ

Disabled

See normal operations

Write leveling not enabled

0

 

Enabled

(1)

Disabled

(1)

n/a

Low

Off

Off

DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated

1

2



˖



˖



˖



˖

, or

120

˖

High

On

DQS not receiving: terminated by R

TT

Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated

2

Enabled

(0)

n/a

Low

Off

DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated

3

3



˖



˖

, or

120

˖

High

On

DQS receiving: terminated by R

TT

Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated

4

Notes:

1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a

dual-rank module and on the rank not being leveled or on any rank of a module not
being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of
a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is
generally used when DRAM are on the rank that is being leveled.

2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,

and all R

TT,nom

 values are allowed. This simulates a normal standby state to DQS.

3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and

only some R

TT,nom

 values are allowed. This simulates a normal write state to DQS.

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Write Leveling Procedure

A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, as-
suming the other programable features (MR0, MR1, MR2, and MR3) are first set and the
DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a
High-Z state to an undefined driving state, so the DQ bus should not be driven. During
write leveling mode, only the NOP or DES commands are allowed. The memory con-
troller should attempt to level only one rank at a time; thus, the outputs of other ranks
should be disabled by setting MR1[12] to 1 in the other ranks. The memory controller
may assert ODT after a 

t

MOD delay, as the DRAM will be ready to process the ODT tran-

sition. ODT should be turned on prior to DQS being driven LOW by at least ODTLon
delay (WL - 2 

t

CK), provided it does not violate the aforementioned 

t

MOD delay require-

ment.

The memory controller may drive DQS LOW and DQS# HIGH after 

t

WLDQSEN has

been satisfied. The controller may begin to toggle DQS after 

t

WLMRD (one DQS toggle

is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a
HIGH state to a LOW state, then both transition back to their original states). At a mini-
mum, ODTLon and 

t

AON must be satisfied at least one clock prior to DQS toggling.

After 

t

WLMRD and a DQS LOW preamble (

t

WPRE) have been satisfied, the memory

controller may provide either a single DQS toggle or multiple DQS toggles to sample CK
for a given DQS-to-CK skew. Each DQS toggle must not violate 

t

DQSL (MIN) and 

t

DQSH

(MIN) specifications. 

t

DQSL (MAX) and 

t

DQSH (MAX) specifications are not applicable

during write leveling mode. The DQS must be able to distinguish the CK’s rising edge
within 

t

WLS and 

t

WLH. The prime DQ will output the CK’s status asynchronously from

the associated DQS rising edge CK capture within 

t

WLO. The remaining DQ that always

drive LOW when DQS is toggling must be LOW within 

t

WLOE after the first 

t

WLO is sat-

isfied (the prime DQ going LOW). As previously noted, DQS is an input and not an out-
put during this process. Figure 48 (page 134) depicts the basic timing parameters for
the overall write leveling procedure.

The memory controller will most likely sample each applicable prime DQ state and de-
termine whether to increment or decrement its DQS delay setting. After the memory
controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memo-
ry controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting is locked, leveling for the rank will have been achieved, and the write leveling
mode for the rank should be disabled or reprogrammed (if write leveling of another
rank follows).

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Figure 48: Write Leveling Sequence

CK

CK#

Command

T1

T2

Early remaining DQ

Late remaining DQ

t

WLOE

NOP

2

NOP

MRS

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

WLS

t

WLH

Don’t Care

Undefined Driving Mode

Indicates break
in time scale

Prime DQ

5

Differential DQS

4

ODT

t

MOD

t

DQSL

3

t

DQSL

3

t

DQSH

3

t

DQSH

3

t

WLO

t

WLMRD

t

WLDQSEN

t

WLO

t

WLO

t

WLO

Notes:

1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements 

t

DQSH (MIN) and 

t

DQSL

(MIN) as defined for regular writes. The maximum pulse width is system-dependent.

4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are

the zero crossings. The solid line represents DQS; the dotted line represents DQS#.

5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ

are driven LOW and remain in this state throughout the leveling procedure.

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Write Leveling Mode Exit Procedure

After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 49 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
driving the DQS signals after 

t

WLO (MAX) delay plus enough delay to enable the memo-

ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until 

t

MOD

after the MRS command (at Te1).

The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies 

t

IS, ODT must be kept LOW (at

~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After 

t

MOD is satisfied (at Te1), any valid com-

mand may be registered by the DRAM. Some MRS commands may be issued after 

t

MRD

(at Td1).

Figure 49: Write Leveling Exit Procedure

NOP

CK

T0

T1

T2

Ta0

Tb0

Tc0

Tc1

Tc2

Td0

Td1

Te0

Te1

CK#

Command

ODT

R

TT(DQ)

NOP

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Address

MR1

Valid

Valid

Valid

Valid

Don’t Care

Transitioning

R

TT

 DQS, R

TT

 DQS#

R

TT,nom

Undefined Driving Mode

t

AOF (MAX)

t

MRD

Indicates break
in time scale

DQS, DQS#

CK = 1

DQ

t

IS

t

AOF (MIN)

t

MOD

t

WLO + 

t

WLOE

ODTLoff

Note:

1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing

CK HIGH just after the T0 state.

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Initialization

The following sequence is required for power-up and initialization, as shown in Figure
50 (page 137):

1. Apply power. RESET# is recommended to be below 0.2 × V

DDQ

 during power ramp

to ensure the outputs remain disabled (High-Z) and ODT off (R

TT

 is also High-Z).

All other inputs, including ODT, may be undefined.

During power-up, either of the following conditions may exist and must be met:

• Condition A:

– V

DD

 and V

DDQ

 are driven from a single-power converter output and are

ramped with a maximum delta voltage between them of 

ǻ

”

 300mV. Slope re-

versal of any power supply signal is allowed. The voltage levels on all balls oth-
er than V

DD

, V

DDQ

, V

SS

, V

SSQ

 must be less than or equal to V

DDQ

 and V

DD

 on

one side, and must be greater than or equal to V

SSQ

 and V

SS

 on the other side.

– Both V

DD

 and V

DDQ

 power supplies ramp to V

DD,min

 and V

DDQ,min

 within

t

V

DDPR

 = 200ms.

– V

REFDQ

 tracks V

DD

 × 0.5, V

REFCA

 tracks V

DD

 × 0.5.

– V

TT

 is limited to 0.95V when the power ramp is complete and is not applied

directly to the device; however, 

t

VTD should be greater than or equal to 0 to

avoid device latchup.

• Condition B:

– V

DD

 may be applied before or at the same time as V

DDQ

.

– V

DDQ

 may be applied before or at the same time as V

TT

, V

REFDQ

, and V

REFCA

.

– No slope reversals are allowed in the power supply ramp for this condition.

2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled

(High-Z). After the power is stable, RESET# must be LOW for at least 200μs to be-
gin the initialization process. ODT will remain in the High-Z state while RESET# is
LOW and until CKE is registered HIGH.

3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500μs (minus one clock) with CKE LOW.
5. After the CKE LOW time, CKE may be brought HIGH (synchronously) and only

NOP or DES commands may be issued. The clock must be present and valid for at
least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least

t

IS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be

continuously registered HIGH until the full initialization process is complete.

6. After CKE is registered HIGH and after 

t

XPR has been satisfied, MRS commands

may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applica-
ble settings (provide LOW to BA2 and BA0 and HIGH to BA1).

7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling

the DLL and configuring ODT.

9. Issue an MRS command to MR0 with the applicable settings, including a DLL RE-

SET command. 

t

DLLK (512) cycles of clock input are required to lock the DLL.

10. Issue a ZQCL command to calibrate R

TT

 and R

ON

 values for the process voltage

temperature (PVT). Prior to normal operation, 

t

ZQinit must be satisfied.

11. When 

t

DLLK and 

t

ZQinit have been satisfied, the DDR3 SDRAM will be ready for

normal operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Initialization

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Figure 50: Initialization Sequence

CKE

R

TT

BA[2:0]

All voltage
supplies valid
and stable

T = 200μs (MIN)

DM

DQS

Address

A10

CK

CK#

t

CL

Command

NOP

T0

Ta0

Don’t Care

t

CL

t

IS

t

CK

ODT

DQ

Tb0

t

DLLK

MR1 with

DLL enable

MR0 with

DLL reset

t

MRD

t

MOD

MRS

MRS

BA0 = H
BA1 = L
BA2 = L

BA0 = L
BA1 = L
BA2 = L

Code Code 

Code Code 

Valid

Valid

Valid

Valid

Normal

operation

MR2

MR3

t

MRD

t

MRD

MRS

MRS

BA0 = L
BA1 = H
BA2 = L

BA0 = H
BA1 = H
BA2 = L

Code Code 

Code Code 

Tc0

Td0

V

TT

V

REF

V

DDQ

V

DD

RESET#

T = 500μs (MIN)

t

CKSRX

Stable and
valid clock

Valid

Power-up
ramp

T (MAX) = 200ms

DRAM ready for 
external commands

T1

t

ZQinit

ZQ calibration

A10 = H

ZQCL

t

IS

See power-up

conditions 

in the 

initialization

sequence text, 

set up 1 

t

XPR

Valid

t

IOZ = 20ns

Indicates break
in time scale

T (MIN) = 10ns

t

VTD

4Gb: x4, x8, x16 DDR3L SDRAM

Initialization

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Voltage Initialization/Change

If the SDRAM is powered up and initialized for the 1.35V operating voltage range, volt-
age can be increased to the 1.5V operating range provided the following conditions are
met (See Figure 51 (page 139)):

• Just prior to increasing the 1.35V operating voltages, no further commands are issued,

other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.

• The 1.5V operating voltages are stable prior to issuing new commands, other than

NOPs or COMMAND INHIBITs.

• The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to

any READ command.

• The ZQ calibration is performed. 

t

ZQinit must be satisfied after the 1.5V operating

voltages are stable and prior to any READ command.

If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage
can be reduced to the 1.35V operation range provided the following conditions are met
(See Figure 51 (page 139)) :

• Just prior to reducing the 1.5V operating voltages, no further commands are issued,

other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.

• The 1.35V operating voltages are stable prior to issuing new commands, other than

NOPs or COMMAND INHIBITs.

• The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to

any READ command.

• The ZQ calibration is performed. 

t

ZQinit must be satisfied after the 1.35V operating

voltages are stable and prior to any READ command.

4Gb: x4, x8, x16 DDR3L SDRAM

Voltage Initialization/Change

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V

DD

 Voltage Switching

After the DDR3L DRAM is powered up and initialized, the power supply can be altered
between the DDR3L and DDR3 levels, provided the sequence in Figure 51 is main-
tained.

Figure 51: V

DD

 Voltage Switching

(

)

(

)

(

)

(

)

CKE

R

TT

BA

(

)

(

)

(

)

(

)

CK, CK#

Command

Note 1 

Note 1 

(

)

(

)

(

)

(

)

Td

Tc

Tg

Don’t Care

(

)

(

)

(

)

(

)

(

)

(

)

t

IS

ODT

(

)

(

)

(

)

(

)

Th

t

MRD

t

MOD

(

)

(

)

(

)

(

)

MRS

MRS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

MRD

t

MRD

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

MRS

MR0

MR1

MR3

MRS

MR2

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Ti

Tj

Tk

(

)

(

)

(

)

(

)

RESET#

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

T = 500μs

(

)

(

)

(

)

(

)

(

)

(

)

Te

Ta

Tb

Tf

(

)

(

)

(

)

(

)

ZQCL

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

IS

Static LOW in case R

TT,nom

 is enabled at time Tg, otherwise static HIGH or LOW 

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

IS

t

IS

t

XPR

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Time break

T

MIN

 = 10ns

T

MIN

 = 10ns

T

MIN

 = 10ns

T

MIN

 = 

200μs 

t

CKSRX

V

DD

, V

DDQ

 (DDR3)

(

)

(

)

(

)

(

)

t

DLLK

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

ZQinit

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

V

DD

, V

DDQ

 (DDR3L)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Valid

Valid

Valid

Valid

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Note:

1. From time point Td until Tk, NOP or DES commands must be applied between MRS and

ZQCL commands.

4Gb: x4, x8, x16 DDR3L SDRAM

Voltage Initialization/Change

09005aef85af8fa8
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Mode Registers

Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.

Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode register’s variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed cor-
rectly.

The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (

t

RP is satisfied and no data bursts are in progress). After an MRS com-

mand has been issued, two parameters must be satisfied: 

t

MRD and 

t

MOD. The control-

ler must wait 

t

MRD before initiating any subsequent MRS commands.

Figure 52: MRS to MRS Command Timing (

t

MRD)

Valid

Valid

MRS

1

MRS

2

NOP

NOP

NOP

NOP

T0

T1

T2

Ta0

Ta1

Ta2

CK#

CK

Command

Address

CKE

3

Don’t Care

Indicates break
in time scale

t

MRD

Notes:

1. Prior to issuing the MRS command, all banks must be idle and precharged, 

t

RP (MIN)

must be satisfied, and no data bursts can be in progress.

2.

t

MRD specifies the MRS to MRS command minimum cycle time.

3. CKE must be registered HIGH from the MRS command until 

t

MRSPDEN (MIN) (see Pow-

er-Down Mode (page 187)).

4. For a CAS latency change, 

t

XPDLL timing must be met before any non-MRS command.

The controller must also wait 

t

MOD before initiating any non-MRS commands (exclud-

ing NOP and DES). The DRAM requires 

t

MOD in order to update the requested features,

with the exception of DLL RESET, which requires additional time. Until 

t

MOD has been

satisfied, the updated features are to be assumed unavailable.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Registers

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Figure 53: MRS to nonMRS Command Timing (

t

MOD)

Valid

Valid

MRS

non

MRS

NOP

NOP

NOP

NOP

T0

T1

T2

Ta0

Ta1

Ta2

CK#

CK

Command

Address

CKE

Valid

Old 

setting

New 

setting

Indicates break
in time scale

t

MOD

Updating setting

Don’t Care

Notes:

1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, 

t

RP

must be satisfied, and no data bursts can be in progress).

2. Prior to Ta2 when 

t

MOD (MIN) is being satisfied, no commands (except NOP/DES) may be

issued.

3. If R

TT

 was previously enabled, ODT must be registered LOW at T0 so that ODTL is satis-

fied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until

t

MODmin is satisfied at Ta2.

4. CKE must be registered HIGH from the MRS command until 

t

MRSPDEN (MIN), at which

time power-down may occur (see Power-Down Mode (page 187)).

Mode Register 0 (MR0)

The base register, mode register 0 (MR0), is used to define various DDR3 SDRAM modes
of operation. These definitions include the selection of a burst length, burst type, CAS
latency, operating mode, DLL RESET, write recovery, and precharge power-down mode
(see Figure 54 (page 142)).

Burst Length

Burst length is defined by MR0[1:0]. Read and write accesses to the DDR3 SDRAM are
burst-oriented, with the burst length being programmable to 4 (chop) mode, 8 (fixed)
mode, or selectable using A12 during a READ/WRITE command (on-the-fly). The burst
length determines the maximum number of column locations that can be accessed for
a given READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE
command, if A12 = 0, then BC4 mode is selected. If A12 = 1, then BL8 mode is selected.
Specific timing diagrams, and turnaround between READ/WRITE, are shown in the
READ/WRITE sections of this document.

When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[

i

:2] when the burst length is set to 4 and by A[

i

:3] when the burst

length is set to 8, where A

i

 is the most significant column address bit for a given config-

uration. The remaining (least significant) address bit(s) is (are) used to select the start-

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.

Figure 54: Mode Register 0 (MR0) Definitions

BL

CAS# latency

CL

BT

PD

A9

A7 A6 A5 A4 A3

A8

A2 A1 A0

Mode register 0 (MR0)

Address bus

9

7

6

5

4

3

8

2

1

0

A10

A12 A11

BA0

BA1

10

11

12

15–13

M3

 

0

1

READ Burst Type

 

Sequential (nibble)

Interleaved

CAS Latency

Reserved

5

6

7

8

9

10

11

12

13

14

M2

0

0

0

0

0

0

0

0

1

1

1

M4

0

1

0

1

0

1

0

1

0

1

0

M5

0

0

1

1

0

0

1

1

0

0

1

M6

0

0

0

0

1

1

1

1

0

0

0

17

DLL

Write Recovery

16

5

6

7

8

10

12

14

WR

0

0

M12

1

Precharge PD

DLL off (slow exit)

DLL on (fast exit)

BA2

18

0

1

Burst Length

Fixed BL8

4 or 8 (on-the-fly via A12)

Fixed BC4 (chop)

Reserved

M0

0

1

0

1

M1

0

0

1

1

M9

0

1

0

1

0

1

0

1

M10

0

0

1

1

0

0

1

1

M11

0

0

0

0

1

1

1

1

M14

 

0

1

0

1

M15

0

0

1

1

Mode Register 

Mode register 0 (MR0)

Mode register 1 (MR1)

Mode register 2 (MR2)

Mode register 3 (MR3)

A[15:13]

16

0

1

0

1

M8

0

1

DLL Reset

No

Yes

Note:

1. MR0[18, 15:13, 7] are reserved for future use and must be programmed to 0.

Burst Type

Accesses within a given burst can be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR0[3] (see Figure 54 (page 142)). The order-
ing of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are re-
stricted to nibble (BC4) or word (BL8) boundaries.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Table 76: Burst Order

Burst

Length

READ/
WRITE

Starting

Column Address

(A[2, 1, 0])

Burst Type = Sequential

(Decimal)

Burst Type = Interleaved

(Decimal)

Notes

4 (chop)

READ

0 0 0

0, 1, 2, 3, Z, Z, Z, Z

0, 1, 2, 3, Z, Z, Z, Z

1, 2

0 0 1

1, 2, 3, 0, Z, Z, Z, Z

1, 0, 3, 2, Z, Z, Z, Z

1, 2

0 1 0

2, 3, 0, 1, Z, Z, Z, Z

2, 3, 0, 1, Z, Z, Z, Z

1, 2

0 1 1

3, 0, 1, 2, Z, Z, Z, Z

3, 2, 1, 0, Z, Z, Z, Z

1, 2

1 0 0

4, 5, 6, 7, Z, Z, Z, Z

4, 5, 6, 7, Z, Z, Z, Z

1, 2

1 0 1

5, 6, 7, 4, Z, Z, Z, Z

5, 4, 7, 6, Z, Z, Z, Z

1, 2

1 1 0

6, 7, 4, 5, Z, Z, Z, Z

6, 7, 4, 5, Z, Z, Z, Z

1, 2

1 1 1

7, 4, 5, 6, Z, Z, Z, Z

7, 6, 5, 4, Z, Z, Z, Z

1, 2

WRITE

0 V V

0, 1, 2, 3, X, X, X, X

0, 1, 2, 3, X, X, X, X

1, 3, 4

1 V V

4, 5, 6, 7, X, X, X, X

4, 5, 6, 7, X, X, X, X

1, 3, 4

8 (fixed)

READ

0 0 0

0, 1, 2, 3, 4, 5, 6, 7

0, 1, 2, 3, 4, 5, 6, 7

1

0 0 1

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

1

0 1 0

2, 3, 0, 1, 6, 7, 4, 5

2, 3, 0, 1, 6, 7, 4, 5

1

0 1 1

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

1

1 0 0

4, 5, 6, 7, 0, 1, 2, 3

4, 5, 6, 7, 0, 1, 2, 3

1

1 0 1

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

1

1 1 0

6, 7, 4, 5, 2, 3, 0, 1

6, 7, 4, 5, 2, 3, 0, 1

1

1 1 1

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

1

WRITE

V V V

0, 1, 2, 3, 4, 5, 6, 7

0, 1, 2, 3, 4, 5, 6, 7

1, 3

Notes:

1. Internal READ and WRITE operations start at the same point in time for BC4 as they do

for BL8.

2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input

pins.

4. X = “Don’t Care.”

DLL RESET

DLL RESET is defined by MR0[8] (see Figure 54 (page 142)). Programming MR0[8] to 1
activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value
of 0 after the DLL RESET function has been initiated.

Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
stable for 512 (

t

DLLK) clock cycles before a READ command can be issued. This is to

allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization can result in invalid output timing specifications, such as

t

DQSCK timings.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Write Recovery

WRITE recovery time is defined by MR0[11:9] (see Figure 54 (page 142)). Write recovery
values of 5, 6, 7, 8, 10, or 12 can be used by programming MR0[11:9]. The user is re-
quired to program the correct value of write recovery, which is calculated by dividing

t

WR (ns) by 

t

CK (ns) and rounding up a noninteger value to the next integer:

WR (cycles) = roundup (

t

WR (ns)/

t

CK (ns)).

Precharge Power-Down (Precharge PD)

The precharge power-down (precharge PD) bit applies only when precharge power-
down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge
power-down, providing a lower standby current mode; however, 

t

XPDLL must be satis-

fied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge
power-down mode to enable a faster exit of precharge power-down mode; however, 

t

XP

must be satisfied when exiting (see Power-Down Mode (page 187)).

CAS Latency (CL)

CAS latency (CL) is defined by MR0[6:4], as shown in Figure 54 (page 142). CAS latency
is the delay, in clock cycles, between the internal READ command and the availability of
the first bit of output data. CL can be set to 5 through 14. DDR3 SDRAM do not support
half-clock latencies.

Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge 

n

, and the CAS latency is 

m

 clocks, the data will be available nomi-

nally coincident with clock edge 

n

 + 

m.

 See Speed Bin Tables for the CLs supported at

various operating frequencies.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Figure 55: READ Latency

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ

DQS, DQS#

DQS, DQS#

T0

T1

T2

T3

T4

T5

T6

T7

T8

Don’t Care

CK

CK#

Command

DQ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

DI

 n + 3

DI

 n + 1

DI

 n + 2

DI

 n + 4

DI

n

DI

n

NOP

NOP

AL = 0, CL = 8

AL = 0, CL = 6

Transitioning Data

Notes:

1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal 

t

DQSCK and nominal 

t

DSDQ.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Mode Register 1 (MR1)

The mode register 1 (MR1) controls additional functions and features not available in
the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
only), DLL ENABLE/DLL DISABLE, R

TT,nom

 value (ODT), WRITE LEVELING, POSTED

CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are control-
led via the bits shown in Figure 56 (page 146). The MR1 register is programmed via the
MRS command and retains the stored information until it is reprogrammed, until RE-
SET# goes LOW, or until the device loses power. Reprogramming the MR1 register will
not alter the contents of the memory array, provided it is performed correctly.

The MR1 register must be loaded when all banks are idle and no bursts are in progress.
The controller must satisfy the specified timing parameters 

t

MRD and 

t

MOD before ini-

tiating a subsequent operation.

Figure 56: Mode Register 1 (MR1) Definition

AL

R

TT

Q Off

A9

A7 A6 A5 A4 A3

A8

A2

A1 A0

Mode register 1 (MR1)

Address bus

9

7

6

5

4

3

8

2

1

0

A10

A12 A11

BA0

BA1

10

11

12

13

M0

0

1

DLL Enable

Enable (normal)

Disable

M5

0

0

1

1

Output Drive St rength

RZQ/6 (40

ȍ

 [NOM])

RZQ/7 (34

ȍ

 [NOM])

Reserved

Reserved

14

WL

01

01

1

0

ODS DLL

R

TT

TDQS

M12

0

1

Q Off

Enabled

Disabled

BA2

15

01

M7

0

1

Write Levelization

Disable (normal)

Enable

Additive Latency (AL)

Disabled (AL = 0)

AL = CL - 1

AL = CL - 2

Reserved

M3

0

1

0

1

M4

0

0

1

1

R

TT

ODS

M1

0

1

0

1

A13

A14

A15

16

17

18

01

M11

0

1

TDQS 

Disabled

Enabled

01

01

R

TT,nom

 (ODT) 2

Non- Writes

R

TT,nom 

disabled

RZQ/4 (60

ȍ

 [NOM])

RZQ/2 (120

ȍ

 [NOM])

RZQ/6 (40

ȍ

 [NOM])

RZQ/12 (20

ȍ

 [NOM])

RZQ/8 (30

ȍ

 [NOM])

Reserved

Reserved

R

TT,nom 

(ODT) 3

Writes

R

TT,nom 

disabled

RZQ/4 (60

ȍ

 [NOM])

RZQ/2 (120

ȍ

 [NOM])

RZQ/6 (40

ȍ

 [NOM])

n/a

n/a

Reserved

Reserved

M2

0

1

0

1

0

1

0

1

M6

0

0

1

1

0

0

1

1

M9

0

0

0

0

1

1

1

1

Mode Register 

Mode register set 0 (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

M16

 

0

1

0

1

M17 

0

0

1

1

Notes:

1. MR1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.
2. During write leveling, if MR1[7] and MR1[12] are 1, then all R

TT,nom

 values are available

for use.

3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only R

TT,nom

 write values

are available for use.

DLL Enable/DLL Disable

The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE
command, as shown in Figure 56 (page 146). The DLL must be enabled for normal oper-
ation. DLL enable is required during power-up initialization and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debugging or evalua-
tion. Enabling the DLL should always be followed by resetting the DLL using the appro-
priate LOAD MODE command.

If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-
bled when entering SELF REFRESH operation and is automatically re-enabled and reset
upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self re-

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 1 (MR1)

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fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until
it is re-enabled and reset.

The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:

• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks

When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see DLL Disable Mode (page 125)). Disabling
the DLL also implies the need to change the clock frequency (see Input Clock Frequen-
cy Change (page 129)).

Output Drive Strength

The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/7 (34

ȍ

 [NOM]) is the primary output

driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-
pedance, an external precision resistor (RZQ) is connected between the ZQ ball and
V

SSQ

. The value of the resistor must be 240

ȍ

 ±1%.

The output impedance is set during initialization. Additional impedance calibration up-
dates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.

To meet the 34

ȍ

 specification, the output drive strength must be set to 34

ȍ

 during initi-

alization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset proce-
dure.

OUTPUT ENABLE/DISABLE

The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 (page
146). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the
normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during I

DD

 characterization of the READ current and during 

t

DQSS margining (write

leveling) only.

TDQS Enable

Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (R

TT

) and may be useful in some system configurations.

TDQS is not supported in x4 or x16 configurations. When enabled via the mode register
(MR1[11]), the R

TT

 that is applied to DQS and DQS# is also applied to TDQS and TDQS#.

In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-
tion resistance R

TT

 only. The OUTPUT DATA STROBE function of RDQS is not provided

by TDQS; thus, R

ON

 does not apply to TDQS and TDQS#. The TDQS and DM functions

share the same ball. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is pro-
vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 1 (MR1)

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SDRAM configuration only and must be disabled via the mode register for the x4 and
x16 configurations.

On-Die Termination

ODT resistance R

TT,nom

 is defined by MR1[9, 6, 2] (see Figure 56 (page 146)). The R

TT

termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple R

TT

 termination values based on RZQ/

n

 where 

n

 can be 2, 4, 6, 8, or

12 and RZQ is 240

ȍ

.

Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. R

TT,nom

 termination is allowed any time after the DRAM is ini-

tialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT (R

TT(WR)

) enabled temporarily re-

places R

TT,nom

 with R

TT(WR)

.

The actual effective termination, R

TT(EFF)

, may be different from the R

TT

 targeted due to

nonlinearity of the termination. For R

TT(EFF)

 values and calculations (see On-Die Termi-

nation (ODT) (page 197)).

The ODT feature is designed to improve signal integrity of the memory channel by ena-
bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devi-
ces. The ODT input control pin is used to determine when R

TT

 is turned on (ODTL on)

and off (ODTL off ), assuming ODT has been enabled via MR1[9, 6, 2].

Timings for ODT are detailed in On-Die Termination (ODT) (page 197).

WRITE LEVELING

The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 56 (page 146).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.

The fly-by topology benefits from a reduced number of stubs and their lengths. Howev-
er, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining

t

DQSS, 

t

DSS, and 

t

DSH specifications without supporting write leveling in systems

which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 131).

POSTED CAS ADDITIVE Latency

POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus
efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL,
as shown in Figure 57 (page 149). MR1[4, 3] enable the user to program the DDR3
SDRAM with AL = 0, CL - 1, or CL - 2.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 1 (MR1)

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Figure 57: READ Latency (AL = 5, CL = 6)

CK

CK#

Command

DQ

DQS, DQS#

ACTIVE n

T0

T1

Don’t Care

NOP

NOP

T6

T12

NOP

READ n

T13

NOP

DO

n + 3

DO

n + 2

DO

n + 1

RL = AL + CL = 11

T14

NOP

DO

n

t

RCD (MIN)

AL = 5

CL = 6

T11

BC4

Indicates break
in time scale

Transitioning Data

T2

NOP

Mode Register 2 (MR2)

The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AU-
TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(R

TT(WR)

). These functions are controlled via the bits shown in Figure 58. The MR2 is

programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time 

t

MRD and 

t

MOD before initiating a sub-

sequent operation.

Figure 58: Mode Register 2 (MR2) Definition

0

0

0RGH5HJLVWHU

0RGHUHJLVWHUVHW05

0RGHUHJLVWHUVHW05

0RGHUHJLVWHUVHW05

0RGHUHJLVWHUVHW05

$

$ $ $ $ $

$

$ $ $

0RGHUHJLVWHU05

$GGUHVVEXV

$

$ $

%$

%$

&:/

%$

$65

$

$

$

657

5

77:5

0


$XWR6HOI5HIUHVK

2SWLRQDO

'LVDEOHG0DQXDO

(QDEOHG$XWRPDWLF

0


6HOI5HIUHVK7HPSHUDWXUH

1RUPDOƒ&WRƒ&
([WHQGHG •ƒ&WRƒ&

&$6:ULWH/DWHQF\&:/

&.W&.•QV

&.QV!W&.•QV
&.QV!W&.•QV

&.QV!W&.•QV
&.QV!W&.QV

&.QV!

W

&.•QV

5HVHUYHG
5HVHUYHG

0








0








0








0




0




'\QDPLF2'7

5

77:5

5

77:5

GLVDEOHG

5=4:>120@
5=4:>120@

5HVHUYHG

•

Note:

1. MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 2 (MR2)

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CAS Write Latency (CWL)

CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 58 (page 149)). The overall WRITE la-
tency (WL) is equal to CWL + AL (See Figure below).

Figure 59: CAS Write Latency

CK

CK#

Command

DQ

DQS, DQS#

ACTIVE n

T0

T1

Don’t Care

NOP

NOP

T6

T12

NOP

WRITE n

T13

NOP

DI

 n + 3

DI

 n + 2

DI

 n + 1

T14

NOP

DI

 n

t

RCD (MIN)

NOP

AL = 5

T11

Indicates break
in time scale

WL = AL + CWL = 11

Transitioning Data

T2

CWL = 6

AUTO SELF REFRESH (ASR)

Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
sure the DRAM never exceeds a T

C

 of 85°C while in self refresh unless the user enables

the SRT feature listed below when the T

C

 is between 85°C and 105°C.

Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to
2x when the case temperature exceeds 85°C. This enables the user to operate the DRAM
beyond the standard 85°C limit up to the optional extended temperature range of 105°C
while in self refresh mode.

The standard self refresh current test specifies test conditions to normal case tempera-
ture (85°C) only, meaning if ASR is enabled, the standard self refresh current specifica-
tions do not apply (see Extended Temperature Usage).

SELF REFRESH TEMPERATURE (SRT)

Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, SRT requires the user to en-
sure the DRAM never exceeds a T

of 85°C while in self refresh mode unless the user en-

ables ASR.

When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regard-
less of the case temperature. This enables the user to operate the DRAM beyond the
standard 85°C limit up to the optional extended temperature range of 105°C while in
self refresh mode. The standard self refresh current test specifies test conditions to nor-

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 2 (MR2)

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mal case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh
current specifications do not apply (see Extended Temperature Usage).

SRT vs. ASR

If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR
is required, and both can be disabled throughout operation. However, if the extended
temperature option of up to 105°C is needed, the user is required to provide a 2x refresh
rate during (manual) refreshes when the device is (>85°C but less than 95°C) or 4X re-
freshes (>95°C but less than 105°C) and enable either the SRT or the ASR to ensure self
refresh is performed at the 2x rate.

SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is
performed at the 2x refresh rate regardless of the case temperature.

ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. Howev-
er, while in self refresh mode, ASR enables the refresh rate to automatically adjust be-
tween 1x to 2x over the supported temperature range. One other disadvantage with ASR
is the DRAM cannot always switch from a 1x to a 2x refresh rate at an exact case temper-
ature of 85°C. Although the DRAM will support data integrity when it switches from a 1x
to a 2x refresh rate, it may switch at a lower temperature than 85°C.

Since only one mode is necessary, SRT and ASR cannot be enabled at the same time.

DYNAMIC ODT

The dynamic ODT (R

TT(WR)

) feature is defined by MR2[10, 9]. Dynamic ODT is enabled

when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT ter-
mination on-the-fly.

With dynamic ODT (R

TT(WR)

) enabled, the DRAM switches from normal ODT (R

TT_nom

)

to dynamic ODT (R

TT(WR)

) when beginning a WRITE burst and subsequently switches

back to ODT (R

TT_nom

) at the completion of the WRITE burst. If R

TT_nom

 is disabled, the

R

TT_nom

 value will be High-Z. Special timing parameters must be adhered to when dy-

namic ODT (R

TT(WR)

) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,

and 

t

ADC.

Dynamic ODT is only applicable during WRITE cycles. If ODT (R

TT_nom

) is disabled, dy-

namic ODT (R

TT(WR)

) is still permitted. R

TT_nom

 and R

TT(WR)

 can be used independent of

one other. Dynamic ODT is not available during write leveling mode, regardless of the
state of ODT (R

TT_nom

). For details on dynamic ODT operation, refer to Dynamic ODT

(page 199).

Mode Register 3 (MR3)

The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 60 (page 152). The MR3 is pro-
grammed via the LOAD MODE command and retains the stored information until it is
programmed again or until the device loses power. Reprogramming the MR3 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR3 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time 

t

MRD and 

t

MOD before initiating a sub-

sequent operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 60: Mode Register 3 (MR3) Definition

A9

A7

A6 A5

A4 A3

A8

A2

A1

A0

Mode register 3 (MR3)

Address bus

9

7

6

5

4

3

8

2

1

0

A10

A12 A11

BA0

BA1

10

11

12

13

14

15

A13

A14

A15

01

01

01

01

01 01 01

01

01

MPR 

1

1

BA2

16

17

18

01

01

01

01

01

M2

0

1

MPR Enable

Normal DRAM operations2

Dataflow from MPR

MPR_RF

M16

0

1

0

1

M17

0

0

1

1

Mode Register 

Mode register set (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

MPR READ Function

Predefined  pattern3

Reserved

Reserved

Reserved

M0

0

1

0

1

M1

0

0

1

1

Notes:

1. MR3[18 and 15:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.

MULTIPURPOSE REGISTER (MPR)

The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 61 (page 153).

If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a prede-
fined read pattern for system calibration is selected.

To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-
ing the MRS command, all banks must be in the idle state (all banks are precharged,
and 

t

RP is met). When the MPR is enabled, any subsequent READ or RDAP commands

are redirected to the multipurpose register. The resulting operation when either a READ
or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see 
Table 78 (page 154)). When the MPR is enabled, only READ or RDAP commands are al-
lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-
lowed during MPR enable mode. The RESET function is supported during MPR enable
mode.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 61: Multipurpose Register (MPR) Block Diagram

Memory core

MR3[2] = 0 (MPR off)

DQ, DM, DQS, DQS#

Multipurpose register

predefined data for READs

MR3[2] = 1 (MPR on)

Notes:

1. A predefined data pattern can be read out of the MPR with an external READ com-

mand.

2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When

the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.

Table 77: MPR Functional Description of MR3 Bits

MR3[2]

MR3[1:0]

Function

MPR

MPR READ Function

0

“Don’t Care”

Normal operation, no MPR transaction

All subsequent READs come from the DRAM memory array

All subsequent WRITEs go to the DRAM memory array

1

A[1:0]

(see Table 78 (page 154))

Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and

2

MPR Functional Description

The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining
DQs driven LOW, or for all DQs to output the MPR data . The MPR readout supports
fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ
latencies and AC timings applicable, provided the DLL is locked as required.

MPR addressing for a valid MPR read is as follows:

• A[1:0] must be set to 00 as the burst order is fixed per nibble
• A2 selects the burst order:

– BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7

• For burst chop 4 cases, the burst order is switched on the nibble base along with the

following:

– A2 = 0; burst order = 0, 1, 2, 3

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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– A2 = 1; burst order = 4, 5, 6, 7

• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is

assigned to MSB

• A[9:3] are a “Don’t Care”
• A10 is a “Don’t Care”
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0
• A13 is a “Don’t Care”
• BA[2:0] are a “Don’t Care”

MPR Register Address Definitions and Bursting Order

The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 0–1 bit pat-
tern.

Examples of the different types of predefined READ pattern bursts are shown in the fol-
lowing figures.

Table 78: MPR Readouts and Burst Order Bit Mapping

MR3[2]

MR3[1:0]

Function

Burst

Length

Read

A[2:0]

Burst Order and Data Pattern

1

00

READ predefined pattern

for system calibration

BL8

000

Burst order: 0, 1, 2, 3, 4, 5, 6, 7

Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1

BC4

000

Burst order: 0, 1, 2, 3

Predefined pattern: 0, 1, 0, 1

BC4

100

Burst order: 4, 5, 6, 7

Predefined pattern: 0, 1, 0, 1

1

01

RFU

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

1

10

RFU

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

1

11

RFU

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Note:

1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selec-

ted MPR agent.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout

T0

Ta0

Tb0

Tb1

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

CK

CK#

MRS

PREA

READ

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Valid

Command

t

MPRR

Don’t Care

Indicates break
in time scale

DQS, DQS#

Bank address

3

Valid

3

0

A[1:0]

Valid

0

2

1

A2

0

2

0

00

A[9:3]

Valid

00

0

1

A10/AP

Valid

0

0

A11

Valid

0

0

A12/BC#

Valid

1

0

0

A[15:13]

Valid

0

DQ 

t

MOD

t

RP

t

MOD

RL

Notes:

1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 63: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout

T0

Ta

Tb

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

CK

CK#

t

MPRR

Don’t Care

Indicates break
in time scale

RL

3

Valid

3

Bank address

Valid

A[1:0]

Valid

0

2

0

2

0

A2

1

2

0

2

1

0

0

A[15:13]

Valid

Valid

0

A[9:3]

Valid

Valid

00

00

A11

Valid

Valid

0

0

A12/BC#

Valid

1

0

0

A10/AP

Valid

Valid

0

0

1

RL

PREA

READ

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

MRS

Valid

Command

READ

1

MRS

DQ 

Valid

DQS, DQS#

t

RP

t

MOD

t

CCD

t

MOD

Notes:

1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 64: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble

T0

Ta

Tb

CK

CK#

DQ 

DQS, DQS#

t

MOD

t

MPRR

Don’t Care

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Valid

Command

MRS

PREA

READ

1

READ

1

NOP

NOP

Indicates break
in time scale

Bank address

3

Valid

3

Valid

0

A[1:0]

Valid

0

2

0

2

1

A2

1

4

0

3

0

00

A[9:3]

Valid

Valid

00

0

1

A10/AP

Valid

Valid

0

0

A11

Valid

Valid

0

0

A12/BC#

Valid

1

Valid

1

0

0

A[15:13]

Valid

Valid

0

RL

RL

t

RF

t

MOD

t

CCD

Notes:

1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
4. A2 = 1 selects upper 4 nibble bits 4 . . . 7.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 65: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble

T0

Ta

Tb

0

1

A10/AP

Valid

Valid

0

CK

CK#

MRS

PREA

READ

1

READ

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Valid

Command

0

0

4

1

3

1

A2

t

MOD

t

MPRR

3

Valid

3

Bank address

Valid

0

2

0

2

0

A[1:0]

Valid

0

0

A[15:13]

Valid

Valid

0

0

A11

Valid

Valid

00

00

A[9:3]

Valid

Valid

Don’t Care

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

Indicates break
in time scale

RL

DQ 

DQS, DQS#

0

A12/BC#

Valid

1

Valid

1

0

RL

t

RF

t

MOD

t

CCD

Notes:

1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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MPR Read Predefined Pattern

The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The
following is an example of using the read out predetermined read calibration pattern.
The example is to perform multiple reads from the multipurpose register to do system
level read timing calibration based on the predetermined and standardized pattern.

The following protocol outlines the steps used to perform the read calibration:

1. Precharge all banks
2. After 

t

RP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all sub-

sequent reads and loads the predefined pattern into the MPR. As soon as 

t

MRD

and 

t

MOD are satisfied, the MPR is available

3. Data WRITE operations are not allowed until the MPR returns to the normal

DRAM state

4. Issue a read with burst order information (all other address pins are “Don’t Care”):

• A[1:0] = 00 (data burst order is fixed starting at nibble)
• A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
• A12 = 1 (use BL8)

5. After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern

(0, 1, 0, 1, 0, 1, 0, 1)

6. The memory controller repeats the calibration reads until read data capture at

memory controller is optimized

7. After the last MPR READ burst and after 

t

MPRR has been satisfied, issue MRS,

MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subse-
quent read and write accesses will be regular reads and writes from/to the DRAM
array

8. When 

t

MRD and 

t

MOD are satisfied from the last MRS, the regular DRAM com-

mands (such as activate a memory bank for regular read or write access) are per-
mitted

MODE REGISTER SET (MRS) Command

The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which
mode register is programmed:

• BA2 = 0, BA1 = 0, BA0 = 0 for MR0
• BA2 = 0, BA1 = 0, BA0 = 1 for MR1
• BA2 = 0, BA1 = 1, BA0 = 0 for MR2
• BA2 = 0, BA1 = 1, BA0 = 1 for MR3

The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (

t

RP is satisfied and no data bursts are in progress). The controller

must wait the specified time 

t

MRD before initiating a subsequent operation such as an

ACTIVATE command (see Figure 52 (page 140)). There is also a restriction after issuing
an MRS command with regard to when the updated functions become available. This
parameter is specified by 

t

MOD. Both 

t

MRD and 

t

MOD parameters are shown in Figure

52 (page 140) and Figure 53 (page 141). Violating either of these requirements will result
in unspecified operation.

4Gb: x4, x8, x16 DDR3L SDRAM

MODE REGISTER SET (MRS) Command

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ZQ CALIBRATION Operation

The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R

ON

)

and ODT values (R

TT

) over process, voltage, and temperature, provided a dedicated

240

ȍ

 (±1%) external resistor is connected from the DRAM’s ZQ ball to V

SSQ

.

DDR3 SDRAM require a longer time to calibrate R

ON

 and ODT at power-up initialization

and self refresh exit, and a relatively shorter time to perform periodic calibrations.
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example
of ZQ calibration timing is shown below.

All banks must be precharged and 

t

RP must be met before ZQCL or ZQCS commands

can be issued to the DRAM. No other activities (other than issuing another ZQCL or
ZQCS command) can be performed on the DRAM channel by the controller for the du-
ration of 

t

ZQinit or 

t

ZQoper. The quiet time on the DRAM channel helps accurately cali-

brate R

ON

 and ODT. After DRAM calibration is achieved, the DRAM should disable the

ZQ ball’s current consumption path to reduce power.

ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.

In dual-rank systems that share the ZQ resistor between devices, the controller must not
enable overlap of 

t

ZQinit, 

t

ZQoper, or 

t

ZQCS between ranks.

Figure 66: ZQ CALIBRATION Timing (ZQCL and ZQCS)

NOP

ZQCL

NOP

NOP

Valid

Valid

ZQCS

NOP

NOP

NOP

Valid

Command

Indicates break
in time scale

T0

T1

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tc0

Tc1

Tc2

Address

Valid

Valid

Valid

A10

Valid

Valid

Valid

CK

CK#

Don’t Care

DQ

High-Z

High-Z

3

3

Activities

Activ-
ities

Valid

Valid

ODT

2

2

Valid

1

CKE

1

Valid

Valid

Valid

t

ZQCS

t

ZQinit or 

t

ZQoper

Notes:

1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.

4Gb: x4, x8, x16 DDR3L SDRAM

ZQ CALIBRATION Operation

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ACTIVATE Operation

Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE com-
mand, which selects both the bank and the row to be activated.

After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the 

t

RCD specification. However, if the additive latency

is programmed correctly, a READ or WRITE command may be issued prior to 

t

RCD

(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to 

t

RCD (MIN) with the require-

ment that (ACTIVATE-to-READ/WRITE) + AL 

•

 

t

RCD (MIN) (see Posted CAS Additive

Latency). 

t

RCD (MIN) should be divided by the clock period and rounded up to the next

whole number to determine the earliest clock edge after the ACTIVATE command on
which a READ or WRITE command can be entered. The same procedure is used to con-
vert other specification limits from time units to clock cycles.

When at least one bank is open, any READ-to-READ command delay or WRITE-to-
WRITE command delay is restricted to 

t

CCD (MIN).

A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time in-
terval between successive ACTIVATE commands to the same bank is defined by 

t

RC.

A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is de-
fined by 

t

RRD. No more than four bank ACTIVATE commands may be issued in a given

t

FAW (MIN) period, and the 

t

RRD (MIN) restriction still applies. The 

t

FAW (MIN) param-

eter applies, regardless of the number of banks already opened or closed.

Figure 67: Example: Meeting 

t

RRD (MIN) and 

t

RCD (MIN)

Command

Don’t Care

T1

T0

T2

T3

T4

T5

T8

T9

t

RRD

Row

Row

Col

Bank x

Bank y

Bank y

NOP

ACT

NOP

NOP

ACT

NOP

NOP

RD/WR

t

RCD

BA[2:0]

CK#

Address

CK

T10

T11

NOP

NOP

Indicates break
in time scale

4Gb: x4, x8, x16 DDR3L SDRAM

ACTIVATE Operation

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Figure 68: Example: 

t

FAW

Command

Don’t Care

T1

T0

T4

T5

T8

T9

T10

T11

t

RRD

Row

Row

Bank a

Bank b

Row

Bank c

Row

Bank d

Bank y

Row

Bank y

NOP

ACT

NOP

ACT

ACT

NOP

NOP

t

FAW

BA[2:0]

CK#

Address

CK

T19

T20

NOP

ACT

ACT

Bank e

Indicates break
in time scale

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ACTIVATE Operation

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READ Operation

READ bursts are initiated with a READ command. The starting column and bank ad-
dresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-
ble in the mode register via the MRS command. Each subsequent data-out element is
valid nominally at the next positive or negative clock edge (that is, at the next crossing
of CK and CK#). Figure 69 shows an example of RL based on a CL setting of 8 and an AL
setting of 0.

Figure 69: READ Latency

CK

CK#

Command

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Address

Bank a,

Col n

CL = 8, AL = 0

DQ

DQS, DQS#

DO

n

T0

T7

T8

T9

T10

T11

Don’t Care

Transitioning Data

T12

T12

Indicates break
in time scale

Notes:

1. DO 

n

 = data-out from column 

n

.

2. Subsequent elements of data-out appear in the programmed order following DO 

n

.

DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS and HIGH state on DQS# is known as the READ preamble (

t

RPRE). The LOW state

on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (

t

RPST). Upon completion of a burst, assuming no other

commands have been initiated, the DQ goes High-Z. A detailed explanation of 

t

DQSQ

(valid data-out skew), 

t

QH (data-out window hold), and the valid data window are de-

picted in Figure 80 (page 171). A detailed explanation of 

t

DQSCK (DQS transition skew

to CK) is also depicted in Figure 80 (page 171).

Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued 

t

CCD cycles after the first READ command. This is shown for BL8 in Figure 70

(page 165). If BC4 is enabled, 

t

CCD must still be met, which will cause a gap in the data

output, as shown in Figure 71 (page 165). Nonconsecutive READ data is reflected in 
Figure 72 (page 166). DDR3 SDRAM does not allow interrupting or truncating any
READ burst.

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READ Operation

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Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Fig-
ure 73 (page 166) (BC4 is sho
wn in Figure 74 (page 167)). To ensure the READ data is
completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing
is RL + 

t

CCD - WL + 2

t

CK.

A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called 

t

RTP (READ-to-PRECHARGE). 

t

RTP starts AL

cycles later than the READ command. Examples for BL8 are shown in Figure 75 (page
167) and BC4 in Figure 76 (page 168). Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until 

t

RP is met. The PRECHARGE

command followed by another PRECHARGE command to the same bank is allowed.
However, the precharge period will be determined by the last PRECHARGE command
issued to the bank.

If A10 is HIGH when a READ command is issued, the READ with auto precharge func-
tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL + 

t

RTP cycles after the READ command. DRAM support a 

t

RAS lockout feature (see 

Figure 78 (page 168)). I

t

RAS (MIN) is not satisfied at the edge, the starting point of the

auto precharge operation will be delayed until 

t

RAS (MIN) is satisfied. If 

t

RTP (MIN) is

not satisfied at the edge, the starting point of the auto precharge operation is delayed
until 

t

RTP (MIN) is satisfied. In case the internal precharge is pushed out by 

t

RTP, 

t

RP

starts at the point at which the internal precharge happens (not at the next rising clock
edge after this event). The time from READ with auto precharge to the next ACTIVATE
command to the same bank is AL + (

t

RTP + 

t

RP)*, where * means rounded up to the next

integer. In any event, internal precharge does not start earlier than four clocks after the
last 8

n

-bit prefetch.

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READ Operation

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Figure 70: Consecutive READ Bursts (BL8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

t

RPST

NOP

READ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ3

DQS, DQS#

Bank,

Col n

Bank,

Col b

Address

2

RL = 5

t

RPRE

t

CCD

RL = 5

DO

 n + 3

DO

 n + 2

DO

 n + 1

DO

 n

DO

 n + 7

DO

 n + 6

DO

 n + 5

DO 

n + 4

DO

 b + 3

DO

 b + 2

DO

 b + 1

DO

 b

DO

 b + 7

DO

 b + 6

DO

 b + 5

DO 

b + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0

and T4.

3. DO 

n

 (or 

b

) = data-out from column 

n

 (or column 

b

).

4. BL8, RL = 5 (CL = 5, AL = 0).

Figure 71: Consecutive READ Bursts (BC4)

NOP

CK

CK#

Command

1

DQ3

DQS, DQS#

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Address

2

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

READ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Bank,

Col n

Bank,

Col b

t

RPST

t

RPRE

t

RPST

t

RPRE

RL = 5

DO

 n + 3

DO

 n + 2

DO

 n + 1

DO

 n

DO

 b + 3

DO

 b + 2

DO

 b + 1

DO

 b

RL = 5

t

CCD

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0

and T4.

3. DO 

n

 (or 

b

) = data-out from column 

n

 (or column 

b

).

4. BC4, RL = 5 (CL = 5, AL = 0).

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READ Operation

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Figure 72: Nonconsecutive READ Bursts

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

DQS, DQS#

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

READ

NOP

READ

Address

Bank a,

Col n

Bank a,

Col b

CK

CK#

DQ

DO

n

DO

b

CL = 8 

CL = 8 

Notes:

1. AL = 0, RL = 8.
2. DO 

n

 (or 

b

) = data-out from column 

n

 (or column 

b

).

3. Seven subsequent elements of data-out appear in the programmed order following DO 

n

.

4. Seven subsequent elements of data-out appear in the programmed order following DO 

b

.

Figure 73: READ (BL8) to WRITE (BL8)

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

CK

CK#

Command

1

NOP

NOP

NOP

NOP

NOP

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

WPST

t

RPRE

t

WPRE

t

RPST

DQS, DQS#

DQ3

WL = 5

t

WR

t

WR

READ

DO

 n

DO

 n + 1

DO

 n + 2

DO

 n + 3

DO

 n + 4

DO

 n + 5

DO

 n + 6

DO

 n + 7

DI

 n

DI

 n + 1

DI

 n + 2

DI

 n + 3

DI

 n + 4

DI

 n + 5

DI

 n + 6

DI

 n + 7

READ-to-WRITE command delay = RL + 

t

CCD + 2

t

CK - WL

t

BL = 4 clocks

Address

2

Bank,

Col b

Bank,

Col n

RL = 5

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at

T0, and the WRITE command at T6.

3. DO 

n

 = data-out from column, DI 

b

 = data-in for column 

b

.

4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

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READ Operation

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Figure 74: READ (BC4) to WRITE (BC4) OTF

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

CK

CK#

Address

2

Command

1

t

WPST

t

WPRE

t

RPST

DQS, DQS#

DQ3

WL = 5

t

WR

t

WTR

t

BL = 4 clocks

t

RPRE

RL = 5

READ-to-WRITE command delay = RL + 

t

CCD/2 + 2

t

CK - WL

READ

DO

n

DO

n +  1

DO

n +  2

DO

n + 3

DI

n

DI

n + 1

DI

n + 2

DI

n +  3

Bank,

Col b

Bank,

Col n

NOP

NOP

NOP

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at

T4.

3. DO 

n

 = data-out from column 

n

; DI 

n

 = data-in from column 

b

.

4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

Figure 75: READ to PRECHARGE (BL8)

t

RAS

t

RTP

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

DQ

DQS, DQS#

Don’t Care

Transitioning Data

NOP

NOP

NOP

NOP

NOP

ACT

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

NOP

READ

Bank a,

Col n

NOP

PRE

Bank a,

(or all)

Bank a,

Row b

t

RP

DO

n

DO

n + 1

DO

n + 2

DO

n + 3

DO

n + 4

DO

n + 5

DO

n + 6

DO

n + 7

4Gb: x4, x8, x16 DDR3L SDRAM

READ Operation

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Figure 76: READ to PRECHARGE (BC4)

CK

CK#

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

ACT

NOP

NOP

NOP

NOP

NOP

READ

NOP

PRE

Address

Bank a,

Col n

Bank a,

(or all)

Bank a,

Row b

t

RP

t

RTP

DQS, DQS#

DQ

DO

n

DO

n + 1

DO

n + 2

DO

n + 3

t

RAS

Figure 77: READ to PRECHARGE (AL = 5, CL = 6)

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

DQ

DQS, DQS#

Don’t Care

Transitioning Data

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

NOP

READ

Bank a,

Col n

NOP

PRE

Bank a,

(or all)

ACT

Bank a,

Row b

NOP

NOP

t

RAS

CL = 6

AL = 5

t

RTP

t

RP

DO

n + 3

DO

n + 2

DO

n

DO

n + 1

Figure 78: READ with Auto Precharge (AL = 4, CL = 6)

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

DQ

DQS, DQS#

Don’t Care

Transitioning Data

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

Ta0

t

RTP (MIN)

NOP

READ

NOP

AL = 4

NOP

NOP

CL = 6

NOP

t

RAS (MIN)

ACT

Indicates break
in time scale

t

RP

Bank a,

Col n

Bank a,

Row b

DO

n

DO

n + 1

DO

n + 2

DO

n + 3

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READ Operation

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DQS to DQ output timing is shown in Figure 79 (page 170). The DQ transitions between
valid data outputs must be within 

t

DQSQ of the crossing point of DQS, DQS#. DQS must

also maintain a minimum HIGH and LOW time of 

t

QSH and 

t

QSL. Prior to the READ

preamble, the DQ balls will either be floating or terminated, depending on the status of
the ODT signal.

Figure 80 (page 171) shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±

t

DQSCK of the clock crossing point. The data

out has no timing relationship to CK, only to DQS, as shown in Figure 80 (page 171).

Figure 80 (page 171) also shows the READ preamble and postamble. Typically, both
DQS and DQS# are High-Z to save power (V

DDQ

). Prior to data output from the DRAM,

DQS is driven LOW and DQS# is HIGH for 

t

RPRE. This is known as the READ preamble.

The READ postamble, 

t

RPST, is one half clock from the last DQS, DQS# transition. Dur-

ing the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the
DQ is disabled or continues terminating, depending on the state of the ODT signal. Fig-
ure 83 (page 173) demonstr
ates how to measure 

t

RPST.

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READ Operation

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Figure 79: Data Output Timing – 

t

DQSQ and Data Valid Window

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

Bank,

Col n

t

RPST

NOP

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

Address

2

t

DQSQ (MAX)

DQS, DQS#

DQ

3

 (last data valid)

DQ

3

 (first data no longer valid)

All DQ collectively

DO

n

DO

n + 3

DO

n + 2

DO

n + 1

DO

n + 7

DO

n + 6

DO

n + 5

DO

n + 4

DO

n + 2

DO

n + 1

DO

n + 7

DO

n + 6

DO

n + 5

DO

n + 4

DO

 n + 3

DO

 n + 2

DO

 n + 1

DO

 n

DO

 n + 7

DO

 n + 6

DO

 n + 5

DO

 n

DO

n + 3

t

RPRE

Don’t Care

Data valid

Data valid

t

QH

t

QH

t

HZDQ (MAX)

DO 

n + 4

RL = AL + CL

t

DQSQ (MAX)

t

LZDQ (MIN)

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at

T0.

3. DO 

n

 = data-out from column 

n

.

4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to V

DDQ

/2 and DLL on and locked.

6.

t

DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.

7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within

a burst.

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READ Operation

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t

HZ and 

t

LZ transitions occur in the same access time as valid data transitions. These

parameters are referenced to a specific voltage level that specifies when the device out-
put is no longer driving 

t

HZDQS and 

t

HZDQ, or begins driving 

t

LZDQS, 

t

LZDQ. Figure

81 (page 172) shows a method of calculating the point when the device is no longer
driving 

t

HZDQS and 

t

HZDQ, or begins driving 

t

LZDQS, 

t

LZDQ, by measuring the signal

at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters 

t

LZDQS, 

t

LZDQ, 

t

HZDQS, and 

t

HZDQ

are defined as single-ended.

Figure 80: Data Strobe Timing – READs

RL measured

to this point

DQS, DQS#

early strobe

CK

t

LZDQS (MIN)

t

HZDQS (MIN)

DQS, DQS#

late strobe

t

LZDQS (MAX)

t

HZDQS (MAX)

t

DQSCK (MAX)

t

DQSCK (MAX)

t

DQSCK (MAX)

t

DQSCK (MAX)

t

DQSCK (MIN)

t

DQSCK (MIN)

t

DQSCK (MIN)

t

DQSCK (MIN)

CK#

t

RPRE

t

QSH

t

QSH

t

QSL

t

QSL

t

QSL

t

QSL

t

QSH

t

QSH

Bit 0

Bit 1

Bit 2

Bit 7

t

RPRE

Bit 0

Bit 1

Bit 2

Bit 7

Bit 6

Bit 3

Bit 4

Bit 5

Bit 6

Bit 4

Bit 3

Bit 5

t

RPST

t

RPST

T0

T1

T2

T3

T4

T5

T6

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READ Operation

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Figure 81: Method for Calculating 

t

LZ and 

t

HZ

t

HZDQS, 

t

HZDQ

t

HZDQS, 

t

HZDQ end point = 2 × T1 - T2

V

OH

 - xmV

V

TT

 - xmV

V

OL

 + xmV

V

TT

 + xmV

V

OH

 - 2xmV

V

TT

 - 2xmV

V

OL

 + 2xmV

V

TT

 + 2xmV

t

LZDQS, 

t

LZDQ

t

LZDQS, 

t

LZDQ begin point = 2 × T1 - T2

T1

T1

T2

T2

Notes:

1. Within a burst, the rising strobe edge is not necessarily fixed at 

t

DQSCK (MIN) or 

t

DQSCK

(MAX). Instead, the rising strobe edge can vary between 

t

DQSCK (MIN) and 

t

DQSCK

(MAX).

2. The DQS HIGH pulse width is defined by 

t

QSH, and the DQS LOW pulse width is defined

by 

t

QSL. Likewise, 

t

LZDQS (MIN) and 

t

HZDQS (MIN) are not tied to 

t

DQSCK (MIN) (early

strobe case), and 

t

LZDQS (MAX) and 

t

HZDQS (MAX) are not tied to 

t

DQSCK (MAX) (late

strobe case); however, they tend to track one another.

3. The minimum pulse width of the READ preamble is defined by 

t

RPRE (MIN). The mini-

mum pulse width of the READ postamble is defined by 

t

RPST (MIN).

Figure 82: 

t

RPRE Timing

tRPRE

DQS - DQS# 

DQS

DQS#

T1

t

RPRE begins

T2

t

RPRE ends

CK

CK#

V

TT

Resulting differential 
signal relevant for 

t

RPRE specification

t

C

t

A

t

B

t

D

Single-ended signal provided
as background information

0V

Single-ended signal provided
as background information

V

TT

V

TT

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Figure 83: 

t

RPST Timing

t

RPST

DQS - DQS#

DQS 

DQS#

T1

t

RPST begins

T2

t

RPST ends

Resulting differential 
signal relevant for 

t

RPST specification

CK

CK#

V

TT

t

C

t

A

t

B

t

D

Single-ended signal, provided
as background information

Single-ended signal, provided
as background information

0V

V

TT

V

TT

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READ Operation

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WRITE Operation

WRITE bursts are initiated with a WRITE command. The starting column and bank ad-
dresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the row being accessed is pre-
charged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in Figure
86 (page 176) thr
ough Figure 94 (page 181), auto precharge is disabled.

During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,
DQS#) and specified as the WRITE preamble shown in Figure 86 (page 176). The half
cycle on DQS following the last data-in element is known as the WRITE postamble.

The time between the WRITE command and the first valid edge of DQS is WL clocks
±

t

DQSS. Figure 87 (page 177) through Figure 94 (page 181) show the nominal case

where 

t

DQSS = 0ns; however, Figure 86 (page 176) includes 

t

DQSS (MIN) and 

t

DQSS

(MAX) cases.

Data may be masked from completing a WRITE using data mask. The data mask occurs
on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal-
ly. If DM is HIGH, that bit of data is masked.

Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide a continuous flow of input data. The new WRITE command can be 

t

CCD clocks

following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figure 87 (page 177) and Figure 88
(page 177) show concatenated bursts. An example of nonconsecutive WRITEs is shown
in Figure 89 (page 178).

Data for any WRITE burst may be followed by a subsequent READ command after 

t

WTR

has been met (see Figure 90 (page 178), Figure 91 (page 179), and Figure 92 (page
180)).

Data for any WRITE burst may be followed by a subsequent PRECHARGE command,
providing 

t

WR has been met, as shown in Figure 93 (page 181) and Figure 94 (page

181).

Both 

t

WTR and 

t

WR starting time may vary, depending on the mode register settings

(fixed BC4, BL8 versus OTF).

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WRITE Operation

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Figure 84: 

t

WPRE Timing

DQS - DQS#

T1

t

WPRE begins

T2

t

WPRE ends

t

WPRE

Resulting differential 

signal relevant for 

t

WPRE specification

0V

CK

CK#

V

TT

Figure 85: 

t

WPST Timing

t

WPST

DQS - DQS#

T1

t

WPST begins

T2

t

WPST ends

Resulting differential 

signal relevant for 

t

WPST specification

0V

CK

CK#

V

TT

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WRITE Operation

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Figure 86: WRITE Burst

DI

n + 3

DI

 n + 2

DI

n + 1

DI

n

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

Don’t Care

Transitioning Data

DI

n + 7

DI

 n + 6

DI

n + 5

DI

n + 4

Bank,

Col n

NOP

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

3

DQS, DQS#

Address

2

t

WPST

t

WPRE

t

WPST

t

DQSL

DQ

3

DQ

3

t

WPST

DQS, DQS#

DQS, DQS#

t

DQSL

t

WPRE

t

DQSS

t

DQSS

t

DSH

t

DSH

t

DSH

t

DSH

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSH

t

DSH

t

DSH

t

DSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSH

t

DQSL

t

DQSL

t

DQSL

t

DQSL

t

DQSH

t

DQSH

t

DQSH

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSH

WL = AL + CWL

t

DQSS (MIN)

t

DQSS (NOM)

t

DQSS (MAX)

t

DQSL

t

WPRE

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

DI

n + 7

DI

 n + 6

DI

 n + 5

DI

n + 4

DI

n + 3

DI

n + 2

DI

n + 1

DI

 n

DI

n + 7

DI

n + 6

DI

n + 5

DI

n + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

the WRITE command at T0.

3. DI 

n

 = data-in for column 

n

.

4. BL8, WL = 5 (AL = 0, CWL = 5).
5.

t

DQSS must be met at each rising clock edge.

6.

t

WPST is usually depicted as ending at the crossing of DQS, DQS#; however, 

t

WPST ac-

tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.

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Figure 87: Consecutive WRITE (BL8) to WRITE (BL8)

WL = 5

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CCD

t

WPRE

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

Valid

Valid

NOP

WRITE

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

3

DQS, DQS#

Address

2

t

WPST

t

WR

t

WTR

t

BL = 4 clocks

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

DI

 n + 7

DI

 n + 6

DI

n + 5

DI

n + 4

DI

 b + 3

DI

 b + 2

DI

 b + 1

DI

 b

DI

 b + 7

DI

 b + 6

DI

 b + 5

DI

b + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at

T0 and T4.

3. DI 

n

 (or 

b

) = data-in for column 

n

 (or column 

b

).

4. BL8, WL = 5 (AL = 0, CWL = 5).

Figure 88: Consecutive WRITE (BC4) to WRITE (BC4) via OTF

WL = 5

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CCD

t

WPRE

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

Valid

Valid

NOP

WRITE

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

3

DQS, DQS#

Address

2

t

WPST

t

WR

t

WTR

t

WPST

t

WPRE

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

n

DI

 b + 3

DI

 b + 2

DI

 b + 1

DI

 b

t

BL = 4 clocks

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. BC4, WL = 5 (AL = 0, CWL = 5).
3. DI 

n

 (or 

b

) = data-in for column 

n

 (or column 

b

).

4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
5. If set via MRS (fixed) 

t

WR and 

t

WTR would start T11 (2 cycles earlier).

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WRITE Operation

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Figure 89: Nonconsecutive WRITE to WRITE

CK

CK#

Command

NOP

NOP

NOP

Address

DQ

DM

DQS, DQS#

Transitioning Data

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

NOP

WRITE

NOP

WRITE

Valid

Valid

NOP

DI

n

DI

n + 1

DI

n + 2

DI

n + 3

DI

n + 4

DI

n + 5

DI

n + 6

Don't Care

DI

n + 7

DI

b

DI

b + 1

DI

b + 2

DI

b + 3

DI

b + 4

DI

b + 5

DI

b + 6

DI

b + 7

WL = CWL + AL  = 7

WL = CWL + AL  = 7

Notes:

1. DI 

n

 (or 

b

) = data-in for column

 n

 (or column 

b

).

2. Seven subsequent elements of data-in are applied in the programmed order following DO 

n

.

3. Each WRITE command may be to any bank.
4. Shown for WL = 7 (CWL = 7, AL = 0).

Figure 90: WRITE (BL8) to READ (BL8)

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

WPRE

T10

T11

Don’t Care

Transitioning Data

Ta0

NOP

WRITE

READ

Valid

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

4

DQS, DQS#

Address

3

t

WPST

t

WTR

2

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

DI

n + 7

DI

n + 6

DI

n + 5

DI

n + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.

t

WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last

write data shown at T9.

3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command

at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.

4. DI 

n

 = data-in for column 

n

.

5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

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Figure 91: WRITE to READ (BC4 Mode Register Setting)

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Ta0

Don’t Care

Transitioning Data

NOP

WRITE

Valid

READ

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

4

DQS, DQS#

Address

3

t

WPST

t

WTR

2

t

WPRE

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.

t

WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last

write data shown at T7.

3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at

Ta0.

4. DI 

n

 = data-in for column 

n

.

5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).

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WRITE Operation

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Figure 92: WRITE (BC4 OTF) to READ (BC4 OTF)

WL = 5

RL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

WPRE

T10

T11

Don’t Care

Transitioning Data

Tn

NOP

WRITE

READ

Valid

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

4

DQS, DQS#

Address

3

t

WPST

t

BL = 4 clocks

NOP

t

WTR

2

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.

t

WTR controls the WRITE-to-READ delay to the same device and starts after 

t

BL.

3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ

command at T

n

.

4. DI 

n

 = data-in for column 

n

.

5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

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Figure 93: WRITE (BL8) to PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

Ta0

Ta1

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

DI

n + 6

DI

n + 7

DI

n + 5

DI

n + 4

NOP

WRITE

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

PRE

CK

CK#

Command

DQ BL8

DQS, DQS#

Address

Don’t Care

Transitioning Data

Indicates break
in time scale

t

WR

WL = AL + CWL

Valid

Notes:

1. DI 

n

 = data-in from column 

n

.

2. Seven subsequent elements of data-in are applied in the programmed order following

DO 

n

.

3. Shown for WL = 7 (AL = 0, CWL = 7).

Figure 94: WRITE (BC4 Mode Register Setting) to PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

Ta0

Ta1

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

NOP

WRITE

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

PRE

CK

CK#

Command

DQ BC4

DQS, DQS#

Address

Don’t Care

Transitioning Data

Indicates break
in time scale

t

WR

WL = AL + CWL

Valid

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. The write recovery time (

t

WR) is referenced from the first rising clock edge after the last

write data is shown at T7. 

t

WR specifies the last burst WRITE cycle until the PRECHARGE

command can be issued to the same bank.

3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI 

n

 = data-in for column 

n

.

5. BC4 (fixed), WL = 5, RL = 5.

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WRITE Operation

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Figure 95: WRITE (BC4 OTF) to PRECHARGE

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Tn

Don’t Care

Transitioning Data

Bank,

Col n

NOP

WRITE

PRE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command1

DQ4

DQS, DQS#

Address3

t

WPST

t

WPRE

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

t

WR

2

Valid

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. The write recovery time (

t

WR) is referenced from the rising clock edge at T9. 

t

WR speci-

fies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.

3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command

at T0.

4. DI 

n

 = data-in for column 

n

.

5. BC4 (OTF), WL = 5, RL = 5.

DQ Input Timing

Figure 86 (page 176) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25

t

CK of the clock transitions, as limited by 

t

DQSS. All

data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.

The WRITE preamble and postamble are also shown in Figure 86 (page 176). One clock
prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for
a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,

t

WPRE. Likewise, DQS must be kept LOW by the controller after the last data is written

to the DRAM during the WRITE postamble, 

t

WPST.

Data setup and hold times are also shown in Figure 86 (page 176). All setup and hold
times are measured from the crossing points of DQS and DQS#. These setup and hold
values pertain to data input and data mask input.

Additionally, the half period of the data input strobe is specified by 

t

DQSH and 

t

DQSL.

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Figure 96: Data Input Timing

t

DH

t

DH

t

DS

t

DS

DM

DQ

DI

b

DQS, DQS#

Don’t Care

Transitioning Data

t

DQSH

t

DQSL

t

WPRE

t

WPST

4Gb: x4, x8, x16 DDR3L SDRAM

WRITE Operation

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PRECHARGE Operation

Input A10 determines whether one bank or all banks are to be precharged and, in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.

When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.

SELF REFRESH Operation

The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.

All power supply inputs (including V

REFCA

 and V

REFDQ

) must be maintained at valid lev-

els upon entry/exit and during self refresh mode operation. V

REFDQ

 may float or not

drive V

DDQ

/2 while in self refresh mode under certain conditions:

• V

SS

 < V

REFDQ

 < V

DD

 is maintained.

• V

REFDQ

 is valid and stable prior to CKE going back HIGH.

• The first WRITE operation may not occur earlier than 512 clocks after V

REFDQ

 is valid.

• All other self refresh mode exit timing requirements are met.

The DRAM must be idle with all banks in the precharge state (

t

RP is satisfied and no

bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) ( for timing requirements).
If R

TT,nom

 and R

TT(WR)

 are disabled in the mode registers, ODT can be a “Don’t Care.”

After the self refresh entry command is registered, CKE must be held LOW to keep the
DRAM in self refresh mode.

After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-
mand internally within the 

t

CKE period when it enters self refresh mode.

The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting

t

CK specifications) when self refresh mode is entered. If the clock remains stable and

the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after 

t

CKESR is satisfied (CKE is allowed to transition HIGH 

t

CKESR

later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change), 

t

CKSRE and 

t

CKSRX are not required. However, if the

clock is altered during self refresh mode (if it is turned-off or its frequency changes),
then 

t

CKSRE and 

t

CKSRX must be satisfied. When entering self refresh mode, 

t

CKSRE

must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh
mode, 

t

CKSRX must be satisfied prior to registering CKE HIGH.

When CKE is HIGH during self refresh exit, NOP or DES must be issued for 

t

XS time. 

t

XS

is required for the completion of any internal refresh already in progress and must be
satisfied before a valid command not requiring a locked DLL can be issued to the de-
vice. 

t

XS is also the earliest time self refresh re-entry may occur. Before a command re-

quiring a locked DLL can be applied, a ZQCL command must be issued, 

t

ZQOPER tim-

ing must be met, and 

t

XSDLL must be satisfied. ODT must be off during 

t

XSDLL.

4Gb: x4, x8, x16 DDR3L SDRAM

PRECHARGE Operation

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Figure 97: Self Refresh Entry/Exit Timing

CK

CK#

Command

NOP

NOP

4

SRE (REF)

3

Address

CKE

ODT

2

RESET#

2

Valid

Valid

6

SRX (NOP)

NOP

5

t

RP

8

t

XSDLL

7, 9

ODTL

t

IS

t

CPDED

t

IS

t

IS

Enter self refresh mode

(synchronous)

Exit self refresh mode

(asynchronous)

T0

T1

T2

Tc0

Tc1

Td0

Tb0

Don’t Care

Te0

Valid

Valid

7

Valid

Valid

Valid

t

IH

Ta0

Tf0

Indicates break
in time scale

t

CKSRX

1

t

CKSRE

1

t

XS

6, 9

t

CKESR (MIN)

1

Notes:

1. The clock must be valid and stable, meeting 

t

CK specifications at least 

t

CKSRE after en-

tering self refresh mode, and at least 

t

CKSRX prior to exiting self refresh mode, if the

clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then 

t

CKSRE and 

t

CKSRX do not

apply; however, 

t

CKESR must be satisfied prior to exiting at SRX.

2. ODT must be disabled and R

TT

 off prior to entering self refresh at state T1. If both

R

TT,nom

 and R

TT(WR)

 are disabled in the mode registers, ODT can be a “Don’t Care.”

3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the

inputs becoming “Don’t Care.”

5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.

t

XS is required before any commands not requiring a locked DLL.

7.

t

XSDLL is required before any commands requiring a locked DLL.

8. The device must be in the all banks idle state prior to entering self refresh mode. For

example, all banks must be precharged, 

t

RP must be met, and no data bursts can be in

progress.

9. Self refresh exit is asynchronous; however, 

t

XS and 

t

XSDLL timings start at the first rising

clock edge where CKE HIGH satisfies 

t

ISXR at Tc1. 

t

CKSRX timing is also measured so that

t

ISXR is satisfied at Tc1.

4Gb: x4, x8, x16 DDR3L SDRAM

SELF REFRESH Operation

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Extended Temperature Usage

Micron’s DDR3 SDRAM support the optional extended case temperature (T

C

) range of

0°C to 105°C. Thus, the SRT and ASR options must be used at a minimum for tempera-
tures above 85°C (and does not exceed 105°C).

The extended temperature range DRAM must be refreshed manually at 2x (double re-
fresh) anytime the case temperature is above 85°C (and does not exceed 95°C) and 4x
(four times refresh) anytime the case temperature is above 95°C (and does not exceed
105°C). The manual refresh requirement is accomplished by reducing the refresh period
from 64ms to 32ms (2x refresh) or 64ms to 16ms (4x refresh). However, self refresh mode
requires either ASR or SRT to support the extended temperature. Thus, either ASR or
SRT must be enabled when T

C

 is above 85°C or self refresh cannot be used until T

C

 is at

or below 85°C. Table 79 summarizes the two extended temperature options and Table
80 summar
izes how the two extended temperature options relate to one another.

Table 79: Self Refresh Temperature and Auto Self Refresh Description

Field

MR2 Bits

Description

Self Refresh Temperature (SRT)

SRT

7

If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate T

OPER 

during self refresh:

*MR2[7] = 0: Normal operating temperature range (0°C to 85°C)
*MR2[7] = 1: Extended operating temperature range (0°C to 105°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is
supported
*MR2[7] = 0: SRT is disabled

Auto Self Refresh (ASR)

ASR

6

When ASR is enabled, the DRAM automatically provides SELF REFRESH power management func-
tions, (refresh rate for all supported operating temperature values)
* MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate T

OPER 

during SELF REFRESH

operation
* MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)

Table 80: Self Refresh Mode Summary

MR2[6]

(ASR)

MR2[7]

(SRT)

SELF REFRESH Operation

Permitted Operating Temperature
Range for Self Refresh Mode

0

0

Self refresh mode is supported in the normal temperature
range

Normal (0°C to 85°C)

0

1

Self refresh mode is supported in normal and extended temper-
ature ranges; When SRT is enabled, it increases self refresh
power consumption

Normal and extended (0°C to 105°C)

1

0

Self refresh mode is supported in normal and extended temper-
ature ranges; Self refresh power consumption may be tempera-
ture-dependent

Normal and extended (0°C to 105°C)

1

1

Illegal

4Gb: x4, x8, x16 DDR3L SDRAM

Extended Temperature Usage

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Power-Down Mode

Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-
FRESH) are in progress. However, the power-down I

DD

 specifications are not applicable

until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 81). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 98 (page 189) through Figure 107 (page 193).

Table 81: Command to Power-Down Entry Parameters

DRAM Status

Last Command Prior to

CKE LOW

1

Parameter (Min)

Parameter Value

Figure

Idle or active

ACTIVATE

t

ACTPDEN

1

t

CK

Figure 105 (page 192)

Idle or active

PRECHARGE

t

PRPDEN

1

t

CK

Figure 106 (page 193)

Active

READ or READAP

t

RDPDEN

RL + 4

t

CK + 1

t

CK

Figure 101 (page 190)

Active

WRITE: BL8OTF, BL8MRS,

BC4OTF

t

WRPDEN

WL + 4

t

CK + 

t

WR/

t

CK

Figure 102 (page 191)

Active

WRITE: BC4MRS

WL + 2

t

CK + 

t

WR/

t

CK

Figure 102 (page 191)

Active

WRITEAP: BL8OTF, BL8MRS,

BC4OTF

t

WRAPDEN

WL + 4

t

CK + WR + 1

t

CK

Figure 103 (page 191)

Active

WRITEAP: BC4MRS

WL + 2

t

CK + WR + 1

t

CK

Figure 103 (page 191)

Idle

REFRESH

t

REFPDEN

1

t

CK

Figure 104 (page 192)

Power-down

REFRESH

t

XPDLL

Greater of 10

t

CK or 24ns

Figure 108 (page 194)

Idle

MODE REGISTER SET

t

MRSPDEN

t

MOD

Figure 107 (page 193)

Note:

1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-

chronous 

t

ANPD prior to CKE going LOW and remains asynchronous until 

t

ANPD +

t

XPDLL after CKE goes HIGH.

Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until 

t

CPDED has been satis-

fied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.

During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.

The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 210) for detailed ODT usage requirements in slow

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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exit mode precharge power-down. A summary of the two power-down modes is listed in 
Table 82 (page 188).

While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
remain LOW until 

t

PD (MIN) has been satisfied. The maximum time allowed for power-

down duration is 

t

PD (MAX) (9 × 

t

REFI).

The power-down states are synchronously exited when CKE is registered HIGH (with a
required NOP or DES command). CKE must be maintained HIGH until 

t

CKE has been

satisfied. A valid, executable command may be applied after power-down exit latency,

t

XP, and 

t

XPDLL have been satisfied. A summary of the power-down modes is listed be-

low.

For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-
to-power-down-entry sequence, the number of clock cycles between power-down exit
and power-down entry may not be sufficient to keep the DLL properly updated. In addi-
tion to meeting 

t

PD when the REFRESH command is used between power-down exit

and power-down entry, two other conditions must be met. First, 

t

XP must be satisfied

before issuing the REFRESH command. Second, 

t

XPDLL must be satisfied before the

next power-down may be entered. An example is shown in Figure 108 (page 194).

Table 82: Power-Down Modes

DRAM State

MR0[12]

DLL State

Power-

Down Exit

Relevant Parameters

Active (any bank open)

“Don’t Care”

On

Fast

t

XP to any other valid command

Precharged
(all banks precharged)

1

On

Fast

t

XP to any other valid command

0

Off

Slow

t

XPDLL to commands that require the DLL to be

locked (READ, RDAP, or ODT on);

t

XP to any other valid command

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 98: Active Power-Down Entry and Exit

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Exit power-down

mode

Don’t Care

Valid

Valid

Valid

t

CPDED

Valid

t

IS

t

IH

t

IH

t

IS

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

NOP

t

XP

t

CKE (MIN)

Indicates break
in time scale

t

PD

Figure 99: Precharge Power-Down (Fast-Exit Mode) Entry and Exit

CK

CK#

Command

NOP

NOP

NOP

NOP

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Exit power-down

mode

t

PD

Valid

t

CPDED

t

IS

t

IH

t

IS

T0

T1

T2

T3

T4

T5

Ta0

Ta1

NOP

Don’t Care

Indicates break
in time scale

t

XP

t

CKE (MIN)

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 100: Precharge Power-Down (Slow-Exit Mode) Entry and Exit

CK

CK#

Command

NOP

NOP

NOP

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Exit power-down

mode

t

PD

Valid

2

Valid

1

PRE

t

XPDLL

t

CPDED

t

IS

t

IH

t

IS

T0

T1

T2

T3

T4

Ta

Ta1

Tb

NOP

Don’t Care

Indicates break
in time scale

t

XP

t

CKE (MIN)

Notes:

1. Any valid command not requiring a locked DLL.
2. Any valid command requiring a locked DLL.

Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP)

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Ta9

Don’t Care

Transitioning Data

Ta10

Ta11

Ta12

NOP

Valid

READ/

RDAP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

CKE

t

CPDED

t

IS

t

PD

Power-down or

self refresh entry

Indicates break
in time scale

t

RDPDEN

DI

n + 3

DI

n + 1

DI

n + 2

DI

n

RL = AL + CL

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

DI

n + 6

DI

n + 7

DI

n+ 5

DI

n + 4

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 102: Power-Down Entry After WRITE

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

Tb2

Tb3

Tb4

NOP

WRITE

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

CKE

t

CPDED

Power-down or

self refresh entry

1

Don’t Care

Transitioning Data

t

WRPDEN

DI

n + 3

DI

n + 1

DI

n + 2

DI

n

t

PD

Indicates break
in time scale

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

DI

 n + 6

DI

 n + 7

DI

 n + 5

DI

 n + 4

t

IS

WL = AL + CWL

t

WR

Note:

1. CKE can go LOW 2

t

CK earlier if BC4MRS.

Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP)

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

Don’t Care

Transitioning Data

Tb2

Tb3

Tb4

NOP

WRAP

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

A10

CKE

t

PD

t

WRAPDEN

Power-down or

self refresh entry

2

Start internal

precharge

t

CPDED

t

IS

Indicates break
in time scale

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

n

DI

 n + 6

DI

 n + 7

DI

 n + 5

DI

 n + 4

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

WR

1

WL = AL + CWL

Notes:

1.

t

WR is programmed through MR0[11:9] and represents 

t

WRmin (ns)/

t

CK rounded up to

the next integer 

t

CK.

2. CKE can go LOW 2

t

CK earlier if BC4MRS.

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 104: REFRESH to Power-Down Entry

CK

CK#

Command

REFRESH

NOP

NOP

NOP

NOP

Valid

CKE

t

CK

t

CH

t

CL

t

CPDED

t

REFPDEN

t

IS

T0

T1

T2

T3

Ta0

Ta1

Ta2

Tb0

t

XP (MIN)

t

RFC (MIN)

1

Don’t Care

Indicates break
in time scale

t

CKE (MIN)

t

PD

Note:

1. After CKE goes HIGH during 

t

RFC, CKE must remain HIGH until 

t

RFC is satisfied.

Figure 105: ACTIVATE to Power-Down Entry

CK

CK#

Command

Address

ACTIVE

NOP

NOP

CKE

t

CK

t

CH

t

CL

Don’t Care

t

CPDED

t

ACTPDEN

Valid

t

IS

T0

T1

T2

T3

T4

T5

T6

T7

t

PD

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 106: PRECHARGE to Power-Down Entry

CK

CK#

Command

Address

CKE

t

CK

t

CH

t

CL

Don’t Care

t

CPDED

t

PREPDEN

t

IS

T0

T1

T2

T3

T4

T5

T6

T7

t

PD

All/single

bank

PRE

NOP

NOP

Figure 107: MRS Command to Power-Down Entry

CK

CK#

CKE

t

CK

t

CH

t

CL

t

CPDED

Address

t

IS

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

t

PD

Don’t Care

Indicates break
in time scale

Valid

Command

MRS

NOP

NOP

NOP

NOP

NOP

t

MRSPDEN

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 108: Power-Down Exit to Refresh to Power-Down Entry

CK

CK#

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Enter power-down

mode

Exit power-down

mode

t

PD

t

CPDED

t

IS

t

IH

t

IS

T0

T1

T2

T3

T4

Ta0

Ta1

Tb0

Don’t Care

Indicates break
in time scale

Command

NOP

NOP

NOP

NOP

REFRESH

NOP

NOP

t

XP

1

t

XPDLL

2

Notes:

1.

t

XP must be satisfied before issuing the command.

2.

t

XPDLL must be satisfied (referenced to the registration of power-down exit) before the

next power-down can be entered.

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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RESET Operation

The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it
drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes
LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT
(R

TT

) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to

RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized
as though a normal power-up was executed. All counters, except refresh counters, on
the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET#
has gone LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

RESET Operation

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Figure 109: RESET Sequence

T = 10ns  (MIN)

T = 100ns (MIN)

T = 500μs (MIN)

t

XPR

t

MRD

t

MRD

t

MRD

t

MOD

t

CK

t

IOZ = 20ns

CKE

R

TT

BA[2:0]

All voltage
supplies valid
and stable

High-Z

DM

DQS

High-Z

Address

A10

CK

CK#

t

CL

Command

NOP

T0

Ta0

Don’t Care

t

CL

ODT

DQ

High-Z

Tb0

t

DLLK

MR1 with

DLL ENABLE

MRS

MRS

BA0 = H

BA1 = L
BA2 = L

BA0 = L
BA1 = L
BA2 = L

Code Code 

Code Code 

Valid

Valid

Valid

Valid

 Normal

operation

MR2

MR3

MRS

MRS

BA0 = L

BA1 = H

BA2 = L

BA0 = H
BA1 = H

BA2 = L

Code Code 

Code Code 

Tc0

Td0

RESET#

Stable and

valid clock

Valid

DRAM ready

for external

commands

T1

t

ZQinit

A10 = H

ZQCL

t

IS

Valid

System RESET

(warm boot)

ZQCAL

MR0 with

DLL RESET

Indicates break
in time scale

t

CKSRX

1

t

IS

t

IS

t

IS

Static LOW in case R

TT_Nom

 is enabled at time Ta0, otherwise static HIGH or LOW

Note:

1. The minimum time required is the longer of 10ns or 5 clocks.

4Gb: x4, x8, x16 DDR3L SDRAM

RESET Operation

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On-Die Termination (ODT)

On-die termination (ODT) is a feature that enables the DRAM to enable/disable and
turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8
configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is ap-
plied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 con-
figuration.

ODT is designed to improve signal integrity of the memory channel by enabling the
DRAM controller to independently turn on/off the DRAM’s internal termination resist-
ance for any grouping of DRAM devices. ODT is not supported during DLL disable
mode (simple functional representation shown below). The switch is enabled by the in-
ternal ODT control logic, which uses the external ODT ball and other control informa-
tion.

Figure 110: On-Die Termination

ODT

V

DDQ

/2

R

TT

Switch

DQ, DQS, DQS#, 
DM, TDQS, TDQS#

To other
circuitry
such as
RCV, 
. . . 

Functional Representation of ODT

The value of R

TT

 (ODT termination resistance value) is determined by the settings of

several mode register bits (see Table 88 (page 201)). The ODT ball is ignored while in
self refresh mode (must be turned off prior to self refresh entry) or if mode registers
MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and
dynamic ODT modes and either of these can function in synchronous or asynchronous
mode (when the DLL is off during precharge power-down or when the DLL is synchro-
nizing). Nominal ODT is the base termination and is used in any allowable ODT state.
Dynamic ODT is applied only during writes and provides OTF switching from no R

TT

 or

R

TT,nom

 to R

TT(WR)

.

The actual effective termination, R

TT(EFF)

, may be different from R

TT

 targeted due to

nonlinearity of the termination. For R

TT(EFF)

 values and calculations, see Table 33 (page

61).

Nominal ODT

ODT (NOM) is the base termination resistance for each applicable ball; it is enabled or
disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or
off via the ODT ball.

4Gb: x4, x8, x16 DDR3L SDRAM

On-Die Termination (ODT)

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Table 83: Truth Table – ODT (Nominal)

Note 1 applies to the entire table

MR1[9, 6, 2]

ODT Pin

DRAM Termination State

DRAM State

Notes

000

0

R

TT,nom

 disabled, ODT off

Any valid

2

000

1

R

TT,nom

 disabled, ODT on

Any valid except self refresh, read

3

000–101

0

R

TT,nom

 enabled, ODT off

Any valid

2

000–101

1

R

TT,nom

 enabled, ODT on

Any valid except self refresh, read

3

110 and 111

X

R

TT,nom

 reserved, ODT on or off

Illegal

 

Notes:

1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 199) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal

for it to be off during writes.

3. ODT must be disabled during reads. The R

TT,nom

 value is restricted during writes. Dynam-

ic ODT is applicable if enabled.

Nominal ODT resistance R

TT,nom

 is defined by MR1[9, 6, 2], as shown in Mode Register 1

(MR1) Definition. The R

TT,nom

 termination value applies to the output pins previously

mentioned. DDR3 SDRAM supports multiple R

TT,nom

 values based on RZQ/

n

 where 

n

can be 2, 4, 6, 8, or 12 and RZQ is 240

ȍ

. R

TT,nom

 termination is allowed any time after the

DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.

Write accesses use R

TT,nom

 if dynamic ODT (R

TT(WR)

) is disabled. If R

TT,nom

 is used dur-

ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 87 (page 200)). ODT
timings are summarized in Table 84 (page 198), as well as listed in the Electrical Char-
acteristics and AC Operating Conditions table.

Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 205).

Table 84: ODT Parameters

Symbol

Description

Begins at

Defined to

Definition for All

DDR3L Speed Bins

Unit

ODTLon

ODT synchronous turn-on delay

ODT registered HIGH

R

TT(ON)

 ±

t

AON

CWL + AL - 2

t

CK

ODTLoff

ODT synchronous turn-off delay

ODT registered HIGH

R

TT(OFF)

 ±

t

AOF

CWL + AL - 2

t

CK

t

AONPD

ODT asynchronous turn-on delay

ODT registered HIGH

R

TT(ON)

2–8.5

ns

t

AOFPD

ODT asynchronous turn-off delay

ODT registered HIGH

R

TT(OFF)

2–8.5

ns

ODTH4

ODT minimum HIGH time after ODT

assertion or write (BC4)

ODT registered HIGH

or write registration

with ODT HIGH

ODT registered

LOW

4

t

CK

t

CK

ODTH8

ODT minimum HIGH time after

write (BL8)

Write registration

with ODT HIGH

ODT registered

LOW

6

t

CK

t

CK

t

AON

ODT turn-on relative to ODTLon

completion

Completion of

ODTLon

R

TT(ON)

See Electrical Charac-

teristics and AC Oper-

ating Conditions table

ps

t

AOF

ODT turn-off relative to ODTLoff

completion

Completion of

ODTLoff

R

TT(OFF)

0.5

t

CK ± 0.2

t

CK

t

CK

4Gb: x4, x8, x16 DDR3L SDRAM

On-Die Termination (ODT)

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Dynamic ODT

In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT R

TT(WR)

) enabled, the DRAM switches from nominal ODT R

TT,nom

) to dy-

namic ODT R

TT(WR)

) when beginning a WRITE burst and subsequently switches back to

nominal ODT R

TT,nom

) at the completion of the WRITE burst. This requirement is sup-

ported by the dynamic ODT feature, as described below.

Dynamic ODT Special Use Case

When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special use case: the ODT ball can be wired high (via a current limiting resistor prefer-
red) by having R

TT,nom

 disabled via MR1 and R

TT(WR)

 enabled via MR2. This will allow

the ODT signal not to have to be routed yet the DRAM can provide ODT coverage dur-
ing write accesses.

When enabling this special use case, some standard ODT spec conditions may be viola-
ted: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not
LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this
would appear to be a problem since R

TT(WR)

 can not be used (should be disabled) and

R

TT(NOM)

 should be used. For Write leveling during this special use case, with the DLL

locked, then R

TT(NOM)

 maybe enabled when entering Write Leveling mode and disabled

when exiting Write Leveling mode. More so, R

TT(NOM)

 must be enabled when enabling

Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via
same MR1 load if R

TT(NOM)

 is to be used.

ODT will turn-on within a delay of ODTLon + 

t

AON + 

t

MOD + 1CK (enabling via MR1)

or turn-off within a delay of ODTLoff + 

t

AOF + 

t

MOD + 1CK. As seen in the table below,

between the Load Mode of MR1 and the previously specified delay, the value of ODT is
uncertain. this means the DQ ODT termination could turn-on and then turn-off again
during the period of stated uncertainty.

Table 85: Write Leveling with Dynamic ODT Special Case

Begin R

TT,nom

 Uncertainty

End R

TT,nom

 Uncertainty

I/Os

R

TT,nom

 Final State

MR1 load mode command:

Enable Write Leveling and R

TT(NOM)

ODTLon + 

t

AON + 

t

MOD + 1CK

DQS, DQS#

Drive R

TT,nom

 value

DQs

No R

TT,nom

MR1 load mode command:

Disable Write Leveling and R

TT(NOM)

ODTLoff + 

t

AOFF + 

t

MOD + 1CK

DQS, DQS#

No R

TT,nom

DQs

No R

TT,nom

Functional Description

The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic
ODT is not supported during DLL disable mode so R

TT(WR)

 must be disabled. The dy-

namic ODT function is described below:

• Two R

TT

 values are available—R

TT,nom

 and R

TT(WR)

.

– The value for R

TT,nom

 is preselected via MR1[9, 6, 2].

– The value for R

TT(WR)

 is preselected via MR2[10, 9].

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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• During DRAM operation without READ or WRITE commands, the termination is con-

trolled.

– Nominal termination strength R

TT,nom

 is used.

– Termination on/off timing is controlled via the ODT ball and latencies ODTLon and

ODTLoff.

• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,

and if dynamic ODT is enabled, the ODT termination is controlled.

– A latency of ODTLcnw after the WRITE command: termination strength R

TT,nom

switches to R

TT(WR)

– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)

after the WRITE command: termination strength R

TT(WR)

 switches back to R

TT,nom

.

– On/off termination timing is controlled via the ODT ball and determined by ODT-

Lon, ODTLoff, ODTH4, and ODTH8.

– During the 

t

ADC transition window, the value of R

TT

 is undefined.

ODT is constrained during writes and when dynamic ODT is enabled (see the table be-
low, Dynamic ODT Specific Parameters). ODT timings listed in the ODT Parameters ta-
ble in On-Die Termination (ODT) also apply to dynamic ODT mode.

Table 86: Dynamic ODT Specific Parameters

Symbol

Description

Begins at

Defined to

Definition for All

DDR3L Speed

Bins

Unit

ODTLcnw

Change from R

TT,nom

 to

R

TT(WR)

Write registration

R

TT

 switched from R

TT,nom

to R

TT(WR)

WL - 2

t

CK

ODTLcwn4

Change from R

TT(WR)

 to

R

TT,nom

 (BC4)

Write registration

R

TT

 switched from R

TT(WR)

to R

TT,nom

4

t

CK + ODTL off

t

CK

ODTLcwn8

Change from R

TT(WR)

 to

R

TT,nom

 (BL8)

Write registration

R

TT

 switched from R

TT(WR)

to R

TT,nom

6

t

CK + ODTL off

t

CK

t

ADC

R

TT

 change skew

ODTLcnw completed

R

TT

 transition complete

0.5

t

CK ± 0.2

t

CK

t

CK

Table 87: Mode Registers for R

TT,nom

MR1 (R

TT,nom

)

R

TT,nom

 (RZQ)

R

TT,nom

 (Ohm)

R

TT,nom

 Mode Restriction

M9

M6

M2

0

0

0

Off

Off

n/a

0

0

1

RZQ/4

60

Self refresh

0

1

0

RZQ/2

120

0

1

1

RZQ/6

40

1

0

0

RZQ/12

20

Self refresh, write

1

0

1

RZQ/8

30

1

1

0

Reserved

Reserved

n/a

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Table 87: Mode Registers for R

TT,nom

 (Continued)

MR1 (R

TT,nom

)

R

TT,nom

 (RZQ)

R

TT,nom

 (Ohm)

R

TT,nom

 Mode Restriction

M9

M6

M2

1

1

1

Reserved

Reserved

n/a

Note:

1. RZQ = 240

˖

. If R

TT,nom

 is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.

Table 88: Mode Registers for R

TT(WR)

MR2 (R

TT(WR)

)

R

TT(WR)

 (RZQ)

R

TT(WR)

 (Ohm)

M10

M9

0

0

Dynamic ODT off: WRITE does not affect R

TT,nom

0

1

RZQ/4

60

1

0

RZQ/2

120

1

1

Reserved

Reserved

Table 89: Timing Diagrams for Dynamic ODT

Figure and Page

Title

Figure 111 (page 202)

Dynamic ODT: ODT Asserted Before and After the WRITE, BC4

Figure 112 (page 202)

Dynamic ODT: Without WRITE Command

Figure 113 (page 203)

Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8

Figure 114 (page 204)

Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4

Figure 115 (page 204)

Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Figure 111: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLon

ODTLcwn4

ODTLcnw

WL

ODTLoff

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

Command

Address

R

TT

ODT

DQ 

DQS, DQS#

Valid

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Don’t Care

Transitioning

R

TT(WR)

R

TT,nom

R

TT,nom

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

ODTH4

ODTH4

t

AON (MIN)

t

ADC (MIN)

t

ADC (MIN)

t

AOF (MIN)

t

AON (MAX)

t

ADC (MAX)

t

ADC (MAX)

t

AOF (MAX)

Notes:

1. Via MRS or OTF. AL = 0, CWL = 5. R

TT,nom

 and R

TT(WR)

 are enabled.

2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,

ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).

Figure 112: Dynamic ODT: Without WRITE Command

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLoff 

T10

T11

CK

CK#

R

TT

Don’t Care

Transitioning

Command

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Address

DQS, DQS#

DQ

ODTH4

ODTLon

t

AON (MAX)

t

AON (MIN)

t

AOF (MIN)

t

AOF (MAX)

ODT

R

TT,nom

Notes:

1. AL = 0, CWL = 5. R

TT,nom

 is enabled and R

TT(WR)

 is either enabled or disabled.

2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT reg-

istered LOW at T5 is also legal.

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLcwn8

ODTLon

ODTLcnw

WL

t

AOF (MAX)

T10

T11

CK

CK#

Address

R

TT

ODT

DQ

DQS, DQS#

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

 b + 4

Valid

Don’t Care

Transitioning

Command

WRS8

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

R

TT(WR)

ODTH8

ODTLoff

t

ADC (MAX)

t

AON (MIN)

t

AOF (MIN)

Notes:

1. Via MRS or OTF; AL = 0, CWL = 5. If R

TT,nom

 can be either enabled or disabled, ODT can be HIGH. R

TT(WR)

 is enabled.

2. In this example, ODTH8 = 6 is satisfied exactly.

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLon

ODTLcnw

WL

T10

T11

CK

CK#

ODTLcwn4

DQS, DQS#

Address

Valid

Don’t Care

Transitioning

ODTLoff 

Command

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

DQ

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

t

ADC (MIN)

t

AOF (MIN)

t

AOF (MAX)

t

ADC (MAX)

t

ADC (MAX)

t

AON (MIN)

ODTH4

ODT

R

TT

R

TT(WR)

R

TT,nom

Notes:

1. Via MRS or OTF. AL = 0, CWL = 5. R

TT,nom

 and R

TT(WR)

 are enabled.

2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,

ODTH4 is satisfied. ODT registered LOW at T5 is also legal.

Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLon

ODTLcnw

WL

T10

T11

CK

CK#

ODTLcwn4

DQS, DQS#

Address

Valid

Command

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Don’t Care

Transitioning

DQ

DI

n

DI

n + 3

DI

n + 2

DI

n + 1

ODTH4

t

ADC (MAX)

t

AON (MIN)

t

AOF (MIN)

t

AOF (MAX)

ODTLoff 

R

TT

R

TT(WR)

ODT

Notes:

1. Via MRS or OTF. AL = 0, CWL = 5. R

TT,nom

 can be either enabled or disabled. If disabled,

ODT can remain HIGH. R

TT(WR)

 is enabled.

2. In this example ODTH4 = 4 is satisfied exactly.

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Synchronous ODT Mode

Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either R

TT,nom

 or R

TT(WR)

 is enabled. Based on the power-down definition, these

modes are:

• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled by MR0[12] during precharge power-

down

ODT Latency and Posted ODT

In synchronous ODT mode, R

TT

 turns on ODTLon clock cycles after ODT is sampled

HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by 

t

AON and 

t

AOF around

each clock edge (see Table 90 (page 206)). The ODT latency is tied to the WRITE latency
(WL) by ODTLon = WL - 2 and ODTLoff = WL - 2.

Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL),
the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal.
The device’s internal ODT signal is delayed a number of clock cycles defined by the AL
relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL +
AL - 2.

Timing Parameters

Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff,
ODTH4, ODTH8, 

t

AON, and 

t

AOF. The minimum R

TT

 turn-on time (

t

AON [MIN]) is the

point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi-
mum R

TT

 turn-on time (

t

AON [MAX]) is the point at which ODT resistance is fully on.

Both are measured relative to ODTLon. The minimum R

TT

 turn-off time (

t

AOF [MIN]) is

the point at which the device starts to turn off ODT resistance. The maximum R

TT

 turn

off time (

t

AOF [MAX]) is the point at which ODT has reached High-Z. Both are measured

from ODTLoff.

When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com-
mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 117 (page 207)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Synchronous ODT Mode

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Table 90: Synchronous ODT Parameters

Symbol

Description

Begins at

Defined to

Definition for All

DDR3L Speed Bins

Unit

ODTLon

ODT synchronous turn-on delay

ODT registered HIGH

R

TT(ON)

 ±

t

AON

CWL + AL - 2

t

CK

ODTLoff

ODT synchronous turn-off delay

ODT registered HIGH

R

TT(OFF)

 ±

t

AOF

CWL +AL - 2

t

CK

ODTH4

ODT minimum HIGH time after ODT
assertion or WRITE (BC4)

ODT registered HIGH or write regis-
tration with ODT HIGH

ODT registered LOW

4

t

CK

t

CK

ODTH8

ODT minimum HIGH time after WRITE
(BL8)

Write registration with ODT HIGH

ODT registered LOW

6

t

CK

t

CK

t

AON

ODT turn-on relative to ODTLon
completion

Completion of ODTLon

R

TT(ON)

See Electrical Charac-

teristics and AC Oper-

ating Conditions ta-

ble

ps

t

AOF

ODT turn-off relative to ODTLoff
completion

Completion of ODTLoff

R

TT(OFF)

0.5

t

CK ± 0.2

t

CK

t

CK

Figure 116: Synchronous ODT

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CWL - 2

AL = 3

AL = 3

t

AON (MAX)

t

AOF (MAX)

T10

T11

T12

T13

T14

T15

CK

CK#

R

TT

ODT

Don’t Care

Transitioning

R

TT,nom

CKE

t

AOF (MIN)

ODTLoff = CWL + AL - 2

ODTLon = CWL + AL - 2

ODTH4 (MIN)

t

AON (MIN)

Note:

1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. R

TT,nom

 is enabled.

4Gb: x4, x8, x16 DDR3L SDRAM

Synchr

onous ODT Mode

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Figure 117: Synchronous ODT (BC4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

AOF (MAX)

t

AOF (MIN)

t

AON (MAX)

t

AOF (MAX)

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

R

TT

CKE

NOP

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Command

Don’t Care

Transitioning

t

AON (MIN)

R

TT,nom

ODTLoff = WL - 2

ODTH4 (MIN) 

ODTH4 

ODTLoff = WL - 2

ODTLon = WL - 2

t

AON (MIN)

t

AON (MAX)

ODTH4 

ODTLon = WL - 2

t

AOF (MIN)

ODT

R

TT,nom

Notes:

1. WL = 7. R

TT,nom

 is enabled. R

TT(WR)

 is disabled.

2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the

WRITE command with ODT HIGH to ODT registered LOW.

5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must

also be satisfied from the registration of the WRITE command at T7.

4Gb: x4, x8, x16 DDR3L SDRAM

Synchr

onous ODT Mode

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ODT Off During READs

Because the device cannot terminate and drive at the same time, R

TT

 must be disabled

at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if
either R

TT,nom

 or R

TT(WR)

 is enabled). R

TT

 may not be enabled until the end of the post-

amble, as shown in the following example.

Note: 

ODT may be disabled earlier and enabled later than shown in Figure 118

(page 209).

4Gb: x4, x8, x16 DDR3L SDRAM

Synchronous ODT Mode

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Figure 118: ODT During READs

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

Valid

Address

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

DQ

DQS, DQS#

Don’t Care

Transitioning

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

READ

ODTLon = CWL + AL - 2

ODT

t

AON (MAX)

RL = AL + CL

ODTLoff = CWL + AL - 2

t

AOF (MIN)

R

TT

R

TT,nom

R

TT,nom

t

AOF (MAX)

Note:

1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL

+ CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8. R

TT,nom

 is enabled. R

TT(WR)

 is a “Don’t

Care.”

4Gb: x4, x8, x16 DDR3L SDRAM

Synchr

onous ODT Mode

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Asynchronous ODT Mode

Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when
either R

TT,nom

 or R

TT(WR)

 is enabled; however, the DLL is temporarily turned off in pre-

charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous-
ly when the DLL is synchronizing after being reset. See Power-Down Mode (page 187)
for definition and guidance over power-down details.

In asynchronous ODT timing mode, the internal ODT command is not delayed by AL
relative to the external ODT command. In asynchronous ODT mode, ODT controls R

TT

by analog time. The timing parameters 

t

AONPD and 

t

AOFPD replace ODTLon/

t

AON

and ODTLoff/

t

AOF, respectively, when ODT operates asynchronously.

The minimum R

TT

 turn-on time (

t

AONPD [MIN]) is the point at which the device termi-

nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum R

TT

 turn-

on time (

t

AONPD [MAX]) is the point at which ODT resistance is fully on. 

t

AONPD

(MIN) and 

t

AONPD (MAX) are measured from ODT being sampled HIGH.

The minimum R

TT

 turn-off time (

t

AOFPD [MIN]) is the point at which the device termi-

nation circuit starts to turn off ODT resistance. Maximum R

TT

 turn-off time (

t

AOFPD

[MAX]) is the point at which ODT has reached High-Z. 

t

AOFPD (MIN) and 

t

AOFPD

(MAX) are measured from ODT being sampled LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous ODT Mode

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Figure 119: Asynchronous ODT Timing with Fast ODT Transition

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

AONPD (MAX)

t

AOFPD (MAX)

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

R

TT

ODT

R

TT,nom

Don’t Care

Transitioning

CKE

t

IH

t

IS

t

IH

t

IS

t

AOFPD (MIN)

t

AONPD (MIN)

Note:

1. AL is ignored.

Table 91: Asynchronous ODT Timing Parameters for All Speed Bins

Symbol

Description

Min

Max

Unit

t

AONPD

Asynchronous R

TT

 turn-on delay (power-down with DLL off)

2

8.5

ns

t

AOFPD

Asynchronous R

TT

 turn-off delay (power-down with DLL off)

2

8.5

ns

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous ODT Mode

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Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)

There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period oc-
curs if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins 

t

ANPD prior to CKE first being registered LOW,

and ends when CKE is first registered LOW. 

t

ANPD is equal to the greater of ODTLoff +

1

t

CK or ODTLon + 1

t

CK. If a REFRESH command has been issued, and it is in progress

when CKE goes LOW, power-down entry ends 

t

RFC after the REFRESH command, rath-

er than when CKE is first registered LOW. Power-down entry then becomes the greater
of 

t

ANPD and 

t

RFC - REFRESH command to CKE registered LOW.

ODT assertion during power-down entry results in an R

TT

 change as early as the lesser

of 

t

AONPD (MIN) and ODTLon × 

t

CK + 

t

AON (MIN), or as late as the greater of 

t

AONPD

(MAX) and ODTLon × 

t

CK + 

t

AON (MAX). ODT de-assertion during power-down entry

can result in an R

TT

 change as early as the lesser of 

t

AOFPD (MIN) and ODTLoff × 

t

CK +

t

AOF (MIN), or as late as the greater of 

t

AOFPD (MAX) and ODTLoff × 

t

CK + 

t

AOF (MAX). 

Table 92 (page 213) summarizes these parameters.

If AL has a large value, the uncertainty of the state of R

TT

 becomes quite large. This is

because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL. 
Figure 120 (page 213) shows three different cases:

• ODT_A: Synchronous behavior before 

t

ANPD.

• ODT_B: ODT state changes during the transition period with 

t

AONPD (MIN) <

ODTLon × 

t

CK + 

t

AON (MIN) and 

t

AONPD (MAX) > ODTLon × 

t

CK + 

t

AON (MAX).

• ODT_C: ODT state changes after the transition period with asynchronous behavior.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous ODT Mode

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Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period

Description

Min

Max

Power-down entry transition period
(power-down entry)

Greater of: 

t

ANPD or 

t

RFC - refresh to CKE LOW

Power-down exit transition period
(power-down exit)

t

ANPD + 

t

XPDLL

ODT to R

TT

 turn-on delay

(ODTLon = WL - 2)

Lesser of: 

t

AONPD (MIN) (2ns) or

ODTLon × 

t

CK + 

t

AON (MIN)

Greater of: 

t

AONPD (MAX) (8.5ns) or

ODTLon × 

t

CK + 

t

AON (MAX)

ODT to R

TT

 turn-off delay

(ODTLoff = WL - 2)

Lesser of: 

t

AOFPD (MIN) (2ns) or

ODTLoff × 

t

CK + 

t

AOF (MIN)

Greater of: 

t

AOFPD (MAX) (8.5ns) or

ODTLoff × 

t

CK + 

t

AOF (MAX)

t

ANPD

WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)

Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

AOFPD (MAX)

ODTLoff

T10

T11

T12

T13

Ta0

Ta1

Ta3

Ta2

CK

CK#

DRAM R

TT

 B 

asynchronous 

or synchronous

R

TT,nom

DRAM R

TT

 C

asynchronous

R

TT,nom

Don’t Care

Transitioning

CKE

NOP

NOP

NOP

NOP

NOP

Command

NOP

REF

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

PDE transition period

Indicates break
in time scale

ODTLoff + 

t

AOFPD (MIN)

t

AOFPD (MAX)

t

AOFPD (MIN)

ODTLoff + 

t

AOFPD (MAX)

t

AOFPD (MIN)

t

ANPD

t

AOF (MIN)

t

AOF (MAX)

DRAM R

TT

 A 

synchronous

R

TT,nom

ODT A 

synchronous

ODT C 

asynchronous

ODT B 

asynchronous 

or synchronous

t

RFC (MIN)

Note:

1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous ODT Mode

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Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins

t

ANPD prior to CKE first being registered HIGH, and ends 

t

XPDLL after CKE is first reg-

istered HIGH. 

t

ANPD is equal to the greater of ODTLoff + 1

t

CK or ODTLon + 1

t

CK. The

transition period is 

t

ANPD + 

t

XPDLL.

ODT assertion during power-down exit results in an R

TT

 change as early as the lesser of

t

AONPD (MIN) and ODTLon × 

t

CK + 

t

AON (MIN), or as late as the greater of 

t

AONPD

(MAX) and ODTLon × 

t

CK + 

t

AON (MAX). ODT de-assertion during power-down exit

may result in an R

TT

 change as early as the lesser of 

t

AOFPD (MIN) and ODTLoff × 

t

CK +

t

AOF (MIN), or as late as the greater of 

t

AOFPD (MAX) and ODTLoff × 

t

CK + 

t

AOF (MAX). 

Table 92 (page 213) summarizes these parameters.

If AL has a large value, the uncertainty of the R

TT

 state becomes quite large. This is be-

cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL.  Figure
121 (page 215) sho
ws three different cases:

• ODT C: Asynchronous behavior before 

t

ANPD.

• ODT B: ODT state changes during the transition period, with 

t

AOFPD (MIN) < ODTL-

off × 

t

CK + 

t

AOF (MIN), and ODTLoff × 

t

CK + 

t

AOF (MAX) > 

t

AOFPD (MAX).

• ODT A: ODT state changes after the transition period with synchronous response.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

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Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb1

Tb2

Tc0

Tc1

Td0

Td1

Tc2

CK

CK#

Don’t Care

Transitioning

ODT C

synchronous

NOP

NOP

NOP

COMMAND

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

R

TT

 B

asynchronous

or synchronous

DRAM R

TT

 A

asynchronous

DRAM R

TT

 C

synchronous

R

TT,nom

NOP

NOP

ODT B

asynchronous

or synchronous

CKE

t

AOF (MIN)

R

TT,nom

Indicates break
in time scale

ODTLoff + 

t

AOF (MIN)

t

AOFPD (MAX)

ODTLoff + 

t

AOF (MAX)

t

XPDLL

t

AOF (MAX)

ODTLoff

ODT A

asynchronous

PDX transition period

t

AOFPD (MIN)

t

AOFPD (MAX)

R

TT,nom

t

ANPD

t

AOFPD (MIN)

Note:

1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous to Synchr

onous ODT Mode T

ransition (Power

-

Down Exit)

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Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)

If the time in the precharge power-down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods overlap. When
overlap occurs, the response of the DRAM’s R

TT

 to a change in the ODT state can be

synchronous or asynchronous from the start of the power-down entry transition period
to the end of the power-down exit transition period, even if the entry period ends later
than the exit period.

If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the re-
sponse of the DRAM’s R

TT

 to a change in the ODT state may be synchronous or asyn-

chronous from the start of power-down exit transition period to the end of the power-
down entry transition period.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

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Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Ta0

Ta1

Ta2

Ta3

Ta4

CK

CK#

CKE

Command

Don’t Care

Transitioning

t

XPDLL

t

RFC (MIN)

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

REF

NOP

NOP

NOP

NOP

PDE transition period

PDX transition period

Indicates break
in time scale

t

ANPD

Short CKE low transition period (R

TT

 change asynchronous or synchronous)

t

ANPD

Note:

1. AL = 0, WL = 5, 

t

ANPD = 4.

Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK

CK#

Command

Don’t Care

Transitioning

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

ANPD

t

XPDLL

Indicates break
in time scale

Ta0

Ta1

Ta2

Ta3

Ta4

CKE

t

ANPD

Short CKE HIGH transition period (R

TT

 change asynchronous or synchonous)

Note:

1. AL = 0, WL = 5, 

t

ANPD = 4.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous to Synchr

onous ODT Mode T

ransition (Power

-

Down Exit)

09005aef85af8fa8

4Gb_DDR3L.pdf - Rev

. R 09/18 EN

217

Micron T

echnology

, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron T

echnology

, Inc. All rights reserved.

datasheets/MT41K256M16TW-html.html

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

218

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DDR3L SDRAM

MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM
(Die Rev :E) data sheet specifications when running in
1.5V compatible mode.

Features

• V

DD

 = V

DDQ

 = 1.35V (1.283–1.45V)

• Backward compatible to V

DD

 = V

DDQ

 = 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe
• 8

n

-bit prefetch architecture

• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T

of 105°C

– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
– 16ms, 8192-cycle refresh at >95°C to 105°C

• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration

Options

Marking

• Configuration

 

– 1 Gig x 4

1G4

– 512 Meg x 8

512M8

– 256 Meg x 16

256M16

• FBGA package (Pb-free) – x4, x8

 

– 78-ball (9mm x 10.5mm) Rev. E

RH

– 78-ball (7.5mm x 10.6mm) Rev. N

RG

– 78-ball (8mm x 10.5mm) Rev. P

DA

• FBGA package (Pb-free) – x16

 

– 96-ball (9mm x 14mm) Rev. E

HA

– 96-ball (7.5mm x 13.5mm) Rev. N

LY

– 96-ball (8mm x 14mm) Rev. P

TW

• Timing – cycle time

 

– 938ps @ CL = 14 (DDR3-2133)

-093

– 1.07ns @ CL = 13 (DDR3-1866)

-107

– 1.25ns @ CL = 11 (DDR3-1600)

-125

• Operating temperature

– Commercial (0°C 

”

 T

C

 

”

 +95°C)

None

– Industrial (–40°C 

”

 T

C

 

”

 +95°C)

IT

– Automotive (–40°C 

”

 T

C

 

”

 +105°C)

AT

• Revision

:E/:N/:P

Table 1: Key Timing Parameters

Speed Grade

Data Rate (MT/s)

Target 

t

RCD-

t

RP-CL

t

RCD (ns)

t

RP (ns)

CL (ns)

-093

 1, 2

2133

14-14-14

13.09

13.09

13.09

-107

 1

1866

13-13-13

13.91

13.91

13.91

-125

1600

11-11-11

13.75

13.75

13.75

Notes:

1. Backward compatible to 1600, CL = 11 (-125).
2. Backward compatible to 1866, CL = 13 (-107).

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

1

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

MT41K256M16TW-html.html

Table 2: Addressing

Parameter

1 Gig x 4

512 Meg x 8

256 Meg x 16

Configuration

128 Meg x 4 x 8 banks

64 Meg x 8 x 8 banks

32 Meg x 16 x 8 banks

Refresh count

8K

8K

8K

Row address

64K (A[15:0])

64K (A[15:0])

32K (A[14:0])

Bank address

8 (BA[2:0])

8 (BA[2:0])

8 (BA[2:0])

Column address

2K (A[11, 9:0])

1K (A[9:0])

1K (A[9:0])

Page size

1KB

1KB

2KB

Figure 1: DDR3L Part Numbers

([DPSOH3DUW1XPEHU 07.0'$3

&RQILJXUDWLRQ
*LJ[
0HJ[
0HJ[

*

0
0

&RQILJXUDWLRQ

07.

3DFNDJH

6SHHG

5HYLVLRQ

5HYLVLRQ

(13

&RPPHUFLDO

,QGXVWULDOWHPSHUDWXUH

^

1RQH

,7

$XWRPRWLYHWHPSHUDWXUH

$7

3DFNDJH

EDOOPP[PP)%*$

0DUN

+$

5HY

(

EDOOPP[PP)%*$

5+

(

6SHHG*UDGH

W

&. QV&/

W

&. QV&/

7HPSHUDWXUH

EDOOPP[PP)%*$

3

'$

W

&. QV&/

EDOOPP[PP)%*$

EDOOPP[PP)%*$

1

1

5*

/<

EDOOPP[PP)%*$

3

7:

Note:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: 
http://www.micron.com.

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Contents

Important Notes and Warnings  .......................................................................................................................  11
State Diagram  ................................................................................................................................................  12
Functional Description ...................................................................................................................................  13

Industrial Temperature  ...............................................................................................................................  13
Automotive Temperature  
............................................................................................................................  13
General Notes  ............................................................................................................................................  14

Functional Block Diagrams  .............................................................................................................................  15
Ball Assignments and Descriptions  .................................................................................................................  17
Package Dimensions .......................................................................................................................................  23
Electrical Specifications  ..................................................................................................................................  29

Absolute Ratings .........................................................................................................................................  29
Input/Output Capacitance ..........................................................................................................................  30

Thermal Characteristics ..................................................................................................................................  31
Electrical Specifications – I

DD

 Specifications and Conditions ............................................................................  33

Electrical Characteristics – Operating I

DD

 Specifications  ..................................................................................  44

Electrical Specifications – DC and AC  ..............................................................................................................  49

DC Operating Conditions  ...........................................................................................................................  49
Input Operating Conditions  ........................................................................................................................  50
DDR3L 1.35V AC Overshoot/Undershoot Specification  ................................................................................  54
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals  ..............................................................  57
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals  .................................................................  59

ODT Characteristics  .......................................................................................................................................  60

1.35V ODT Resistors  ...................................................................................................................................  61
ODT Sensitivity  ..........................................................................................................................................  62
ODT Timing Definitions  
.............................................................................................................................  62

Output Driver Impedance ...............................................................................................................................  66

34 Ohm Output Driver Impedance  ..............................................................................................................  67
DDR3L 34 Ohm Driver  ................................................................................................................................   68
DDR3L 34 Ohm Output Driver Sensitivity  ....................................................................................................  69
DDR3L Alternative 40 Ohm Driver ...............................................................................................................  70
DDR3L 40 Ohm Output Driver Sensitivity  
....................................................................................................  70

Output Characteristics and Operating Conditions ............................................................................................  72

Reference Output Load  ...............................................................................................................................  75
Slew Rate Definitions for Single-Ended Output Signals 
.................................................................................  75
Slew Rate Definitions for Differential Output Signals ....................................................................................  77

Speed Bin Tables  ............................................................................................................................................  78
Electrical Characteristics and AC Operating Conditions  ...................................................................................  83
Command and Address Setup, Hold, and Derating .......................................................................................... 103
Data Setup, Hold, and Derating ...................................................................................................................... 110
Commands – Truth Tables  ............................................................................................................................. 118
Commands  ................................................................................................................................................... 121

DESELECT  ................................................................................................................................................ 121
NO OPERATION  
........................................................................................................................................ 121
ZQ CALIBRATION LONG  
........................................................................................................................... 121
ZQ CALIBRATION SHORT 
.......................................................................................................................... 121
ACTIVATE  
................................................................................................................................................. 121
READ  
........................................................................................................................................................ 121
WRITE  ...................................................................................................................................................... 122
PRECHARGE  ............................................................................................................................................. 123
REFRESH  
.................................................................................................................................................. 123

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

3

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SELF REFRESH .......................................................................................................................................... 124
DLL Disable Mode ..................................................................................................................................... 125

Input Clock Frequency Change  ...................................................................................................................... 129
Write Leveling  ............................................................................................................................................... 131

Write Leveling Procedure  ........................................................................................................................... 133
Write Leveling Mode Exit Procedure  ........................................................................................................... 135

Initialization  ................................................................................................................................................. 136
Voltage Initialization/Change  ........................................................................................................................ 138

V

DD

 Voltage Switching  ............................................................................................................................... 139

Mode Registers .............................................................................................................................................. 140
Mode Register 0 (MR0) ................................................................................................................................... 141

Burst Length  ............................................................................................................................................. 141
Burst Type  ................................................................................................................................................. 142
DLL RESET ................................................................................................................................................ 143
Write Recovery  .......................................................................................................................................... 144
Precharge Power-Down (Precharge PD)  
...................................................................................................... 144
CAS Latency (CL) 
....................................................................................................................................... 144

Mode Register 1 (MR1) ................................................................................................................................... 146

DLL Enable/DLL Disable  ........................................................................................................................... 146
Output Drive Strength  ............................................................................................................................... 147
OUTPUT ENABLE/DISABLE  
...................................................................................................................... 147
TDQS Enable 
............................................................................................................................................. 147
On-Die Termination  .................................................................................................................................. 148
WRITE LEVELING  
..................................................................................................................................... 148
POSTED CAS ADDITIVE Latency 
................................................................................................................ 148

Mode Register 2 (MR2) ................................................................................................................................... 149

CAS Write Latency (CWL) ........................................................................................................................... 150
AUTO SELF REFRESH (ASR) 
....................................................................................................................... 150
SELF REFRESH TEMPERATURE (SRT)
 ........................................................................................................ 150
SRT vs. ASR  ............................................................................................................................................... 151
DYNAMIC ODT  
......................................................................................................................................... 151

Mode Register 3 (MR3) ................................................................................................................................... 151

MULTIPURPOSE REGISTER (MPR)  ............................................................................................................ 152
MPR Functional Description ...................................................................................................................... 153
MPR Register Address Definitions and Bursting Order ................................................................................. 154
MPR Read Predefined Pattern  .................................................................................................................... 159

MODE REGISTER SET (MRS) Command  ........................................................................................................ 159
ZQ CALIBRATION Operation  ......................................................................................................................... 160
ACTIVATE Operation  ..................................................................................................................................... 161
READ Operation ............................................................................................................................................ 163
WRITE Operation  .......................................................................................................................................... 174

DQ Input Timing  ....................................................................................................................................... 182

PRECHARGE Operation  ................................................................................................................................. 184
SELF REFRESH Operation 
.............................................................................................................................. 184
Extended Temperature Usage  ........................................................................................................................ 186
Power-Down Mode ........................................................................................................................................ 187
RESET Operation ........................................................................................................................................... 195
On-Die Termination (ODT) ............................................................................................................................ 197

Functional Representation of ODT  ............................................................................................................. 197
Nominal ODT 
............................................................................................................................................ 197

Dynamic ODT  ............................................................................................................................................... 199

Dynamic ODT Special Use Case  ................................................................................................................. 199

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

4

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© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Functional Description .............................................................................................................................. 199

Synchronous ODT Mode ................................................................................................................................ 205

ODT Latency and Posted ODT .................................................................................................................... 205
Timing Parameters  
.................................................................................................................................... 205
ODT Off During READs .............................................................................................................................. 208

Asynchronous ODT Mode .............................................................................................................................. 210

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 212

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)  ........................................................ 214

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)  ...................................................... 216

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

5

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List of Figures

Figure 1:   DDR3L Part Numbers  ........................................................................................................................  2
Figure 2:   Simplified State Diagram  .................................................................................................................  12
Figure 3:   1 Gig x 4 Functional Block Diagram  ..................................................................................................  15
Figure 4:   512 Meg x 8 Functional Block Diagram  .............................................................................................  16
Figure 5:   256 Meg x 16 Functional Block Diagram  
...........................................................................................  16
Figure 6:   78-Ball FBGA – x4, x8 (Top View)  ......................................................................................................  17
Figure 7:   96-Ball FBGA – x16 (Top View)  .........................................................................................................  18
Figure 8:   78-Ball FBGA – x4, x8 (RH)  ...............................................................................................................  23
Figure 9:   78-Ball FBGA – x4, x8 (RG)  ...............................................................................................................  24
Figure 10:   78-Ball FBGA – x4, x8 (DA)  .............................................................................................................  25
Figure 11:   96-Ball FBGA – x16 (HA) .................................................................................................................  26
Figure 12:   96-Ball FBGA – x16 (LY) ..................................................................................................................  27
Figure 13:   96-Ball FBGA – x16 (TW) ................................................................................................................  28
Figure 14:   Thermal Measurement Point  .........................................................................................................  31
Figure 15:   DDR3L 1.35V Input Signal ..............................................................................................................  53
Figure 16:   Overshoot  .....................................................................................................................................  54
Figure 17:   Undershoot ...................................................................................................................................  55
Figure 18:   V

IX

 for Differential Signals  ..............................................................................................................  55

Figure 19:   Single-Ended Requirements for Differential Signals  ........................................................................  55
Figure 20:   Definition of Differential AC-Swing and 

t

DVAC ...............................................................................  56

Figure 21:   Nominal Slew Rate Definition for Single-Ended Input Signals ..........................................................  58
Figure 22:   DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# ..............  59
Figure 23:   ODT Levels and I-V Characteristics  ................................................................................................  60
Figure 24:   ODT Timing Reference Load  ..........................................................................................................  63
Figure 25:   

t

AON and 

t

AOF Definitions  ............................................................................................................  64

Figure 26:   

t

AONPD and 

t

AOFPD Definitions  ...................................................................................................  64

Figure 27:   

t

ADC Definition .............................................................................................................................  65

Figure 28:   Output Driver ................................................................................................................................   66
Figure 29:   DQ Output Signal  ..........................................................................................................................  73
Figure 30:   Differential Output Signal  ..............................................................................................................  74
Figure 31:   Reference Output Load for AC Timing and Output Slew Rate  ...........................................................  75
Figure 32:   Nominal Slew Rate Definition for Single-Ended Output Signals  .......................................................  76
Figure 33:   Nominal Differential Output Slew Rate Definition for DQS, DQS# ....................................................  77
Figure 34:   Nominal Slew Rate and 

t

VAC for 

t

IS (Command and Address – Clock)  ............................................. 106

Figure 35:   Nominal Slew Rate for 

t

IH (Command and Address – Clock) ........................................................... 107

Figure 36:   Tangent Line for 

t

IS (Command and Address – Clock)  .................................................................... 108

Figure 37:   Tangent Line for 

t

IH (Command and Address – Clock) .................................................................... 109

Figure 38:   Nominal Slew Rate and 

t

VAC for 

t

DS (DQ – Strobe) ......................................................................... 114

Figure 39:   Nominal Slew Rate for 

t

DH (DQ – Strobe)  ...................................................................................... 115

Figure 40:   Tangent Line for 

t

DS (DQ – Strobe)  ................................................................................................ 116

Figure 41:   Tangent Line for 

t

DH (DQ – Strobe)  ............................................................................................... 117

Figure 42:   Refresh Mode  ............................................................................................................................... 124
Figure 43:   DLL Enable Mode to DLL Disable Mode  ........................................................................................ 126
Figure 44:   DLL Disable Mode to DLL Enable Mode  ........................................................................................ 127
Figure 45:   DLL Disable 

t

DQSCK  .................................................................................................................... 128

Figure 46:   Change Frequency During Precharge Power-Down  ........................................................................ 130
Figure 47:   Write Leveling Concept ................................................................................................................. 131
Figure 48:   Write Leveling Sequence  ............................................................................................................... 134
Figure 49:   Write Leveling Exit Procedure  ....................................................................................................... 135
Figure 50:   Initialization Sequence  ................................................................................................................. 137

4Gb: x4, x8, x16 DDR3L SDRAM

Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Figure 51:   V

DD

 Voltage Switching  .................................................................................................................. 139

Figure 52:   MRS to MRS Command Timing (

t

MRD) ......................................................................................... 140

Figure 53:   MRS to nonMRS Command Timing (

t

MOD)  .................................................................................. 141

Figure 54:   Mode Register 0 (MR0) Definitions  ................................................................................................ 142
Figure 55:   READ Latency  .............................................................................................................................. 145
Figure 56:   Mode Register 1 (MR1) Definition  ................................................................................................. 146
Figure 57:   READ Latency (AL = 5, CL = 6)  ....................................................................................................... 149
Figure 58:   Mode Register 2 (MR2) Definition  
................................................................................................. 149
Figure 59:   CAS Write Latency  ........................................................................................................................ 150
Figure 60:   Mode Register 3 (MR3) Definition  ................................................................................................. 152
Figure 61:   Multipurpose Register (MPR) Block Diagram  ................................................................................. 153
Figure 62:   MPR System Read Calibration with BL8: Fixed Burst Order Single Readout  ..................................... 155
Figure 63:   MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 156
Figure 64:   MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble  .................................... 157
Figure 65:   MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble  .................................... 158
Figure 66:   ZQ CALIBRATION Timing (ZQCL and ZQCS)  ................................................................................. 160
Figure 67:   Example: Meeting 

t

RRD (MIN) and 

t

RCD (MIN)  ............................................................................. 161

Figure 68:   Example: 

t

FAW ............................................................................................................................. 162

Figure 69:   READ Latency  .............................................................................................................................. 163
Figure 70:   Consecutive READ Bursts (BL8)  .................................................................................................... 165
Figure 71:   Consecutive READ Bursts (BC4)  
.................................................................................................... 165
Figure 72:   Nonconsecutive READ Bursts  ....................................................................................................... 166
Figure 73:   READ (BL8) to WRITE (BL8)
  .......................................................................................................... 166
Figure 74:   READ (BC4) to WRITE (BC4) OTF  .................................................................................................. 167
Figure 75:   READ to PRECHARGE (BL8) 
.......................................................................................................... 167
Figure 76:   READ to PRECHARGE (BC4)  ......................................................................................................... 168
Figure 77:   READ to PRECHARGE (AL = 5, CL = 6)  
........................................................................................... 168
Figure 78:   READ with Auto Precharge (AL = 4, CL = 6) 
..................................................................................... 168
Figure 79:   Data Output Timing – 

t

DQSQ and Data Valid Window   .................................................................... 170

Figure 80:   Data Strobe Timing – READs  ......................................................................................................... 171
Figure 81:   Method for Calculating 

t

LZ and 

t

HZ ............................................................................................... 172

Figure 82:   

t

RPRE Timing  ............................................................................................................................... 172

Figure 83:   

t

RPST Timing  ............................................................................................................................... 173

Figure 84:   

t

WPRE Timing  .............................................................................................................................. 175

Figure 85:   

t

WPST Timing  .............................................................................................................................. 175

Figure 86:   WRITE Burst  ................................................................................................................................ 176
Figure 87:   Consecutive WRITE (BL8) to WRITE (BL8)   ..................................................................................... 177
Figure 88:   Consecutive WRITE (BC4) to WRITE (BC4) via OTF   
........................................................................ 177
Figure 89:   Nonconsecutive WRITE to WRITE   ................................................................................................. 178
Figure 90:   WRITE (BL8) to READ (BL8)
  .......................................................................................................... 178
Figure 91:   WRITE to READ (BC4 Mode Register Setting)  ................................................................................. 179
Figure 92:   WRITE (BC4 OTF) to READ (BC4 OTF)  ........................................................................................... 180
Figure 93:   WRITE (BL8) to PRECHARGE  ........................................................................................................ 181
Figure 94:   WRITE (BC4 Mode Register Setting) to PRECHARGE
  ...................................................................... 181
Figure 95:   WRITE (BC4 OTF) to PRECHARGE  ................................................................................................ 182
Figure 96:   Data Input Timing  ........................................................................................................................ 183
Figure 97:   Self Refresh Entry/Exit Timing  ...................................................................................................... 185
Figure 98:   Active Power-Down Entry and Exit  ................................................................................................ 189
Figure 99:   Precharge Power-Down (Fast-Exit Mode) Entry and Exit 
................................................................. 189
Figure 100:   Precharge Power-Down (Slow-Exit Mode) Entry and Exit  .............................................................. 190
Figure 101:   Power-Down Entry After READ or READ with Auto Precharge (RDAP)  
........................................... 190
Figure 102:   Power-Down Entry After WRITE  .................................................................................................. 191

4Gb: x4, x8, x16 DDR3L SDRAM

Description

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Figure 103:   Power-Down Entry After WRITE with Auto Precharge (WRAP)  ...................................................... 191
Figure 104:   REFRESH to Power-Down Entry  .................................................................................................. 192
Figure 105:   ACTIVATE to Power-Down Entry  
................................................................................................. 192
Figure 106:   PRECHARGE to Power-Down Entry  ............................................................................................. 193
Figure 107:   MRS Command to Power-Down Entry  
......................................................................................... 193
Figure 108:   Power-Down Exit to Refresh to Power-Down Entry  ....................................................................... 194
Figure 109:   RESET Sequence ......................................................................................................................... 196
Figure 110:   On-Die Termination  ................................................................................................................... 197
Figure 111:   Dynamic ODT: ODT Asserted Before and After the WRITE, BC4  .................................................... 202
Figure 112:   Dynamic ODT: Without WRITE Command 
  .................................................................................. 202
Figure 113:   Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8  ............ 203
Figure 114:   Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 204
Figure 115:   Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 
.......................... 204
Figure 116:   Synchronous ODT  ...................................................................................................................... 206
Figure 117:   Synchronous ODT (BC4)  ............................................................................................................. 207
Figure 118:   ODT During READs  .................................................................................................................... 209
Figure 119:   Asynchronous ODT Timing with Fast ODT Transition  .................................................................. 211
Figure 120:   Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off ) Entry  ............ 213
Figure 121:   Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off ) Exit ............... 215
Figure 122:   Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 217
Figure 123:   Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping  
................... 217

4Gb: x4, x8, x16 DDR3L SDRAM

Description

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List of Tables

Table 1:   Key Timing Parameters  .......................................................................................................................  1
Table 2:   Addressing  .........................................................................................................................................  2
Table 3:   78-Ball FBGA – x4, x8 Ball Descriptions  ..............................................................................................  19
Table 4:   96-Ball FBGA – x16 Ball Descriptions  .................................................................................................  21
Table 5:   Absolute Maximum Ratings  ..............................................................................................................  29
Table 6:   DDR3L Input/Output Capacitance  ....................................................................................................  30
Table 7:   Thermal Characteristics ....................................................................................................................  31
Table 8:   Thermal Impedance  .........................................................................................................................  32
Table 9:   Timing Parameters Used for I

DD

 Measurements – Clock Units  ............................................................  33

Table 10:   I

DD0

 Measurement Loop ..................................................................................................................  34

Table 11:   I

DD1

 Measurement Loop ..................................................................................................................  35

Table 12:   I

DD

 Measurement Conditions for Power-Down Currents ...................................................................  36

Table 13:   I

DD2N

 and I

DD3N

 Measurement Loop  ................................................................................................  37

Table 14:   I

DD2NT

 Measurement Loop  ..............................................................................................................  37

Table 15:   I

DD4R

 Measurement Loop  ................................................................................................................  38

Table 16:   I

DD4W

 Measurement Loop  ...............................................................................................................  39

Table 17:   I

DD5B

 Measurement Loop  ................................................................................................................  40

Table 18:   I

DD

 Measurement Conditions for I

DD6

, I

DD6ET

, and I

DD8

 ....................................................................  41

Table 19:   I

DD7

 Measurement Loop ..................................................................................................................  42

Table 20:   I

DD

 Maximum Limits Die Rev. E for 1.35/1.5V Operation ...................................................................  44

Table 21:   I

DD

 Maximum Limits Die Rev. N for 1.35V/1.5V Operation  ................................................................  45

Table 22:   I

DD

 Maximum Limits Die Rev. P for 1.35V/1.5V Operation .................................................................  47

Table 23:   DDR3L 1.35V DC Electrical Characteristics and Operating Conditions  ..............................................  49
Table 24:   DDR3L 1.35V DC Electrical Characteristics and Input Conditions  .....................................................  50
Table 25:   DDR3L 1.35V Input Switching Conditions – Command and Address  .................................................  51
Table 26:   DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) ..............................  52
Table 27:   DDR3L Control and Address Pins .....................................................................................................  54
Table 28:   DDR3L 1.35V Clock, Data, Strobe, and Mask Pins  
.............................................................................  54
Table 29:   DDR3L 1.35V – Minimum Required Time 

t

DVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...

 56

Table 30:   Single-Ended Input Slew Rate Definition ..........................................................................................  57
Table 31:   DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................  59
Table 32:   On-Die Termination DC Electrical Characteristics ............................................................................  60
Table 33:   1.35V R

TT

 Effective Impedance  ........................................................................................................  61

Table 34:   ODT Sensitivity Definition  ..............................................................................................................  62
Table 35:   ODT Temperature and Voltage Sensitivity
  ........................................................................................  62
Table 36:   ODT Timing Definitions ..................................................................................................................  63
Table 37:   DDR3L(1.35V) Reference Settings for ODT Timing Measurements  
....................................................  63
Table 38:   DDR3L 34 Ohm Driver Impedance Characteristics  ...........................................................................  67
Table 39:   DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations  ...........................................  68
Table 40:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.35V  .....................................  68

Table 41:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.45V  .....................................  68

Table 42:   DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.283  .....................................  69

Table 43:   DDR3L 34 Ohm Output Driver Sensitivity Definition  ........................................................................  69
Table 44:   DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity
  ..................................................  69
Table 45:   DDR3L 40 Ohm Driver Impedance Characteristics  ...........................................................................  70
Table 46:   DDR3L 40 Ohm Output Driver Sensitivity Definition  
........................................................................  70
Table 47:   40 Ohm Output Driver Voltage and Temperature Sensitivity ..............................................................  71
Table 48:   DDR3L Single-Ended Output Driver Characteristics  .........................................................................  72
Table 49:   DDR3L Differential Output Driver Characteristics  ............................................................................  73
Table 50:   DDR3L Differential Output Driver Characteristics V

OX(AC)

 .................................................................  74

4Gb: x4, x8, x16 DDR3L SDRAM

Description

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Table 51:   Single-Ended Output Slew Rate Definition  .......................................................................................  75
Table 52:   Differential Output Slew Rate Definition  ..........................................................................................  77
Table 53:   DDR3L-1066 Speed Bins ..................................................................................................................  78
Table 54:   DDR3L-1333 Speed Bins ..................................................................................................................  79
Table 55:   DDR3L-1600 Speed Bins ..................................................................................................................  80
Table 56:   DDR3L-1866 Speed Bins ..................................................................................................................  81
Table 57:   DDR3L-2133 Speed Bins ..................................................................................................................  82
Table 58:   Electrical Characteristics and AC Operating Conditions ....................................................................  83
Table 59:   Electrical Characteristics and AC Operating Conditions for Speed Extensions ....................................  93
Table 60:   DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based   ............... 103
Table 61:   DDR3L-800/1066 Derating Values 

t

IS/

t

IH – AC160/DC90-Based ....................................................... 104

Table 62:   DDR3L-800/1066/1333/1600 Derating Values for 

t

IS/

t

IH – AC135/DC90-Based  ................................ 104

Table 63:   DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based  ................................................ 104

Table 64:   DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL[AC]

) for Valid ADD/CMD Transition  . 105

Table 65:   DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based   ....................... 110
Table 66:   DDR3L Derating Values for 

t

DS/

t

DH – AC160/DC90-Based  .............................................................. 111

Table 67:   DDR3L Derating Values for 

t

DS/

t

DH – AC135/DC90-Based  .............................................................. 111

Table 68:   DDR3L Derating Values for 

t

DS/

t

DH – AC130/DC90-Based at 2V/ns ................................................. 112

Table 69:   DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL(AC)

) for Valid DQ Transition  ............. 113

Table 70:   Truth Table – Command ................................................................................................................. 118
Table 71:   Truth Table – CKE  .......................................................................................................................... 120
Table 72:   READ Command Summary  ............................................................................................................ 122
Table 73:   WRITE Command Summary  
.......................................................................................................... 122
Table 74:   READ Electrical Characteristics, DLL Disable Mode ......................................................................... 128
Table 75:   Write Leveling Matrix  ..................................................................................................................... 132
Table 76:   Burst Order .................................................................................................................................... 143
Table 77:   MPR Functional Description of MR3 Bits  ........................................................................................ 153
Table 78:   MPR Readouts and Burst Order Bit Mapping  ................................................................................... 154
Table 79:   Self Refresh Temperature and Auto Self Refresh Description  ............................................................ 186
Table 80:   Self Refresh Mode Summary  
........................................................................................................... 186
Table 81:   Command to Power-Down Entry Parameters  .................................................................................. 187
Table 82:   Power-Down Modes ....................................................................................................................... 188
Table 83:   Truth Table – ODT (Nominal)  ......................................................................................................... 198
Table 84:   ODT Parameters  
............................................................................................................................ 198
Table 85:   Write Leveling with Dynamic ODT Special Case  .............................................................................. 199
Table 86:   Dynamic ODT Specific Parameters  ................................................................................................. 200
Table 87:   Mode Registers for R

TT,nom

 ............................................................................................................. 200

Table 88:   Mode Registers for R

TT(WR)

 ............................................................................................................. 201

Table 89:   Timing Diagrams for Dynamic ODT ................................................................................................ 201
Table 90:   Synchronous ODT Parameters ........................................................................................................ 206
Table 91:   Asynchronous ODT Timing Parameters for All Speed Bins  ............................................................... 211
Table 92:   ODT Parameters for Power-Down (DLL Off ) Entry and Exit Transition Period  ................................... 213

4Gb: x4, x8, x16 DDR3L SDRAM

Description

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Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.

Automotive Applications.

 Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications.

 Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.

Customer Responsibility.

 Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.

Limited Warranty.

 In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

4Gb: x4, x8, x16 DDR3L SDRAM
Important Notes and Warnings

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION

Bank

active

Reading

Writing

Activating

Refreshing

Self

refresh

Idle

Active 

power-

down

ZQ

calibration

From any
state

Power
applied

Reset 

procedure

  Power 

on

Initial-

ization

MRS, MPR, 

write

leveling

Precharge

power-

down

Writing

Reading

Automatic
sequence

Command
sequence

Precharging

READ

READ

READ

READ AP

READ AP

READ AP

PRE, PREA

PRE,  PREA

PRE,  PREA

WRITE

WRITE

CKE L

CKE L

CKE L

WRITE

WRITE AP

WRITE AP

WRITE AP

PDE

PDE

PDX

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE

PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8 
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry

4Gb: x4, x8, x16 DDR3L SDRAM

State Diagram

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Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8

n

-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8

n

-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding 

n

-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-
mand, and address signals are registered at every positive edge of CK. Input data is reg-
istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-
erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad-
dress bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row pre-
charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T

is < 0°C or

>95°C.

Automotive Temperature

The Automotive temperature (AT) device requires that the case temperature not exceed
–40°C or 105°C. Micron specification requires the refresh rate to 4X when T

exceeds

95°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T

is < 0°C or

>95°C.

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.

• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[

n

:0]

. For example, 

1Gb: 

n

 = 12 (x16); 1Gb: 

n

 = 13 (x4,

x8); 2Gb: 

n

 = 13 (x16) and 2Gb: 

n

 = 14 (x4, x8); 4Gb: 

n

 = 14 (x16); and 4Gb: 

n

 = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1k

ȍ

* resistor.

– Connect UDQS# to V

DD

 via 1k

ȍ

* resistor.

– Connect UDM to V

DD

 via 1k

ȍ

* resistor.

– Connect DQ[15:8] individually to either V

SS

, V

DD

, or V

REF

 via 1k

ȍ

 resistors,* or float

DQ[15:8].

*If ODT is used, 1k

ȍ

 resistor should be changed to 4x that of the selected ODT.

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.

Figure 3: 1 Gig x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

16

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

11

Command 

decode

A[15:0]
BA[2:0]

16

Address
register

19

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(65,536 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank

control

logic

19

Bank 1

Bank 2

Bank 3

16

8

3

3

Refresh
counter

4

32

32

32

DQS, DQS#

Columns 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To pull-up/pull-down

networks

READ 

drivers

DQ[3:0]

READ

FIFO

and

data

MUX

Data

4

3

Bank 1

Bank 2

Bank 3

DM

DM

CK, CK#

DQS, DQS#

ZQ CAL

CS#

ZQ

RZQ

CK, CK#

RAS#

WE#

CAS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

OTF

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

 WRITE 

drivers

and 

input

logic

ODT

control

V

SSQ

A12

OTF

BC4

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Figure 4: 512 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

16

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

10

Command 

decode

A[15:0]
BA[2:0]

16

19

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(65,536  x 128 x 64)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank 

control

logic

19

Bank 1

Bank 2

Bank 3

16

7

3

3

Refresh
counter

8

64

64

64

DQS, DQS#

Columns 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read 

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

8

3

Bank 1

Bank 2

Bank 3

DM/TDQS
(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

ZQ

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT(WR)

R

TT,nom

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

BC4 (burst chop)

BC4

BC4

Write 

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128
x64)

ODT

control

Address
register

A12

V

SSQ

OTF

OTF

Figure 5: 256 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

13

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

10

Command 

decode

A[14:0]
BA[2:0]

15

Address
register

18

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

18

Bank 1

Bank 2

Bank 3

15

7

3

3

Refresh
counter

16

128

128

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ 

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

16

BC4 (burst chop)

3

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

ZQ

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

BC4

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

sw1

sw2

V

DDQ

/2

R

TT,nom

R

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

 WRITE 

drivers

and

input

logic

ODT

control

V

SSQ

A12

OTF

OTF

4Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

16

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© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1

2

3

4

6

7

8

9

5

V

SS

V

SS

V

DDQ

V

SSQ

V

REFDQ

NC

ODT

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SSQ

DQ2

NF, DQ6

V

DDQ

V

SS

V

DD

CS#

BA0

A3

A5

A7

RESET#

NC

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A0

A2

A9

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

V

DD

NF, DQ7

CK

CK#

A10/AP

A15

A12/BC#

A1

A11

A14

V

DD

V

DDQ

V

SSQ

V

SSQ

V

DDQ

NC

CKE

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SSQ

DQ3

V

SS

NF, DQ5

V

SS

V

DD

ZQ

V

REFCA

BA1

A4

A6

A8

A

B

C

D

E

F

G

H

J

K

L

M

N

Notes:

1. Ball descriptions listed in Table 3 (page 19) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

17

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© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Figure 7: 96-Ball FBGA – x16 (Top View)

1

2

3

4

6

7

8

9

5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

SS

V

DDQ

V

SSQ

V

REFDQ

NC

ODT

NC

V

SS

V

DD

V

SS

V

DD

V

SS

DQ13

V

DD

DQ11

V

DDQ

V

SSQ

DQ2

DQ6

V

DDQ

V

SS

V

DD

CS#

BA0

A3

A5

A7

RESET#

DQ15

V

SS

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

A0

A2

A9

A13

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

V

DD

DQ7

CK

CK#

A10/AP

NC

A12/BC#

A1

A11

A14

V

DDQ

DQ14

DQ10

V

SSQ

V

SSQ

DQ3

V

SS

DQ5

V

SS

V

DD

ZQ

V

REFCA

BA1

A4

A6

A8

V

SS

V

SSQ

V

DDQ

V

DD

V

DDQ

V

SSQ

V

SSQ

V

DDQ

NC

CKE

NC

V

SS

V

DD

V

SS

V

DD

V

SS

Notes:

1. Ball descriptions listed in Table 4 (page 21) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol

Type

Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input

Address inputs:

 Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 118).

BA[2:0]

Input

Bank address inputs:

 BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V

REFCA

.

CK, CK#

Input

Clock:

 CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock enable:

 CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/
disabled is dependent upon the DDR3 SDRAM configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-
bled during SELF REFRESH. CKE is referenced to V

REFCA

.

CS#

Input

Chip select:

 CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V

REFCA

.

DM

Input

Input data mask:

 DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT

Input

On-die termination:

 ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

.

RAS#, CAS#, WE#

Input

Command inputs:

 RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

.

RESET#

Input

Reset:

 RESET# is an active LOW CMOS input referenced to V

SS

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 

 0.8 × V

DD

 and

DC LOW 

 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol

Type

Description

DQ[3:0]

I/O

Data input/output:

 Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to V

REFDQ

.

DQ[7:0]

I/O

Data input/output:

 Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to V

REFDQ

.

DQS, DQS#

I/O

Data strobe:

 Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS#

Output

Termination data strobe: 

Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.

V

DD

Supply

Power supply:

 1.5V ±0.075V.

V

DDQ

Supply

DQ power supply:

 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

V

REFCA

Supply

Reference voltage for control, command, and address:

 V

REFCA

 must be

maintained at all times (including self refresh) for proper device operation.

V

REFDQ

Supply

Reference voltage for data:

 V

REFDQ

 must be maintained at all times (excluding self

refresh) for proper device operation.

V

SS

Supply

Ground.

V

SSQ

Supply

DQ ground:

 Isolated on the device for improved noise immunity.

ZQ

Reference

External reference ball for output drive calibration:

 This ball is tied to an

external 240

˖

 resistor (RZQ), which is tied to V

SSQ

.

NC

No connect:

 These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF

No function:

 When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

20

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© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol

Type

Description

A[14:13], A12/BC#,

A11, A10/AP, A[9:0]

Input

Address inputs: 

Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 118).

BA[2:0]

Input

Bank address inputs:

 BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to V

REFCA

.

CK, CK#

Input

Clock:

 CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE

Input

Clock enable:

 CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for power-
down entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to V

REFCA

.

CS#

Input

Chip select:

 CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V

REFCA

.

LDM

Input

Input data mask:

 LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

.

ODT

Input

On-die termination: 

ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to V

REFCA

.

RAS#, CAS#, WE#

Input

Command inputs:

 RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

.

RESET#

Input

Reset:

 RESET# is an active LOW CMOS input referenced to V

SS

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 

 0.8 × V

DD

 and

DC LOW 

 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

21

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© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)

Symbol

Type

Description

UDM

Input

Input data mask:

 UDM is an upper-byte, input mask signal for write data. Upper-

byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to V

REFDQ

.

DQ[7:0]

I/O

Data input/output:

 Lower byte of bidirectional data bus for the x16 configuration.

DQ[7:0] are referenced to V

REFDQ

.

DQ[15:8]

I/O

Data input/output:

 Upper byte of bidirectional data bus for the x16 configuration.

DQ[15:8] are referenced to V

REFDQ

.

LDQS, LDQS#

I/O

Lower byte data strobe:

 Output with read data. Edge-aligned with read data.

Input with write data. Center-aligned to write data.

UDQS, UDQS#

I/O

Upper byte data strobe:

 Output with read data. Edge-aligned with read data.

Input with write data. DQS is center-aligned to write data.

V

DD

Supply

Power supply:

 1.5V ±0.075V.

V

DDQ

Supply

DQ power supply:

 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

V

REFCA

Supply

Reference voltage for control, command, and address:

 V

REFCA

 must be

maintained at all times (including self refresh) for proper device operation.

V

REFDQ

Supply

Reference voltage for data:

 V

REFDQ

 must be maintained at all times (excluding self

refresh) for proper device operation.

V

SS

Supply

Ground.

V

SSQ

Supply

DQ ground:

 Isolated on the device for improved noise immunity.

ZQ

Reference

External reference ball for output drive calibration:

 This ball is tied to an

external 240

˖

 resistor (RZQ), which is tied to V

SSQ

.

NC

No connect:

 These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

22

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Package Dimensions

Figure 8: 78-Ball FBGA – x4, x8 (RH)

6.4 CTR

9 ±0.1

0.8 TYP

10.5 ±0.1

9.6 CTR

0.8 TYP

1.1 ±0.1

0.25 MIN

1

A

2

3

7

8

9

B

C

D

E

F

G

H

J

K

L

M

N

0.12 A

A

0.155

78X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.35 SMD
ball pads.

Seating plane

Ball A1 ID
(covered by SR)

Ball A1 ID

1.8 CTR

Nonconductive

overmold

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

23

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Figure 9: 78-Ball FBGA – x4, x8 (RG)

1.8 CTR

nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

A

0.25 MIN

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

9.6 CTR

10.6 ±0.1

78X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

24

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© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Figure 10: 78-Ball FBGA – x4, x8 (DA)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

0.29 MIN

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

9.6 CTR

10.5 ±0.1

78X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

A

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

25

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Figure 11: 96-Ball FBGA – x16 (HA)

Ball A1 Index

Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.

14 ±0.1

0.8 TYP

1.1 ±0.1

12 CTR

Ball A1 Index
(covered by SR)

0.8 TYP

9 ±0.1

0.25 MIN

6.4 CTR

96X Ø0.45

9 8 7 

3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

0.12 A

Seating plane

1.8 CTR

Nonconductive

overmold

0.155

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

26

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-html.html

Figure 12: 96-Ball FBGA – x16 (LY)

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

A

0.29 MIN

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

12 CTR

13.5 ±0.1

96X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42
SMD ball pads.

0.8 TYP

1.8 CTR

Nonconductive

overmold

0.155

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Notes:

1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

27

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Figure 13: 96-Ball FBGA – x16 (TW)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID
(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

12 CTR

14 ±0.1

96X Ø0.47

Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.

0.8 TYP

1

2

3

7

8

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

A

Notes:

1. All dimensions are in millimeters.
2. Material composition: Pb-free SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

4Gb: x4, x8, x16 DDR3L SDRAM

Package Dimensions

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Electrical Specifications

Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.

Table 5: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

V

DD

V

DD

 supply voltage relative to V

SS

–0.4

1.975

V

1

V

DDQ

V

DD

 supply voltage relative to V

SSQ

–0.4

1.975

V

 

V

IN

, V

OUT

Voltage on any pin relative to V

SS

–0.4

1.975

V

 

T

C

Operating case temperature – Commercial

0

95

°C

2, 3

Operating case temperature – Industrial

–40

95

°C

2, 3

Operating case temperature – Automotive

–40

105

°C

2, 3

T

STG

Storage temperature

–55

150

°C

 

Notes:

1. V

DD

 and V

DDQ

 must be within 300mV of each other at all times, and V

REF

 must not be

greater than 0.6 × V

DDQ

. When V

DD

 and V

DDQ

 are <500mV, V

REF

 can be 

300mV.

2. MAX operating case temperature. T

C

 is measured in the center of the package.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T

C

 dur-

ing operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications

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Input/Output Capacitance

Table 6: DDR3L Input/Output Capacitance

Note 1 applies to the entire table

Capacitance
Parameters

Sym

DDR3L

-800

DDR3L

-1066

DDR3L

-1333

DDR3L

-1600

DDR3L

-1866

DDR3L

-2133

Unit Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

CK and CK#

C

CK

0.8

1.6

0.8

1.6

0.8

1.4

0.8

1.4

0.8

1.3

0.8

1.3

pF

 

˂

C: CK to CK#

C

DCK

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

pF

 

Single-end
I/O: DQ, DM

C

IO

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1.4

2.1

pF

2

Differential
I/O: DQS,
DQS#, TDQS,
TDQS#

C

IO

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1.4

2.1

pF

3

˂

C: DQS to

DQS#, TDQS,
TDQS#

C

DDQS

0.0

0.2

0.0

0.2

0.0

0.15

0.0

0.15

0.0

0.15

0.0

0.15

pF

3

˂

C: DQ to

DQS

C

DIO

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

–0.5

0.3

pF

4

Inputs (CTRL,
CMD, ADDR)

C

I

0.75

1.3

0.75

1.3

0.75

1.3

0.75

1.2

0.75

1.2

0.75

1.2

pF

5

˂

C: CTRL to

CK

C

DI_CTRL

–0.5

0.3

–0.5

0.3

–0.4

0.2

–0.4

0.2

–0.4

0.2

–0.4

0.2

pF

6

˂

C:

CMD_ADDR
to CK

C

DI_CMD

_ADDR

–0.5

0.5

–0.5

0.5

–0.4

0.4

–0.4

0.4

–0.4

0.4

–0.4

0.4

pF

7

ZQ pin
capacitance

C

ZQ

3.0

3.0

3.0

3.0

3.0

3.0

pF

 

Reset pin
capacitance

C

RE

3.0

3.0

3.0

3.0

3.0

3.0

pF

 

Notes:

1. V

DD

 = 1.35V (1.283–1.45V), V

DDQ

 = V

DD

, V

REF

 = V

SS

= 100 MHz, T

= 25°C. V

OUT(DC)

 = 0.5

× V

DDQ

, V

OUT

 = 0.1V (peak-to-peak).

2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. C

DDQS

 is for DQS vs. DQS# and TDQS vs. TDQS# separately.

4. C

DIO

 = C

IO(DQ)

 - 0.5 × (C

IO(DQS)

 + C

IO(DQS#)

).

5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =

A[

n

:0], BA[2:0].

6. C

DI_CTRL

 = C

I(CTRL)

 - 0.5 × (C

CK(CK)

 + C

CK(CK#)

).

7. C

DI_CMD_ADDR

 = C

I(CMD_ADDR)

 - 0.5 × (C

CK(CK)

 + C

CK(CK#)

).

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications

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Thermal Characteristics

Table 7: Thermal Characteristics

Notes 1–3 apply to entire table

Parameter

Symbol

Value

Units

Notes

Operating temperature - Commercial

T

C

0 to 85

°C

Operating temperature - Industrial

T

C

-40 to 95

°C

4

Operating temperature - Automotive

T

C

-40 to105

°C

5

Notes:

1. MAX operating case temperature T

C

 is measured in the center of the package, as shown

below.

2. A thermal solution must be designed to ensure that the device does not exceed the

maximum T

C

 during operation.

3. Device functionality is not guaranteed if the device exceeds maximum T

C

 during

operation.

4. If T

C

 exceeds 85°C, but is less than 95°C, the DRAM must be refreshed manually at 2x re-

fresh, which is a 3.9μs interval refresh rate. The use of self refresh temperature (SRT) or
automatic self refresh (ASR), must be enabled.

5. If T

C

 exceeds 95°C, but less than 105°C, the DRAM must be refreshed manually at 4x re-

fresh, which is a 1.95μs interval refresh rate. The use of self refresh temperature (SRT) or
automatic self refresh (ASR), must be enabled.

Figure 14: Thermal Measurement Point

(L/2)

L

W

(W/2)

Tc test point

4Gb: x4, x8, x16 DDR3L SDRAM

Thermal Characteristics

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Table 8: Thermal Impedance

Die Rev.

Package

Substrate

ˆ

ˆ

 JA (°C/W)

Airflow =

0m/s

ˆ

 JA (°C/W)

Airflow =

1m/s

ˆ

 JA (°C/W)

Airflow =

2m/s

ˆ

 JB (°C/W)

ˆ

 JC (°C/W)

E

78-ball

Low conduc-

tivity

63.7

49.6

44.0

N/A

4.0

High con-

ductivity

42.3

35.7

32.9

29.7

N/A

96-ball

Low conduc-

tivity

50.4

39.2

35.1

N/A

3.9

High con-

ductivity

31.3

26.1

24.3

19.2

N/A

N

78-ball

Low conduc-

tivity

61.7

47.6

42.6

N/A

5.7

High con-

ductivity

40.6

33.4

31.2

19.1

N/A

96-ball

Low conduc-

tivity

52.1

42.1

38.4

N/A

5.6

High con-

ductivity

32.6

27.9

26.5

12.6

N/A

P

78-ball

Low conduc-

tivity

88.3

70.6

64.1

N/A

10.8

High con-

ductivity

56.5

48.4

45.7

25.5

N/A

96-ball

Low conduc-

tivity

54.3

42.1

37.3

N/A

4.6

High con-

ductivity

34.8

29.0

26.9

16.9

N/A

Note:

1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

4Gb: x4, x8, x16 DDR3L SDRAM

Thermal Characteristics

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Electrical Specifications – I

DD

 Specifications and Conditions

Within the following I

DD

 measurement tables, the following definitions and conditions

are used, unless stated otherwise:

• LOW: V

IN

 

”

 V

IL(AC)max

; HIGH: V

IN

 

•

 V

IH(AC)min

.

• Midlevel: Inputs are V

REF

 = V

DD

/2.

• R

ON

 set to RZQ/7 (34

ȍ

).

• R

TT,nom

 set to RZQ/6 (40

ȍ

).

• R

TT(WR)

 set to RZQ/2 (120

ȍ

).

• Q

OFF

 is enabled in MR1.

• ODT is enabled in MR1 (R

TT,nom

) and MR2 (R

TT(WR)

).

• TDQS is disabled in MR1.
• External DQ/DQS/DM load resistor is 25

ȍ

 to V

DDQ

/2.

• Burst lengths are BL8 fixed.
• AL equals 0 (except in I

DD7

).

• I

DD

 specifications are tested after the device is properly initialized.

• Input slew rate is specified by AC parametric test conditions.
• Optional ASR is disabled.
• Read burst type uses nibble sequential (MR0[3] = 0).
• Loop patterns must be executed at least once before current measurements begin.

Table 9: Timing Parameters Used for I

DD

 Measurements – Clock Units

I

DD

Parameter

DDR3L

-800

DDR3L

-1066

DDR3L

-1333

DDR3L

-1600

DDR3L

-1866

DDR3L

-2133

Unit

-25E

-25

-187E

-187

-15E

-15

-125E

-125

-107

-093

5-5-5

6-6-6

7-7-7

8-8-8

9-9-9

10-10-10 10-10-10 11-11-11 13-13-13 14-14-14

t

CK (MIN) I

DD

2.5

1.875

1.5

1.25

1.07

0.938

ns

CL I

DD

5

6

7

8

9

10

10

11

13

14

CK

t

RCD (MIN) I

DD

5

6

7

8

9

10

10

11

13

14

CK

t

RC (MIN) I

DD

20

21

27

28

33

34

38

39

45

50

CK

t

RAS (MIN) I

DD

15

15

20

20

24

24

28

28

32

36

CK

t

RP (MIN)

5

6

7

8

9

10

10

11

13

14

CK

t

FAW

x4, x8

16

16

20

20

20

20

24

24

26

27

CK

x16

20

20

27

27

30

30

32

32

33

38

CK

t

RRD

I

DD

x4, x8

4

4

4

4

4

4

5

5

5

6

CK

x16

4

4

6

6

5

5

6

6

6

7

CK

t

RFC

1Gb

44

44

59

59

74

74

88

88

103

118

CK

2Gb

64

64

86

86

107

107

128

128

150

172

CK

4Gb

104

104

139

139

174

174

208

208

243

279

CK

8Gb

140

140

187

187

234

234

280

280

328

375

CK

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 10: I

DD0

 Measurement Loop

CK, CK#

CKE

Sub-

Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D

1

0

0

0

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

0

0

4

D#

1

1

1

1

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RAS - 1; truncate if needed

n

RAS

PRE

0

0

1

0

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RC - 1; truncate if needed

n

RC

ACT

0

0

1

1

0

0

0

0

0

F

0

n

RC  +  1

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  2

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  3

D#

1

1

1

1

0

0

0

0

0

F

0

n

RC  +  4

D#

1

1

1

1

0

0

0

0

0

F

0

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC - 1 + 

n

RAS -1; truncate if needed

n

RC + 

n

RAS

PRE

0

0

1

0

0

0

0

0

0

F

0

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 2 × RC - 1; truncate if needed

1

2 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 1

2

4 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 2

3

6 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 3

4

8 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 4

5

10 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 5

6

12 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 6

7

14 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. Only selected bank (single) active.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 11: I

DD1

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

2

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D

1

0

0

0

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

0

0

4

D#

1

1

1

1

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RCD - 1; truncate if needed

n

RCD

RD

0

1

0

1

0

0

0

0

0

0

0

00000000

 

Repeat cycles 1 through 4 until 

n

RAS - 1; truncate if needed

n

RAS

PRE

0

0

1

0

0

0

0

0

0

0

0

 

Repeat cycles 1 through 4 until 

n

RC - 1; truncate if needed

n

RC

ACT

0

0

1

1

0

0

0

0

0

F

0

n

RC  +  1

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  2

D

1

0

0

0

0

0

0

0

0

F

0

n

RC  +  3

D#

1

1

1

1

0

0

0

0

0

F

0

n

RC  +  4

D#

1

1

1

1

0

0

0

0

0

F

0

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC + 

n

RCD - 1; truncate if needed

n

RC + 

n

RCD

RD

0

1

0

1

0

0

0

0

0

F

0

00110011

 Repeat 

cycles 

n

RC + 1 through 

n

RC + 4 until 

n

RC + 

n

RAS - 1; truncate if needed

n

RC + 

n

RAS

PRE

0

0

1

0

0

0

0

0

0

F

0

 Repeat 

cycle 

n

RC + 1 through 

n

RC + 4 until 2 × 

n

RC - 1; truncate if needed

1

2 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 1

2

4 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 2

3

6 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 3

4

8 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 4

5

10 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 5

6

12 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 6

7

14 × 

n

RC

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. Only selected bank (single) active.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 12: I

DD

 Measurement Conditions for Power-Down Currents

Name

I

DD2P0

 Precharge

Power-Down

Current (Slow Exit)

1

I

DD2P1

 Precharge

Power-Down

Current (Fast Exit)

1

I

DD2Q

 Precharge

Quiet

Standby Current

I

DD3P

 Active

Power-Down

Current

Timing pattern

N/A

N/A

N/A

N/A

CKE

LOW

LOW

HIGH

LOW

External clock

Toggling

Toggling

Toggling

Toggling

t

CK

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

CK (MIN) I

DD

t

RC

N/A

N/A

N/A

N/A

t

RAS

N/A

N/A

N/A

N/A

t

RCD

N/A

N/A

N/A

N/A

t

RRD

N/A

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

N/A

CL

N/A

N/A

N/A

N/A

AL

N/A

N/A

N/A

N/A

CS#

HIGH

HIGH

HIGH

HIGH

Command inputs

LOW

LOW

LOW

LOW

Row/column addr

LOW

LOW

LOW

LOW

Bank addresses

LOW

LOW

LOW

LOW

DM

LOW

LOW

LOW

LOW

Data I/O

Midlevel

Midlevel

Midlevel

Midlevel

Output buffer DQ, DQS

Enabled

Enabled

Enabled

Enabled

ODT

2

Enabled, off

Enabled, off

Enabled, off

Enabled, off

Burst length

8

8

8

8

Active banks

None

None

None

All

Idle banks

All

All

All

None

Special notes

N/A

N/A

N/A

N/A

Notes:

1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast

exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).

2. “Enabled, off” means the MR bits are enabled, but the signal is LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 13: I

DD2N

 and I

DD3N

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

D

1

0

0

0

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D#

1

1

1

1

0

0

0

0

0

F

0

3

D#

1

1

1

1

0

0

0

0

0

F

0

1

4–7

Repeat sub-loop 0, use BA[2:0] = 1

2

8–11

Repeat sub-loop 0, use BA[2:0] = 2

3

12–15

Repeat sub-loop 0, use BA[2:0] = 3

4

16–19

Repeat sub-loop 0, use BA[2:0] = 4

5

20–23

Repeat sub-loop 0, use BA[2:0] = 5

6

24–27

Repeat sub-loop 0, use BA[2:0] = 6

7

28–31

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed during I

DD2N

; all banks open during I

DD3N

.

Table 14: I

DD2NT

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

D

1

0

0

0

0

0

0

0

0

0

0

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D#

1

1

1

1

0

0

0

0

0

F

0

3

D#

1

1

1

1

0

0

0

0

0

F

0

1

4–7

Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0

2

8–11

Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1

3

12–15

Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1

4

16–19

Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0

5

20–23

Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0

6

24–27

Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1

7

28–31

Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 15: I

DD4R

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

0

0

RD

0

1

0

1

0

0

0

0

0

0

0

00000000

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D#

1

1

1

1

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

0

0

4

RD

0

1

0

1

0

0

0

0

0

F

0

00110011

5

D

1

0

0

0

0

0

0

0

0

F

0

6

D#

1

1

1

1

0

0

0

0

0

F

0

7

D#

1

1

1

1

0

0

0

0

0

F

0

1

8–15

Repeat sub-loop 0, use BA[2:0] = 1

2

16–23

Repeat sub-loop 0, use BA[2:0] = 2

3

24–31

Repeat sub-loop 0, use BA[2:0] = 3

4

32–39

Repeat sub-loop 0, use BA[2:0] = 4

5

40–47

Repeat sub-loop 0, use BA[2:0] = 5

6

48–55

Repeat sub-loop 0, use BA[2:0] = 6

7

56–63

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. All banks open.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 16: I

DD4W

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

4

T

oggling

Static HIGH

0

0

WR

0

1

0

0

1

0

0

0

0

0

0

00000000

1

D

1

0

0

0

1

0

0

0

0

0

0

2

D#

1

1

1

1

1

0

0

0

0

0

0

3

D#

1

1

1

1

1

0

0

0

0

0

0

4

WR

0

1

0

0

1

0

0

0

0

F

0

00110011

5

D

1

0

0

0

1

0

0

0

0

F

0

6

D#

1

1

1

1

1

0

0

0

0

F

0

7

D#

1

1

1

1

1

0

0

0

0

F

0

1

8–15

Repeat sub-loop 0, use BA[2:0] = 1

2

16–23

Repeat sub-loop 0, use BA[2:0] = 2

3

24–31

Repeat sub-loop 0, use BA[2:0] = 3

4

32–39

Repeat sub-loop 0, use BA[2:0] = 4

5

40–47

Repeat sub-loop 0, use BA[2:0] = 5

6

48–55

Repeat sub-loop 0, use BA[2:0] = 6

7

56–63

Repeat sub-loop 0, use BA[2:0] = 7

Notes:

1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the WR command.
4. All banks open.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 17: I

DD5B

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

T

oggling

Static HIGH

0

0

REF

0

0

0

1

0

0

0

0

0

0

0

1a

1

D

1

0

0

0

0

0

0

0

0

0

0

2

D

1

0

0

0

0

0

0

0

0

0

0

3

D#

1

1

1

1

0

0

0

0

0

F

0

4

D#

1

1

1

1

0

0

0

0

0

F

0

1b

5–8

Repeat sub-loop 1a, use BA[2:0] = 1

1c

9–12

Repeat sub-loop 1a, use BA[2:0] = 2

1d

13–16

Repeat sub-loop 1a, use BA[2:0] = 3

1e

17–20

Repeat sub-loop 1a, use BA[2:0] = 4

1f

21–24

Repeat sub-loop 1a, use BA[2:0] = 5

1g

25–28

Repeat sub-loop 1a, use BA[2:0] = 6

1h

29–32

Repeat sub-loop 1a, use BA[2:0] = 7

2

33–

n

RFC - 1

Repeat sub-loop 1a through 1h until 

n

RFC - 1; truncate if needed

Notes:

1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Table 18: I

DD

 Measurement Conditions for I

DD6

, I

DD6ET

, and I

DD8

I

DD

 Test

I

DD6

: Self Refresh Current

Normal Temperature Range

T

C

 = 0°C to +85°C

I

DD6ET

: Self Refresh Current

Extended Temperature Range

T

C

 = 0°C to +95°C

I

DD8

: Reset

2

CKE

LOW

LOW

Midlevel

External clock

Off, CK and CK# = LOW

Off, CK and CK# = LOW

Midlevel

t

CK

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

t

RAS

N/A

N/A

N/A

t

RCD

N/A

N/A

N/A

t

RRD

N/A

N/A

N/A

t

RC

N/A

N/A

N/A

CL

N/A

N/A

N/A

AL

N/A

N/A

N/A

CS#

Midlevel

Midlevel

Midlevel

Command inputs

Midlevel

Midlevel

Midlevel

Row/column addresses

Midlevel

Midlevel

Midlevel

Bank addresses

Midlevel

Midlevel

Midlevel

Data I/O

Midlevel

Midlevel

Midlevel

Output buffer DQ, DQS

Enabled

Enabled

Midlevel

ODT

1

Enabled, midlevel

Enabled, midlevel

Midlevel

Burst length

N/A

N/A

N/A

Active banks

N/A

N/A

None

Idle banks

N/A

N/A

All

SRT

Disabled (normal)

Enabled (extended)

N/A

ASR

Disabled

Disabled

N/A

Notes:

1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable

and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns + 

t

RFC.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 19: I

DD7

 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

0

0

ACT

0

0

1

1

0

0

0

0

0

0

0

1

RDA

0

1

0

1

0

0

0

1

0

0

0

00000000

2

D

1

0

0

0

0

0

0

0

0

0

0

3

Repeat cycle 2 until 

n

RRD - 1

1

n

RRD

ACT

0

0

1

1

0

1

0

0

0

F

0

n

RRD + 1

RDA

0

1

0

1

0

1

0

1

0

F

0

00110011

n

RRD + 2

D

1

0

0

0

0

1

0

0

0

F

0

n

RRD + 3

Repeat cycle 

n

RRD + 2 until 2 × 

n

RRD - 1

2

2 × 

n

RRD

Repeat sub-loop 0, use BA[2:0] = 2

3

3 × 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 3

4

4 × 

n

RRD

D

1

0

0

0

0

3

0

0

0

F

0

4 × 

n

RRD + 1

Repeat cycle 4 × 

n

RRD until 

n

FAW - 1, if needed

5

n

FAW

Repeat sub-loop 0, use BA[2:0] = 4

6

n

FAW + 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 5

7

n

FAW + 2 × 

n

RRD

Repeat sub-loop 0, use BA[2:0] = 6

8

n

FAW + 3 × 

n

RRD

Repeat sub-loop 1, use BA[2:0] = 7

9

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

7

0

0

0

F

0

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 

n

FAW + 4 × 

n

RRD until 2 × 

n

FAW - 1, if needed

10

2 × 

n

FAW

ACT

0

0

1

1

0

0

0

0

0

F

0

2 × 

n

FAW  +  1

RDA

0

1

0

1

0

0

0

1

0

F

0

00110011

2 × 

n

FAW  +  2

D

1

0

0

0

0

0

0

0

0

F

0

2 × 

n

FAW + 3

Repeat cycle 2 × 

n

FAW + 2 until 2 × 

n

FAW + 

n

RRD - 1

11

2 × 

n

FAW + 

n

RRD

ACT

0

0

1

1

0

1

0

0

0

0

0

2 × 

n

FAW + 

n

RRD + 1

RDA

0

1

0

1

0

1

0

1

0

0

0

00000000

2 × 

n

FAW + 

n

RRD + 2

D

1

0

0

0

0

1

0

0

0

0

0

2 × 

n

FAW + 

n

RRD + 3

Repeat cycle 2 × 

n

FAW + 

n

RRD + 2 until 2 × 

n

FAW + 2 × 

n

RRD - 1

12

2 × 

n

FAW + 2 × 

n

RRD

Repeat sub-loop 10, use BA[2:0] = 2

13

2 × 

n

FAW + 3 × 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 3

14

2 × 

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

3

0

0

0

0

0

2 × 

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 2 × 

n

FAW + 4 × 

n

RRD until 3 × 

n

FAW - 1, if needed

15

3 × 

n

FAW

Repeat sub-loop 10, use BA[2:0] = 4

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Table 19: I

DD7

 Measurement Loop (Continued)

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

3

T

oggling

Static HIGH

16

3 × 

n

FAW + 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 5

17

3 × 

n

FAW + 2 × 

n

RRD

Repeat sub-loop 10, use BA[2:0] = 6

18

3 × 

n

FAW + 3 × 

n

RRD

Repeat sub-loop 11, use BA[2:0] = 7

19

3 × 

n

FAW + 4 × 

n

RRD

D

1

0

0

0

0

7

0

0

0

0

0

3 × 

n

FAW + 4 × 

n

RRD + 1

Repeat cycle 3 × 

n

FAW + 4 × 

n

RRD until 4 × 

n

FAW - 1, if needed

Notes:

1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. AL = CL-1.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – I

DD

 Specifications and Conditions

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Electrical Characteristics – Operating I

DD

 Specifications

Table 20: I

DD

 Maximum Limits Die Rev. E for 1.35/1.5V Operation

Speed Bin

DDR3/3L

-1066

DDR3/3L

-1333

DDR3/3L

-1600

DDR3/3L

-1866

Units

Notes

Parameter

Symbol

Width

Operating current 0: One bank
ACTIVATE-to-PRECHARGE

I

DD0

x4, x8

44

47

55

62

mA

1, 2

x16

55

58

66

73

mA

1, 2

Operating current 1: One bank
ACTIVATE-to-READ-to-PRECHARGE

I

DD1

x4

53

57

61

65

mA

1, 2

x8

59

62

66

70

mA

1, 2

x16

80

84

87

91

mA

1, 2

Precharge power-down current:
Slow exit

I

DD2P0

All

18

18

18

18

mA

1, 2

Precharge power-down current:
Fast exit

I

DD2P1

All

26

28

32

37

mA

1, 2

Precharge quiet standby current

I

DD2Q

All

27

28

32

35

mA

1, 2

Precharge standby current

I

DD2N

All

28

29

32

35

mA

1, 2

Precharge standby ODT current

I

DD2NT

x4, x8

32

35

39

42

mA

1, 2

x16

35

39

42

45

mA

1, 2

Active power-down current

I

DD3P

All

32

35

38

41

mA

1, 2

Active standby current

I

DD3N

x4, x8

32

35

38

41

mA

1, 2

x16

41

45

47

49

mA

1, 2

Burst read operating current

I

DD4R

x4

113

130

147

164

mA

1, 2

x8

123

140

157

174

mA

1, 2

x16

185

202

235

252

mA

1, 2

Burst write operating current

I

DD4W

x4

87

103

118

133

mA

1, 2

x8

95

110

125

141

mA

1, 2

x16

137

152

171

190

mA

1, 2

Burst refresh current

I

DD5B

All

224

228

235

242

mA

1, 2

Room temperature self refresh

I

DD6

All

20

20

20

20

mA

1, 2, 3

Extended temperature self refresh

I

DD6ET

All

25

25

25

25

mA

2, 4

All banks interleaved read current

I

DD7

x4, x8

160

190

220

251

mA

1, 2

x16

198

217

243

274

mA

1, 2

Reset current

I

DD8

All

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

 T

C

 

 +85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

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5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

Table 21: I

DD

 Maximum Limits Die Rev. N for 1.35V/1.5V Operation

Speed Bin

DDR3/3L

-1066

DDR3/3L

-1333

DDR3/3L

-1600

DDR3/3L

-1866

DDR3/3L

-2133

Units

Notes

Parameter

Symbol Width

Operating current 0: One bank
ACTIVATE-to-PRECHARGE

I

DD0

x4, x8

42

45

47

49

51

mA

1, 2

x16

52

55

57

59

61

mA

1, 2

Operating current 1: One bank
ACTIVATE-to-READ-to-PRE-
CHARGE

I

DD1

x4

50

53

56

59

62

mA

1, 2

x8

55

58

61

64

67

mA

1, 2

x16

75

78

81

84

87

mA

1, 2

Precharge power-down cur-
rent: Slow exit

I

DD2P0

All

8

8

8

8

8

mA

1, 2

Precharge power-down cur-
rent: Fast exit

I

DD2P1

All

10

12

14

16

18

mA

1, 2

Precharge quiet standby cur-
rent

I

DD2Q

All

20

22

24

26

28

mA

1, 2

Precharge standby current

I

DD2N

All

20

22

24

26

28

mA

1, 2

Precharge standby ODT current

I

DD2NT

x4, x8

24

26

28

30

32

mA

1, 2

x16

27

29

31

33

35

mA

1, 2

Active power-down current

I

DD3P

All

22

24

26

28

30

mA

1, 2

Active standby current

I

DD3N

x4, x8

26

28

30

32

34

mA

1, 2

x16

34

36

38

40

42

mA

1, 2

Burst read operating current

I

DD4R

x4

65

75

85

95

105

mA

1, 2

x8

75

85

95

105

115

mA

1, 2

x16

135

145

155

165

175

mA

1, 2

Burst write operating current

I

DD4W

x4

65

75

85

95

105

mA

1, 2

x8

75

85

95

105

115

mA

1, 2

x16

135

145

155

165

175

mA

1, 2

Burst refresh current

I

DD5B

All

165

170

175

180

185

mA

1, 2

Room temperature self refresh

I

DD6

All

12

12

12

12

12

mA

1, 2, 3

Extended temperature self re-
fresh

I

DD6ET

All

16

16

16

16

16

mA

2, 4

All banks interleaved read cur-
rent

I

DD7

x4, x8

110

120

130

140

150

mA

1, 2

x16

170

180

190

200

210

mA

1, 2

Reset current

I

DD8

All

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

I

DD2P

 +

2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

09005aef85af8fa8
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5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

 T

C

 

 85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

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Table 22: I

DD

 Maximum Limits Die Rev. P for 1.35V/1.5V Operation

Speed Bin

DDR3/3L

-1600

DDR3/3L

-1866

DDR3/3L

-2133

Units

Notes

Parameter

Symbol

Width

Operating current 0: One bank ACTI-
VATE-to-PRECHARGE

I

DD0

x4, x8

28

29

31

mA

1, 2

X16

32

32

34

Operating current 1: One bank ACTI-
VATE-to-READ-to-PRECHARGE

I

DD1

x4, x8

43

44

47

mA

1, 2

x16

45

46

54

Precharge power-down current: Slow
exit

I

DD2P0

x4, x8

10

11

12

mA

1, 2

x16

12

12

12

Precharge power-down current: Fast
exit

I

DD2P1

x4, x8

11

11

13

mA

1, 2

x16

12

12

14

Precharge quiet standby current

I

DD2Q

ALL

15

15

17

mA

1, 2

Precharge standby current

I

DD2N

x4, x8

16

17

22

mA

1, 2

x16

17

17

22

Precharge standby ODT current

I

DD2NT

x4, x8

20

22

27

mA

1, 2

x16

22

23

28

Active power-down current

I

DD3P

x4,x8

15

15

17

mA

1, 2

x16

17

17

19

Active standby current

I

DD3N

x4, x8

20

21

23

mA

1, 2

x16

22

23

25

Burst read operating current

I

DD4R

x4, x8

90

90

110

mA

1, 2

x16

110

120

130

Burst write operating current

I

DD4W

x4, x8

90

90

110

mA

1, 2

16

120

130

140

Burst refresh current

I

DD5B

x4, x8

152

152

160

mA

1, 2

x16

156

156

160

Self refresh

I

DD6

ALL

15

15

15

mA

1, 2, 3

Extended temperature self refresh

I

DD6ET

ALL

23

23

23

mA

2, 4

All banks interleaved read current

I

DD7

x4, x8

130

146

150

mA

1, 2

x16

132

147

160

Reset current

I

DD8

All

I

DD2P

 + 2mA I

DD2P

 + 2mA I

DD2P

 + 2mA

mA

1, 2

Notes:

1. T

C

 = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase I

DD

x

 by up to an additional 2mA.

3. Restricted to T

(MAX) = 85°C.

4. T

C

 = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The I

DD

 values must be derated (increased) on IT-option devices when operated outside

of the range 0°C 

 T

C

 

 +85°C:

5a. When T

C

 < 0°C: I

DD2P0

, I

DD2P1

 and I

DD3P

 must be derated by 4%; I

DD4R

 and I

DD4W

 must

be derated by 2%; and I

DD6

, I

DD6ET

 and I

DD7

 must be derated by 7%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

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5b. When T

C

 > 85°C: I

DD0

, I

DD1

, I

DD2N

, I

DD2NT

, I

DD2Q

, I

DD3N

, I

DD3P

, I

DD4R

, I

DD4W

, and I

DD5B

must be derated by 2%; I

DD2Px

 must be derated by 30%.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics – Operating I

DD

 Specifications

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Electrical Specifications – DC and AC

DC Operating Conditions

Table 23: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Nom

Max

Unit

Notes

Supply voltage

V

DD

1.283

1.35

1.45

V

1–7

I/O supply voltage

V

DDQ

1.283

1.35

1.45

V

1–7

Input leakage current
Any input 0V 

 V

IN

 

 V

DD

, V

REF

 pin 0V 

 V

IN

 

 1.1V

(All other pins not under test = 0V)

I

I

–2

2

μA

 

V

REF

 supply leakage current

V

REFDQ

 = V

DD

/2 or V

REFCA

 = V

DD

/2

(All other pins not under test = 0V)

I

VREF

–1

1

μA

8, 9

Notes:

1. V

DD

 and V

DDQ

 must track one another. V

DDQ

 must be 

 V

DD

. V

SS

 = V

SSQ

.

2. V

DD

 and V

DDQ

 may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the

DC (0 Hz to 250 kHz) specifications. V

DD

 and V

DDQ

 must be at same level for valid AC

timing parameters.

3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average

of V

DD

/V

DDQ

(t) over a very long period of time (for example, 1 second).

4. Under these supply voltages, the device operates to this DDR3L specification.
5. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
6. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifi-

cations under the same speed timings as defined for this device.

7. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is

in reset while V

DD

 and V

DDQ

 are changed for DDR3 operation (see VDD Voltage Switch-

ing (page 139)).

8. The minimum limit requirement is for testing purposes. The leakage current on the V

REF

pin should be minimal.

9. V

REF

 (see Table 24).

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

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Input Operating Conditions

Table 24: DDR3L 1.35V DC Electrical Characteristics and Input Conditions

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Nom

Max

Unit

Notes

V

IN

 low; DC/commands/address busses

V

IL

V

SS

N/A

See Table 25

V

 

V

IN

 high; DC/commands/address busses

V

IH

See Table 25

N/A

V

DD

V

 

Input reference voltage command/address bus

V

REFCA(DC)

0.49 × V

DD

0.5 × V

DD

0.51 × V

DD

V

1, 2

I/O reference voltage DQ bus

V

REFDQ(DC)

0.49 × V

DD

0.5 × V

DD

0.51 × V

DD

V

2, 3

I/O reference voltage DQ bus in SELF REFRESH

V

REFDQ(SR)

V

SS

0.5 × V

DD

V

DD

V

4

Command/address termination voltage
(system level, not direct DRAM input)

V

TT

0.5 × V

DDQ

V

5

Notes:

1. V

REFCA(DC)

 is expected to be approximately 0.5 × V

DD

 and to track variations in the DC

level. Externally generated peak noise (non-common mode) on V

REFCA

 may not exceed

±1% × V

DD

 around the V

REFCA(DC)

 value. Peak-to-peak AC noise on V

REFCA

 should not ex-

ceed ±2% of V

REFCA(DC)

.

2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-

cations if the DRAM induces additional AC noise greater than 20 MHz in frequency.

3. V

REFDQ(DC)

 is expected to be approximately 0.5 × V

DD

 and to track variations in the DC

level. Externally generated peak noise (non-common mode) on V

REFDQ

 may not exceed

±1% × V

DD

 around the V

REFDQ(DC)

 value. Peak-to-peak AC noise on V

REFDQ

 should not ex-

ceed ±2% of V

REFDQ(DC)

.

4. V

REFDQ(DC)

 may transition to V

REFDQ(SR)

 and back to V

REFDQ(DC)

 when in SELF REFRESH,

within restrictions outlined in the SELF REFRESH section.

5. V

TT

 is not applied directly to the device. V

TT

 is a system supply for signal termination re-

sistors. Minimum and maximum values are system-dependent.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

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Table 25: DDR3L 1.35V Input Switching Conditions – Command and Address

Parameter/Condition

Symbol

DDR3L-800/1066

DDR3L-1333/1600

DDR3L-1866/2133

Units

Command and Address

Input high AC voltage: Logic 1

V

IH(AC160),min

5

160

160

mV

V

IH(AC135),min

5

135

135

135

mV

V

IH(AC125),min

5

125

mV

Input high DC voltage: Logic 1

V

IH(DC90),min

90

90

90

mV

Input low DC voltage: Logic 0

V

IL(DC90),min

–90

–90

–90

mV

Input low AC voltage: Logic 0

V

IL(AC125),min

5

–125

mV

V

IL(AC135),min

5

–135

–135

–135

mV

V

IL(AC160),min

5

–160

–160

mV

DQ and DM

Input high AC voltage: Logic 1

V

IH(AC160),min

5

160

160

mV

V

IH(AC135),min

5

135

135

135

mV

V

IH(AC125),min

5

130

mV

Input high DC voltage: Logic 1

V

IH(DC90),min

90

90

90

mV

Input low DC voltage: Logic 0

V

IL(DC90),min

–90

–90

–90

mV

Input low AC voltage: Logic 0

V

IL(AC125),min

5

–130

mV

V

IL(AC135),min

5

–135

–135

–135

mV

V

IL(AC160),min

5

–160

–160

mV

Notes:

1. All voltages are referenced to V

REF

. V

REF

 is V

REFCA

 for control, command, and address. All

slew rates and setup/hold times are specified at the DRAM ball. V

REF

 is V

REFDQ

 for DQ

and DM inputs.

2. Input setup timing parameters (

t

IS and 

t

DS) are referenced at V

IL(AC)

/V

IH(AC)

, not V

REF(DC)

.

3. Input hold timing parameters (

t

IH and 

t

DH) are referenced at V

IL(DC)

/V

IH(DC)

, not V

REF(DC)

.

4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is

900mV (peak-to-peak).

5. When two V

IH(AC)

 values (and two corresponding V

IL(AC)

 values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
V

IH(AC)

 value may be used for address/command inputs and the other V

IH(AC)

 value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC160),min

 and

V

IH(AC135),min

 (corresponding V

IL(AC160),min

 and V

IL(AC135),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC160),min

 with 

t

IS(AC160) of 210ps or V

IH(AC150),min

with 

t

IS(AC135) of 365ps; independently, the data inputs must use either V

IH(AC160),min

with 

t

DS(AC160) of 75ps or V

IH(AC150),min

 with 

t

DS(AC150) of 125ps.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

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Table 26: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#)

Parameter/Condition

Symbol

Min

Max

Units

Notes

Differential input logic high – slew

V

IH,diff(AC)slew

180

N/A

mV

4

Differential input logic low – slew

V

IL,diff(AC)slew

N/A

–180

mV

4

Differential input logic high

V

IH,diff(AC)

2 × (V

IH(AC)

 - V

REF

)

V

DD

/V

DDQ

mV

5

Differential input logic low

V

IL,diff(AC)

V

SS

/V

SSQ

2 × (V

IL(AC)

 - V

REF

)

mV

6

Differential input crossing voltage
relative to V

DD

/2 for DQS, DQS#; CK,

CK#

V

IX

V

REF(DC)

 - 150

V

REF(DC)

 + 150

mV

5, 7, 9

Differential input crossing voltage
relative to V

DD

/2 for CK, CK#

V

IX

 (175)

V

REF(DC)

 - 175

V

REF(DC)

 + 175

mV

5, 7–9

Single-ended high level for strobes

V

SEH

V

DDQ

/2 + 160

V

DDQ

mV

5

Single-ended high level for CK, CK#

V

DD

/2 + 160

V

DD

mV

5

Single-ended low level for strobes

V

SEL

V

SSQ

V

DDQ

/2 - 160

mV

6

Single-ended low level for CK, CK#

V

SS

V

DD

/2 - 160

mV

6

Notes:

1. Clock is referenced to V

DD

 and V

SS

. Data strobe is referenced to V

DDQ

 and V

SSQ

.

2. Reference is V

REFCA(DC)

 for clock and V

REFDQ(DC)

 for strobe.

3. Differential input slew rate = 2 V/ns.
4. Defines slew rate reference points, relative to input crossing voltages.
5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli-

cable.

6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap-

plicable.

7. The typical value of V

IX(AC)

 is expected to be about 0.5 × V

DD

 of the transmitting device,

and V

IX(AC)

 is expected to track variations in V

DD

. V

IX(AC)

 indicates the voltage at which

differential input signals must cross.

8. The V

IX

 extended range (±175mV) is allowed only for the clock; this V

IX

 extended range

is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing V

SEL

, V

SEH

 of at least V

DD

/2 ±250mV, and

the differential slew rate of CK, CK# is greater than 3 V/ns.

9. V

IX

 must provide 25mV (single-ended) of the voltages separation.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

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Figure 15: DDR3L 1.35V Input Signal

0.0V

V

REF

 - 90mV

V

REF

 = V

DD

/2

V

DD

  .51 x

V

IL(AC)

V

IL(DC)

V

REFDQ

 - AC noise

V

REFDQ

 - DC error

V

REFDQ

 + DC error

V

REFDQ

 + AC noise

V

IH(DC)

V

IH(AC)

V

DD

V

DD

 + 0.4V

Narrow pulse width

V

SS

 - 0.40V

Narrow pulse width

V

DDQ

V

DDQ

 + 0.4V

Overshoot

V

SS

 - 0.40V

Undershoot

V

SS

V

IL

 MIN(AC)

V

IL

 MIN(DC)

MAX 2% Total

DC MIN

V

REF

V

REF

 DC MAX

MAX 2% Total

V

IH

 MIN(DC)

V

IH

 MIN(AC)

Minimum V

IL

 and V

IH

 levels

V

IH(DC)

V

IH(AC)

V

IL(AC)

V

IL(DC)

V

IL

 and V

IH

 levels with ringback

V

REF

 DC MAX + 1%

V

REF

 DC MIN - 1% V

DD

V

REF

 + 90mV

V

REF

 + 125/135/160mV

V

REF

 - 125/135/160mV

V

DD

  .49 x

Note:

1. Numbers in diagrams reflect nominal values.

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DDR3L 1.35V AC Overshoot/Undershoot Specification

Table 27: DDR3L Control and Address Pins

Parameter

DDR3L-800

DRR3L-1066

DDR3L-1333

DDR3L-1600

DDR3L-1866

DDR3L-2133

Maximum peak ampli-
tude allowed for over-
shoot area
(see Figure 16)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum peak ampli-
tude allowed for under-
shoot area
(see Figure 17)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum overshoot area
above V

DD

 (see Figure 16)

0.67 V/ns

0.5 V/ns

0.4 V/ns

0.33 V/ns

0.28 V/ns

0.25 V/ns

Maximum undershoot
area below V

SS

 (see Fig-

ure 17)

0.67 V/ns

0.5 V/ns

0.4 V/ns

0.33 V/ns

0.28 V/ns

0.25 V/ns

Table 28: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins

Parameter

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

DDR3L-1866

DDR3L-2133

Maximum peak ampli-
tude allowed for over-
shoot area
(see Figure 16)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum peak ampli-
tude allowed for under-
shoot area
(see Figure 17)

0.4V

0.4V

0.4V

0.4V

0.4V

0.4V

Maximum overshoot area
above V

DD

/V

DDQ

 (see Fig-

ure 16)

0.25 V/ns

0.19 V/ns

0.15 V/ns

0.13 V/ns

0.11 V/ns

0.10 V/ns

Maximum undershoot
area below V

SS

/V

SSQ

 (see 

Figure 17)

0.25 V/ns

0.19 V/ns

0.15 V/ns

0.13 V/ns

0.11 V/ns

0.10 V/ns

Figure 16: Overshoot

Maximum amplitude

Overshoot area

V

DD

/V

DDQ

Time (ns)

Volts (V)

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Figure 17: Undershoot

Maximum amplitude

Undershoot area

V

SS

/V

SSQ

Time (ns)

Volts (V)

Figure 18: V

IX

 for Differential Signals

CK, DQS

V

DD

/2, V

DDQ

/2

V

DD

/2, V

DDQ

/2

V

IX

V

IX

CK#, DQS#

V

DD

, V

DDQ

CK, DQS

V

DD

, V

DDQ

V

SS

, V

SSQ

CK#, DQS#

V

SS

, V

SSQ

X

X

X

X

X

X

X

X

V

IX

V

IX

Figure 19: Single-Ended Requirements for Differential Signals

V

SS

 or V

SSQ

V

DD

 or V

DDQ

V

SEL,max

V

SEH,min

V

SEH

V

SEL

CK or DQS

V

DD

/2 or V

DDQ

/2

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Figure 20: Definition of Differential AC-Swing and 

t

DVAC

V

IH,diff(AC)min

0.0

V

IL,diff,max

tDVAC

V

IH,diff,min

V

IL,diff(AC)max

Half cycle

tDVAC

CK - CK#

DQS - DQS#

Table 29: DDR3L 1.35V – Minimum Required Time 

t

DVAC for CK/CK#, DQS/DQS# Differential for AC

Ringback

Slew Rate (V/ns)

DDR3L-800/1066/1333/1600

DDR3L-1866/2133

t

DVAC at

320mV (ps)

t

DVAC at

270mV (ps)

t

DVAC at

270mV (ps)

t

DVAC at

250mV (ps)

t

DVAC at

260mV (ps)

>4.0

189

201

163

168

176

4.0

189

201

163

168

176

3.0

162

179

140

147

154

2.0

109

134

95

105

111

1.8

91

119

80

91

97

1.6

69

100

62

74

78

1.4

40

76

37

52

55

1.2

Note 1

44

5

22

24

1.0

Note 1

<1.0

Note 1

Note:

1. Rising input signal shall become equal to or greater than V

IH(AC)

 level and Falling input

signal shall become equal to or less than V

IL(AC)

 level.

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DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals

Setup (

t

IS and 

t

DS) nominal slew rate for a rising signal is defined as the slew rate be-

tween the last crossing of V

REF

 and the first crossing of V

IH(AC)min

. Setup (

t

IS and 

t

DS)

nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V

REF

 and the first crossing of V

IL(AC)max

.

Hold (

t

IH and 

t

DH) nominal slew rate for a rising signal is defined as the slew rate be-

tween the last crossing of V

IL(DC)max

 and the first crossing of V

REF

. Hold (

t

IH and 

t

DH)

nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V

IH(DC)min

 and the first crossing of V

REF

 (see Figure 21 (page 58)).

Table 30: Single-Ended Input Slew Rate Definition

Input Slew Rates

(Linear Signals)

Measured

Calculation

Input

Edge

From

To

Setup

Rising

V

REF

V

IH(AC),min

V

IH(AC),min

 - V

REF

ǻ

TRS

se

Falling

V

REF

V

IL(AC),max

V

REF

 - V

IL(AC),max

ǻ

TFS

se

Hold

Rising

V

IL(DC),max

V

REF

V

REF

 - V

IL(DC),max

ǻ

TFH

se

Falling

V

IH(DC),min

V

REF

V

IH(DC),min

 - V

REF

ǻ

TRSH

se

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Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals

ǻ

TRS

se

ǻ

TFS

se

ǻ

TRH

se

ǻ

TFH

se

V

REFDQ

 or

V

REFCA

V

IH(AC)min

V

IH(DC)min

V

IL(AC)max

V

IL(DC)max

V

REFDQ

 or 

V

REFCA

V

IH(AC)min

V

IH(DC)min

V

IL(AC)max

V

IL(DC)max

Setup

Hold

Single-ended input voltage (DQ,  CMD,  ADDR)

Single-ended input voltage (DQ, CMD,  ADDR)

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DDR3L 1.35V Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and meas-
ured, as shown in Table 31 and Figure 22. The nominal slew rate for a rising signal is
defined as the slew rate between V

IL,diff,max

 and V

IH,diff,min

. The nominal slew rate for a

falling signal is defined as the slew rate between V

IH,diff,min

 and V

IL,diff,max

.

Table 31: DDR3L 1.35V Differential Input Slew Rate Definition

Differential Input

Slew Rates

(Linear Signals)

Measured

Calculation

Input

Edge

From

To

CK and
DQS
reference

Rising

V

IL,diff,max

V

IH,diff,min

V

IH,diff,min

 - V

IL,diff,max

ǻ

TR

diff

Falling

V

IH,diff,min

V

IL,diff,max

V

IH,diff,min

 - V

IL,diff,max

ǻ

TF

diff

Figure 22: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#

ǻ

TR

diff

ǻ

TF

diff

V

IH,diff,min

V

IL,diff,max

0

Dif

ferential input voltage (DQS, DQS#; CK, CK#)

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ODT Characteristics

The ODT effective resistance R

TT

 is defined by MR1[9, 6, and 2]. ODT is applied to the

DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values
and a functional representation are listed in Table 32 and Table 33 (page 61). The indi-
vidual pull-up and pull-down resistors (R

TT(PU)

 and R

TT(PD)

) are defined as follows:

R

TT(PU)

 = (

V

DDQ

 - 

V

OUT

)/|

I

OUT

|, under the condition that R

TT(PD)

 is turned off

R

TT(PD)

 = (

V

OUT

)/|

I

OUT

|, under the condition that R

TT(PU)

 is turned off

Figure 23: ODT Levels and I-V Characteristics

R

TT(PU)

R

TT(PD)

ODT

Chip in termination mode

V

DDQ

DQ

V

SSQ

I

OUT

 = I

PD

 - I

PU

I

PU

I

PD

I

OUT

V

OUT

To
other
circuitry
such as 
RCV, . . .

Table 32: On-Die Termination DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Nom

Max

Unit

Notes

R

TT

 effective impedance

R

TT(EFF)

See Table 33 (page 61)

1, 2

Deviation of VM with respect to
V

DDQ

/2

˂

VM

–5

 

5

%

1, 2, 3

Notes:

1. Tolerance limits are applicable after proper ZQ calibration has been performed at a

stable temperature and voltage (V

DDQ

 = V

DD

, V

SSQ

 = V

SS

). Refer to ODT Sensitivity (page

62) if either the temperature or voltage changes after calibration.

2. Measurement definition for R

TT

: Apply V

IH(AC)

 to pin under test and measure current

I[V

IH(AC)

], then apply V

IL(AC)

 to pin under test and measure current I[V

IL(AC)

]:

R

TT 

V

IH(AC)

 - V

IL(AC)

I(V

IH(AC)

) - I(V

IL(AC)

)

 

3. Measure voltage (VM) at the tested pin with no load:

ǻ

VM = 

– 1

2 × VM

V

DDQ

× 100

4. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (T

C

).

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1.35V ODT Resistors

Table 33 provides an overview of the ODT DC electrical characteristics. The values pro-
vided are not specification requirements; however, they can be used as design guide-
lines to indicate what R

TT

 is targeted to provide:

• R

TT

 120

ȍ

 is made up of R

TT120(PD240)

 and R

TT120(PU240)

• R

TT

 60

ȍ

 is made up of R

TT60(PD120)

 and R

TT60(PU120)

• R

TT

 40

ȍ

 is made up of R

TT40(PD80)

 and R

TT40(PU80)

• R

TT

 30

ȍ

 is made up of R

TT30(PD60)

 and R

TT30(PU60)

• R

TT

 20

ȍ

 is made up of R

TT20(PD40)

 and R

TT20(PU40)

Table 33: 1.35V R

TT

 Effective Impedance

MR1

[9, 6, 2]

R

TT

Resistor

V

OUT

Min

Nom

Max

Units

0, 1, 0



˖

R

TT,120PD240

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/1

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/1

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/1

R

TT,120PU240

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/1

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/1

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/1



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/2

0, 0, 1



˖

R

TT,60PD120

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/2

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/2

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/2

R

TT,60PU120

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/2

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/2

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/2



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/4

0, 1, 1



˖

R

TT,40PD80

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/3

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/3

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/3

R

TT,40PU80

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/3

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/3

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/3



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/6

1, 0, 1



˖

R

TT,30PD60

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/4

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/4

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/4

R

TT,30PU60

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/4

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/4

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/4



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/8

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Table 33: 1.35V R

TT

 Effective Impedance (Continued)

MR1

[9, 6, 2]

R

TT

Resistor

V

OUT

Min

Nom

Max

Units

1, 0, 0



˖

R

TT,20PD40

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/6

R

TT,20PU40

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/6



˖

V

IL(AC)

 to V

IH(AC)

0.9

1.0

1.65

RZQ/12

ODT Sensitivity

If either the temperature or voltage changes after I/O calibration, then the tolerance
limits listed in Table 32 and Table 33 can be expected to widen according to Table 34
and Table 35.

Table 34: ODT Sensitivity Definition

Symbol

Min

Max

Unit

R

TT

0.9 - dR

TT

dT × |DT| - dR

TT

dV × |DV|

1.6 + dR

TT

dT × |DT| + dR

TT

dV × |DV|

RZQ/(2, 4, 6, 8, 12)

Note:

1.

˂

T = T - T(@ calibration), 

˂

V = V

DDQ

 - V

DDQ

(@ calibration) and V

DD

 = V

DDQ

.

Table 35: ODT Temperature and Voltage Sensitivity

Change

Min

Max

Unit

dR

TT

dT

0

1.5

%/°C

dR

TT

dV

0

0.15

%/mV

Note:

1.

˂

T = T - T(@ calibration), 

˂

V = V

DDQ

 - V

DDQ

(@ calibration) and V

DD

 = V

DDQ

.

ODT Timing Definitions

ODT loading differs from that used in AC timing measurements. The reference load for
ODT timings is shown in Figure 24. Two parameters define when ODT turns on or off
synchronously, two define when ODT turns on or off asynchronously, and another de-
fines when ODT turns on or off dynamically. Table 36 and Table 37 (page 63) outline
and provide definition and measurement references settings for each parameter.

ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to
turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance
begins to turn off.

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Figure 24: ODT Timing Reference Load

Timing reference point

DQ, DM

DQS, DQS#

TDQS, TDQS#

DUT

V

REF

V

TT

 = V

SSQ

V

DDQ

/2

ZQ

RZQ = 240

ȍ

V

SSQ

 

R

TT

 = 25

ȍ

CK, CK#

Table 36: ODT Timing Definitions

Symbol

Begin Point Definition

End Point Definition

Figure

t

AON

Rising edge of CK – CK# defined by the end
point of ODTLon

Extrapolated point at V

SSQ

Figure 25 (page 64)

t

AOF

Rising edge of CK – CK# defined by the end
point of ODTLoff

Extrapolated point at V

RTT,nom

Figure 25 (page 64)

t

AONPD

Rising edge of CK – CK# with ODT first being
registered HIGH

Extrapolated point at V

SSQ

Figure 26 (page 64)

t

AOFPD

Rising edge of CK – CK# with ODT first being
registered LOW

Extrapolated point at V

RTT,nom

Figure 26 (page 64)

t

ADC

Rising edge of CK – CK# defined by the end
point of ODTLcnw, ODTLcwn4, or ODTLcwn8

Extrapolated points at V

RTT(WR)

 and

V

RTT,nom

Figure 27 (page 65)

Table 37: DDR3L(1.35V) Reference Settings for ODT Timing Measurements

Measured

Parameter

R

TT,nom

 Setting

R

TT(WR)

 Setting

V

SW1

V

SW2

t

AON

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

AOF

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

AONPD

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

AOFPD

RZQ/4 (60

˖

N/A

50mV

100mV

RZQ/12 (20

˖

N/A

100mV

200mV

t

ADC

RZQ/12 (20

˖

RZQ/2 (20

˖

200mV

250mV

4Gb: x4, x8, x16 DDR3L SDRAM

ODT Characteristics

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Figure 25: 

t

AON and 

t

AOF Definitions

CK

CK#

tAON

V

SSQ

DQ, DM

DQS, DQS#

TDQS, TDQS#

Begin point: Rising edge of CK - CK# 
defined by the end point of ODTLon

V

SW1

End point: Extrapolated point at V

SSQ

T

SW1

T

SW2

CK

CK#

V

DDQ

/2

tAOF

Begin point: Rising edge of CK - CK# 
defined by the end point of ODTLoff

End point: Extrapolated point at V

RTT,nom

V

RTT,nom

V

SSQ

tAON

tAOF

V

SW2

V

SW2

V

SW1

T

SW1

T

SW1

Figure 26: 

t

AONPD and 

t

AOFPD Definitions

CK

CK#

tAONPD

V

SSQ

DQ, DM 
DQS, DQS# 
TDQS, TDQS#

Begin point: Rising edge of CK - CK# 
with ODT first registered high

V

SW1

End point: Extrapolated point at V

SSQ

T

SW2

CK

CK#

V

DDQ

/2

tAOFPD

Begin point: Rising edge of CK - CK# 
with ODT first registered low

End point: Extrapolated point at V

RTT,nom

V

RTT,nom

V

SSQ

tAONPD

tAOFPD

T

SW1

T

SW2

T

SW1

V

SW2

V

SW2

V

SW1

4Gb: x4, x8, x16 DDR3L SDRAM

ODT Characteristics

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Figure 27: 

t

ADC Definition

CK

CK#

tADC

DQ, DM 
DQS, DQS# 
TDQS, TDQS#

End point: 
Extrapolated 
point at V

RTT,nom

T

SW21

tADC

End point: Extrapolated point at V

RTT(WR)

V

DDQ

/2

V

SSQ

V

RTT,nom

V

RTT(WR)

V

RTT,nom

Begin point: Rising edge of CK - CK# 
defined by the end point of ODTLcnw

Begin point: Rising edge of CK - CK# defined by 
the end point of ODTLcwn4 or ODTLcwn8

T

SW11

V

SW1

V

SW2

T

SW12

T

SW22

4Gb: x4, x8, x16 DDR3L SDRAM

ODT Characteristics

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Output Driver Impedance

The output driver impedance is selected by MR1[5,1] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is per-
formed. Output specifications refer to the default output driver unless specifically sta-
ted otherwise. A functional representation of the output buffer is shown below. The out-
put driver impedance R

ON

 is defined by the value of the external reference resistor RZQ

as follows:

R

ON,x

 = 

RZQ

/

y

 (with RZQ = 240

ȍ

 ±1%; 

= 34

ȍ

 or 40

ȍ

 with 

= 7 or 6, respectively)

The individual pull-up and pull-down resistors R

ON(PU)

 and R

ON(PD)

 are defined as fol-

lows:

R

ON(PU)

 = (

V

DDQ

 - 

V

OUT

)/|

I

OUT

|, when R

ON(PD)

 is turned off

R

ON(PD)

 = (

V

OUT

)/|

I

OUT

|, when R

ON(PU)

 is turned off

Figure 28: Output Driver

R

ON(PU)

R

ON(PD)

Output driver

To
other
circuitry
such as
RCV, . . .

Chip in drive mode

V

DDQ

V

SSQ

I

PU

I

PD

I

OUT

V

OUT

DQ

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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34 Ohm Output Driver Impedance

The 34

ȍ

 driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings

and specifications listed herein apply to the 34

ȍ

 driver only. Its impedance R

ON

 is de-

fined by the value of the external reference resistor RZQ as follows: R

ON34

 = RZQ/7 (with

nominal RZQ = 240

ȍ

 ±1%) and is actually 34.3

ȍ

 ±1%.

Table 38: DDR3L 34 Ohm Driver Impedance Characteristics

MR1

[5, 1]

R

ON

Resistor

V

OUT

Min

Nom

Max

Units

0, 1



˖

R

ON,34PD

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/7

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/7

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/7

R

ON,34PU

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/7

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/7

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/7

Pull-up/pull-down mismatch (MM

PUPD

)

V

IL(AC)

 to V

IH(AC)

–10

N/A

10

%

Notes:

1. Tolerance limits assume RZQ of 240

˖

±1% and are applicable after proper ZQ calibra-

tion has been performed at a stable temperature and voltage: 

V

DDQ

 = 

V

DD

V

SSQ

 = 

V

SS

).

Refer to DDR3L 34 Ohm Output Driver Sensitivity (page 69) if either the temperature
or the voltage changes after calibration.

2. Measurement definition for mismatch between pull-up and pull-down (MM

PUPD

). Meas-

ure both R

ON(PU)

 and R

ON(PD) 

at 0.5 × V

DDQ

:

MM

PUPD

 = 

 × 

100

R

ON(PU)

 - R

ON(PD)

R

ON,nom

3. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (T

C

).

A larger maximum limit will result in slightly lower minimum currents.

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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DDR3L 34 Ohm Driver

Using Table 39, the 34

ȍ

 driver’s current range has been calculated and summarized in 

Table 40 (page 68) V

DD

 = 1.35V, Table 41 for V

DD

 = 1.45V, and Table 42 (page 69) for

V

DD

 = 1.283V. The individual pull-up and pull-down resistors R

ON34(PD)

 and R

ON34(PU)

are defined as follows:

R

ON34(PD) 

= (

V

OUT

)/|

I

OUT

|; R

ON34(PU) 

is turned off

R

ON34(PU)

 = (

V

DDQ

 - 

V

OUT

)/|

I

OUT

|; R

ON34(PD)

 is turned off

Table 39: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations

R

ON

Min

Nom

Max

Unit

RZQ = 240

˖



237.6

240

242.4

˖

RZQ/7 = (240

˖



33.9

34.3

34.6

˖

MR1[5,1]

R

ON

Resistor

V

OUT

Min

Nom

Max

Unit

0, 1



˖

R

ON34(PD)

0.2 × V

DDQ

20.4

34.3

38.1

˖

0.5 × V

DDQ

30.5

34.3

38.1

˖

0.8 × V

DDQ

30.5

34.3

48.5

˖

R

ON34(PU)

0.2 × V

DDQ

30.5

34.3

48.5

˖

0.5 × V

DDQ

30.5

34.3

38.1

˖

0.8 × V

DDQ

20.4

34.3

38.1

˖

Table 40: DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.35V

MR1[5,1]

R

ON

Resistor

V

OUT

Max

Nom

Min

Unit

0, 1



˖

R

ON34(PD)

I

OL

 @ 0.2 × V

DDQ

13.3

7.9

7.1

mA

I

OL

 @ 0.5 × V

DDQ

22.1

19.7

17.7

mA

I

OL

 @ 0.8 × V

DDQ

35.4

31.5

22.3

mA

R

ON34(PU)

I

OH

 @ 0.2 × V

DDQ

35.4

31.5

22.3

mA

I

OH

 @ 0.5 × V

DDQ

22.1

19.7

17.7

mA

I

OH

 @ 0.8 × V

DDQ

13.3

7.9

7.1

mA

Table 41: DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.45V

MR1[5,1]

R

ON

Resistor

V

OUT

Max

Nom

Min

Unit

0, 1



˖

R

ON34(PD)

I

OL

 @ 0.2 × V

DDQ

14.2

8.5

7.6

mA

I

OL

 @ 0.5 × V

DDQ

23.7

21.1

19.0

mA

I

OL

 @ 0.8 × V

DDQ

38.0

33.8

23.9

mA

R

ON34(PU)

I

OH

 @ 0.2 × V

DDQ

38.0

33.8

23.9

mA

I

OH

 @ 0.5 × V

DDQ

23.7

21.1

19.0

mA

I

OH

 @ 0.8 × V

DDQ

14.2

8.5

7.6

mA

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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Table 42: DDR3L 34 Ohm Driver I

OH

/I

OL

 Characteristics: V

DD

 = V

DDQ

 = DDR3L@1.283

MR1[5,1]

R

ON

Resistor

V

OUT

Max

Nom

Min

Unit

0, 1



˖

R

ON34(PD)

I

OL

 @ 0.2 × V

DDQ

12.6

7.5

6.7

mA

I

OL

 @ 0.5 × V

DDQ

21.0

18.7

16.8

mA

I

OL

 @ 0.8 × V

DDQ

33.6

29.9

21.2

mA

R

ON34(PU)

I

OH

 @ 0.2 × V

DDQ

33.6

29.9

21.2

mA

I

OH

 @ 0.5 × V

DDQ

21.0

18.7

16.8

mA

I

OH

 @ 0.8 × V

DDQ

12.6

7.5

6.7

mA

DDR3L 34 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after ZQ calibration, then the tolerance
limits listed in Table 38 (page 67) can be expected to widen according to Table 43 and 
Table 44.

Table 43: DDR3L 34 Ohm Output Driver Sensitivity Definition

Symbol

Min

Max

Unit

R

ON(PD)

 @ 0.2 × V

DDQ

0.6 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.1 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/7

R

ON(PD)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/7

R

ON(PD)

 @ 0.8 × V

DDQ

0.9 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.4 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/7

R

ON(PU)

 @ 0.2 × V

DDQ

0.9 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.4 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/7

R

ON(PU)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/7

R

ON(PU)

 @ 0.8 × V

DDQ

0.6 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.1 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/7

Note:

1.

˂

T

 = 

T

 - 

T

(@CALIBRATION)



˂

V

 = 

V

DDQ

 - 

V

DDQ(@CALIBRATION)

; and 

V

DD

 = 

V

DDQ

.

Table 44: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity

Change

Min

Max

Unit

dR

ON

dTM

0

1.5

%/°C

dR

ON

dVM

0

0.13

%/mV

dR

ON

dTL

0

1.5

%/°C

dR

ON

dVL

0

0.13

%/mV

dR

ON

dTH

0

1.5

%/°C

dR

ON

dVH

0

0.13

%/mV

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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DDR3L Alternative 40 Ohm Driver

Table 45: DDR3L 40 Ohm Driver Impedance Characteristics

MR1

[5, 1]

R

ON

Resistor

V

OUT

Min

Nom

Max

Units

0, 0



˖

R

ON,40PD

0.2 × V

DDQ

0.6

1.0

1.15

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.9

1.0

1.45

RZQ/6

R

ON,40PU

0.2 × V

DDQ

0.9

1.0

1.45

RZQ/6

0.5 × V

DDQ

0.9

1.0

1.15

RZQ/6

0.8 × V

DDQ

0.6

1.0

1.15

RZQ/6

Pull-up/pull-down mismatch (MM

PUPD

)

V

IL(AC)

 to V

IH(AC)

–10

N/A

10

%

Notes:

1. Tolerance limits assume RZQ of 240

˖

±1% and are applicable after proper ZQ calibra-

tion has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

V

SSQ

 = 

V

SS

).

Refer to DDR3L 40 Ohm Output Driver Sensitivity (page 70) if either the temperature
or the voltage changes after calibration.

2. Measurement definition for mismatch between pull-up and pull-down (MM

PUPD

). Meas-

ure both R

ON(PU)

 and R

ON(PD)

 at 0.5 × V

DDQ

:

MM

PUPD

 = 

 × 

100

R

ON(PU)

 - R

ON(PD)

R

ON,nom

3. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (T

C

).

A larger maximum limit will result in slightly lower minimum currents.

DDR3L 40 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after I/O calibration, then the tolerance
limits listed in Table 45 can be expected to widen according to Table 46 and Table 47
(page 71).

Table 46: DDR3L 40 Ohm Output Driver Sensitivity Definition

Symbol

Min

Max

Unit

R

ON(PD)

 @ 0.2 × V

DDQ

0.6 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.1 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/6

R

ON(PD)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/6

R

ON(PD)

 @ 0.8 × V

DDQ

0.9 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.4 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/6

R

ON(PU)

 @ 0.2 × V

DDQ

0.9 - dR

ON

dTL × |

˂

T| - dR

ON

dVL × |

˂

V|

1.4 + dR

ON

dTL × |

˂

T| + dR

ON

dVL × |

˂

V|

RZQ/6

R

ON(PU)

 @ 0.5 × V

DDQ

0.9 - dR

ON

dTM × |

˂

T| - dR

ON

dVM × |

˂

V|

1.1 + dR

ON

dTM × |

˂

T| + dR

ON

dVM × |

˂

V|

RZQ/6

R

ON(PU)

 @ 0.8 × V

DDQ

0.6 - dR

ON

dTH × |

˂

T| - dR

ON

dVH × |

˂

V|

1.1 + dR

ON

dTH × |

˂

T| + dR

ON

dVH × |

˂

V|

RZQ/6

Note:

1.

˂

T

 = 

T

 - 

T

(@CALIBRATION)



˂

V

 = 

V

DDQ

 - 

V

DDQ(@CALIBRATION)

; and 

V

DD

 = 

V

DDQ

.

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity

Change

Min

Max

Unit

dR

ON

dTM

0

1.5

%/°C

dR

ON

dVM

0

0.15

%/mV

dR

ON

dTL

0

1.5

%/°C

dR

ON

dVL

0

0.15

%/mV

dR

ON

dTH

0

1.5

%/°C

dR

ON

dVH

0

0.15

%/mV

4Gb: x4, x8, x16 DDR3L SDRAM

Output Driver Impedance

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Output Characteristics and Operating Conditions

Table 48: DDR3L Single-Ended Output Driver Characteristics

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Output leakage current: DQ are disabled;
0V 

 V

OUT

 

 V

DDQ

; ODT is disabled; ODT is HIGH

I

OZ

–5

5

μA

1

Output slew rate: Single-ended; For rising and falling edges,
measure between V

OL(AC)

 = V

REF

 - 0.09 × V

DDQ

 and V

OH(AC)

 =

V

REF

 + 0.09 × V

DDQ

SRQ

se

1.75

6

V/ns

1, 2, 3, 4

Single-ended DC high-level output voltage

V

OH(DC)

0.8 × V

DDQ

V

1, 2, 5

Single-ended DC mid-point level output voltage

V

OM(DC)

0.5 × V

DDQ

V

1, 2, 5

Single-ended DC low-level output voltage

V

OL(DC)

0.2 × V

DDQ

V

1, 2, 5

Single-ended AC high-level output voltage

V

OH(AC)

V

TT

 + 0.1 × V

DDQ

V

1, 2, 3, 6

Single-ended AC low-level output voltage

V

OL(AC)

V

TT

 - 0.1 × V

DDQ

V

1, 2, 3, 6

Delta R

ON

 between pull-up and pull-down for DQ/DQS

MM

PUPD

–10

10

%

1, 7

Test load for AC timing and output slew rates

Output to V

TT

 (V

DDQ

/2) via 25

˖

 resistor

3

Notes:

1. RZQ of 240

˖

±1% with RZQ/7 enabled (default 34

˖

 driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

;

V

SSQ

 = 

V

SS

).

2.

V

TT

 = 

V

DDQ

/2.

3. See Figure 31 (page 75) for the test load configuration.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from

HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching in the opposite direction. For all other DQ signal switch-
ing combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.

5. See Figure 28 (page 66) for IV curve linearity. Do not use AC test load.
6. See Slew Rate Definitions for Single-Ended Output Signals (page 75) for output slew

rate.

7. See Figure 28 (page 66) for additional information.
8. See Figure 29 (page 73) for an example of a single-ended output signal.

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Figure 29: DQ Output Signal

V

OH(AC)

MIN output

MAX output

V

OL(AC)

 

Table 49: DDR3L Differential Output Driver Characteristics

All voltages are referenced to V

SS

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Output leakage current: DQ are disabled;
0V 

 V

OUT

 

 V

DDQ

; ODT is disabled; ODT is HIGH

I

OZ

–5

5

μA

1

DDR3L Output slew rate: Differential; For rising and fall-
ing edges, measure between V

OL,diff(AC)

 = –0.18 × V

DDQ

and V

OH,diff(AC)

 = 0.18 × V

DDQ

SRQ

diff

3.5

12

V/ns

1

Differential high-level output voltage

V

OH,diff(AC)

+0.2 × V

DDQ

V

1, 4

Differential low-level output voltage

V

OL,diff(AC)

–0.2 × V

DDQ

V

1, 4

Delta Ron between pull-up and pull-down for DQ/DQS

MM

PUPD

–10

10

%

1, 5

Test load for AC timing and output slew rates

Output to V

TT

 (V

DDQ

/2) via 25

˖

 resistor

3

Notes:

1. RZQ of 240

˖

±1% with RZQ/7 enabled (default 34

˖

 driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

;

V

SSQ

 = 

V

SS

).

2.

V

REF

 = 

V

DDQ

/2; slew rate @ 5 V/ns, interpolate for faster slew rate.

3. See Figure 31 (page 75) for the test load configuration.
4. See Table 52 (page 77) for the output slew rate.
5. See Table 38 (page 67) for additional information.
6. See Figure 30 (page 74) for an example of a differential output signal.

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Table 50: DDR3L Differential Output Driver Characteristics V

OX(AC)

All voltages are referenced to V

SS

Parameter/

Condition

Symbol

DDR3L- 800/1066/1333 DQS/DQS# Differential Slew Rate

Unit

3.5V/ns

4V/ns

5V/ns

6V/ns

7V/ns

8V/ns

9V/ns

10V/ns

12V/ns

Output differential
crosspoint voltage

V

OX(AC)

Max

115

130

135

195

205

205

205

205

205

mV

Min

–115

–130

–135

–195

–205

–205

–205

–205

–205

mV

Parameter/

Condition

Symbol

DDR3L-1600/1866/2133 DQS/DQS# Differential Slew Rate

Unit

3.5V/ns

4V/ns

5v/ns

6V/ns

7V/ns

8V/ns

9V/ns

10V/ns

12V/ns

Output differential

crosspoint voltage

V

OX(AC)

Max

90

105

135

155

180

205

205

205

205

mV

Min

–90

–105

–135

–155

–180

–205

–205

–205

–205

mV

Notes:

1. RZQ of 240

˖

±1% with RZQ/7 enabled (default 34

˖

 driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (

V

DDQ

 = 

V

DD

;

V

SSQ

 = 

V

SS

).

2. See Figure 31 (page 75) for the test load configuration.
3. See Figure 30 (page 74) for an example of a differential output signal.
4. For a differential slew rate between the list values, the V

OX(AC)

 value may be obtained

by linear interpolation.

Figure 30: Differential Output Signal

V

OH

MIN output

MAX output

V

OL

V

OX(AC)max

V

OX(AC)min

X

X

X

X

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Reference Output Load

Figure 31 (page 75) represents the effective reference load of 25

ȍ

 used in defining the

relevant device AC timing parameters (except ODT reference timing) as well as the out-
put slew rate measurements. It is not intended to be a precise representation of a partic-
ular system environment or a depiction of the actual load presented by a production
tester. System designers should use IBIS or other simulation tools to correlate the tim-
ing reference load to a system environment.

Figure 31: Reference Output Load for AC Timing and Output Slew Rate

Timing reference point

DQ

DQS

DQS#

DUT

V

REF

V

TT

 = V

DDQ

/2

V

DDQ

/2

ZQ

RZQ = 240

ȍ

V

SS

 

R

TT

 = 25

ȍ

Slew Rate Definitions for Single-Ended Output Signals

The single-ended output driver is summarized in Table 48 (page 72). With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between V

OL(AC)

 and V

OH(AC)

 for single-ended signals.

Table 51: Single-Ended Output Slew Rate Definition

Single-Ended Output Slew

Rates (Linear Signals)

Measured

Calculation

Output

Edge

From

To

DQ

Rising

V

OL(AC)

V

OH(AC)

V

OH(AC)

 - V

OL(AC)

ǻ

TR

se

Falling

V

OH(AC)

V

OL(AC)

V

OH(AC)

 - V

OL(AC)

ǻ

TF

se

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Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals

V

OH(AC)

V

OL(AC)

V

TT

ǻ

TF

se

ǻ

TR

se

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Slew Rate Definitions for Differential Output Signals

The differential output driver is summarized in Table 49 (page 73). With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between V

OL(AC)

 and V

OH(AC)

 for differential signals.

Table 52: Differential Output Slew Rate Definition

Differential Output Slew

Rates (Linear Signals)

Measured

Calculation

Output

Edge

From

To

DQS, DQS#

Rising

V

OL,diff(AC)

V

OH,diff(AC)

V

OH,diff(AC)

 - V

OL,diff(AC)

ǻ

TR

diff

Falling

V

OH,diff(AC)

V

OL,diff(AC)

V

OH,diff(AC)

 - V

OL,diff(AC)

ǻ

TF

diff

Figure 33: Nominal Differential Output Slew Rate Definition for DQS, DQS#

ǻ

TR

diff

ǻ

TF

diff

V

OH,diff(AC)

V

OL,diff(AC)

0

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Speed Bin Tables

Table 53: DDR3L-1066 Speed Bins

DDR3L-1066 Speed Bin

-187E

-187

Unit

Notes

CL-

t

RCD-

t

RP

7-7-7

8-8-8

Parameter

Symbol

Min

Max

Min

Max

Internal READ command to first data

t

AA

13.125

15

ns

 

ACTIVATE to internal READ or WRITE delay
time

t

RCD

13.125

15

ns

 

PRECHARGE command period

t

RP

13.125

15

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command
period

t

RC

50.625

52.5

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

37.5

9 x 

t

REFI

37.5

9 x 

t

REFI

ns

1

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

3.0

3.3

ns

2

CWL = 6

t

CK (AVG)

Reserved

Reserved

ns

3

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

2.5

3.3

ns

2

CWL = 6

t

CK (AVG)

Reserved

Reserved

ns

3

CL = 7

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

3

CWL = 6

t

CK (AVG)

1.875

<2.5

Reserved

ns

2, 3

CL = 8

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

3

CWL = 6

t

CK (AVG)

1.875

<2.5

1.875

<2.5

ns

2

Supported CL settings

5, 6, 7, 8

5, 6, 8

CK

 

Supported CWL settings

5, 6

5, 6

CK

 

Notes:

1.

t

REFI depends on T

OPER

.

2. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

3. Reserved settings are not allowed.

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Table 54: DDR3L-1333 Speed Bins

DDR3L-1333 Speed Bin

-15E

1

-15

2

Unit

Notes

CL-

t

RCD-

t

RP

9-9-9

10-10-10

Parameter

Symbol

Min

Max

Min

Max

Internal READ command to first data

t

AA

13.5

15

ns

 

ACTIVATE to internal READ or WRITE delay
time

t

RCD

13.5

15

ns

 

PRECHARGE command period

t

RP

13.5

15

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command
period

t

RC

49.5

51

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

36

9 x 

t

REFI

36

9 x 

t

REFI

ns

3

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

3.0

3.3

ns

4

CWL = 6, 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

2.5

3.3

ns

4

CWL = 6

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 7

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 6

t

CK (AVG)

1.875

<2.5

Reserved

ns

4, 5

CWL = 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 8

CWL = 5

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 6

t

CK (AVG)

1.875

<2.5

1.875

<2.5

ns

4

CWL = 7

t

CK (AVG)

Reserved

Reserved

ns

5

CL = 9

CWL = 5, 6

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 7

t

CK (AVG)

1.5

<1.875

Reserved

ns

4, 5

CL = 10

CWL = 5, 6

t

CK (AVG)

Reserved

Reserved

ns

5

CWL = 7

t

CK (AVG)

1.5

<1.875

1.5

<1.875

ns

4

Supported CL settings

5, 6, 7, 8, 9, 10

5, 6, 8, 10

CK

 

Supported CWL settings

5, 6, 7

5, 6, 7

CK

 

Notes:

1. The -15E speed grade is backward compatible with 1066, CL = 7 (-187E).
2. The -15 speed grade is backward compatible with 1066, CL = 8 (-187).
3.

t

REFI depends on T

OPER

.

4. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

5. Reserved settings are not allowed.

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Table 55: DDR3L-1600 Speed Bins

DDR3L-1600 Speed Bin

-125

1

Unit

Notes

CL-

t

RCD-

t

RP

11-11-11

Parameter

Symbol

Min

Max

Internal READ command to first data

t

AA

13.75

ns

 

ACTIVATE to internal READ or WRITE delay time

t

RCD

13.75

ns

 

PRECHARGE command period

t

RP

13.75

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command period

t

RC

48.75

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

35

9 x 

t

REFI

ns

2

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

ns

3

CWL = 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

ns

3

CWL = 6

t

CK (AVG)

Reserved

ns

4

CWL = 7, 8

t

CK (AVG)

Reserved

ns

4

CL = 7

CWL = 5

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 8

CWL = 5

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 9

CWL = 5, 6

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 10

CWL = 5, 6

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 11

CWL = 5, 6, 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

1.25

<1.5

ns

3

Supported CL settings

5, 6, 7, 8, 9, 10, 11

CK

 

Supported CWL settings

5, 6, 7, 8

CK

 

Notes:

1. The -125 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7

(-187E).

2.

t

REFI depends on T

OPER

.

3. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

4Gb: x4, x8, x16 DDR3L SDRAM

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Table 56: DDR3L-1866 Speed Bins

DDR3L-1866 Speed Bin

-107

1

Unit

Notes

CL-

t

RCD-

t

RP

13-13-13

Parameter

Symbol

Min

Max

Internal READ command to first data

t

AA

13.91

20

  

ACTIVATE to internal READ or WRITE delay time

t

RCD

13.91

ns

 

PRECHARGE command period

t

RP

13.91

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command period

t

RC

47.91

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

34

9 x 

t

REFI

ns

2

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 7

CWL = 5, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CL = 8

CWL = 5, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CL = 9

CWL = 5, 6, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CL = 10

CWL = 5, 6, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 11

CWL = 5, 6, 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

1.25

<1.5

ns

3

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 12

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 13

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

1.07

<1.25

ns

3

Supported CL settings

5, 6, 7, 8, 9, 10, 11, 13

CK

 

Supported CWL settings

5, 6, 7, 8, 9

CK

 

Notes:

1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9

(-15E) and 1066, CL = 7 (-187E).

2.

t

REFI depends on T

OPER

.

3. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

4Gb: x4, x8, x16 DDR3L SDRAM

Speed Bin Tables

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Table 57: DDR3L-2133 Speed Bins

DDR3L-2133 Speed Bin

-093

1

Unit

Notes

CL-

t

RCD-

t

RP

14-14-14

Parameter

Symbol

Min

Max

Internal READ command to first data

t

AA

13.09

20

  

ACTIVATE to internal READ or WRITE delay time

t

RCD

13.09

ns

 

PRECHARGE command period

t

RP

13.09

ns

 

ACTIVATE-to-ACTIVATE or REFRESH command period

t

RC

46.09

ns

 

ACTIVATE-to-PRECHARGE command period

t

RAS

33

9 x 

t

REFI

ns

2

CL = 5

CWL = 5

t

CK (AVG)

3.0

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 6

CWL = 5

t

CK (AVG)

2.5

3.3

ns

3

CWL = 6, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CL = 7

CWL = 5, 7, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CL = 8

CWL = 5, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 6

t

CK (AVG)

1.875

<2.5

ns

3

CWL = 7

t

CK (AVG)

Reserved

ns

4

CL = 9

CWL = 5, 6, 8, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CL = 10

CWL = 5, 6, 9

t

CK (AVG)

Reserved

ns

4

CWL = 7

t

CK (AVG)

1.5

<1.875

ns

3

CWL = 8

t

CK (AVG)

Reserved

ns

4

CL = 11

CWL = 5, 6, 7

t

CK (AVG)

Reserved

ns

4

CWL = 8

t

CK (AVG)

1.25

<1.5

ns

3

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 12

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

Reserved

ns

4

CL = 13

CWL = 5, 6, 7, 8

t

CK (AVG)

Reserved

ns

4

CWL = 9

t

CK (AVG)

1.07

<1.25

ns

3

CL = 14

CWL = 5, 6, 7, 8, 9

t

CK (AVG)

Reserved

Reserved

ns

4

CWL = 10

t

CK (AVG)

0.938

<1.07

ns

3

Supported CL settings

5, 6, 7, 8, 9, 10, 11, 13, 14

CK

 

Supported CWL settings

5, 6, 7, 8, 9

CK

 

Notes:

1. The -093 speed grade is backward compatible with 1866, CL = 13 (-107) , 1600, CL = 11

(-125) , 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E).

2.

t

REFI depends on T

OPER

.

3. The CL and CWL settings result in 

t

CK requirements. When making a selection of 

t

CK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

4Gb: x4, x8, x16 DDR3L SDRAM

Speed Bin Tables

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Electrical Characteristics and AC Operating Conditions

Table 58: Electrical Characteristics and AC Operating Conditions

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Clock Timing

Clock period average:
DLL disable mode

T

 85°C

t

CK

(DLL_DIS)

8

7800

8

7800

8

7800

8

7800

ns

9, 42

T

C

 = >85°C to 95°C

8

3900

8

3900

8

3900

8

3900

ns

42

Clock period average: DLL enable mode

t

CK (AVG)

See Speed Bin Tables for 

t

CK range allowed

ns

10, 11

High pulse width average

t

CH (AVG)

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

CK

12

Low pulse width average

t

CL (AVG)

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

CK

12

Clock period jitter

DLL locked

t

JITper

–100

100

–90

90

–80

80

–70

70

ps

13

DLL locking

t

JITper,lck

–90

90

–80

80

–70

70

–60

60

ps

13

Clock absolute period

t

CK (ABS)

MIN = 

t

CK (AVG) MIN + 

t

JITper MIN; MAX = 

t

CK (AVG) MAX + 

t

JITper

MAX

ps

 

Clock absolute high pulse width

t

CH (ABS)

0.43

0.43

0.43

0.43

t

CK

(AVG)

14

Clock absolute low pulse width

t

CL (ABS)

0.43

0.43

0.43

0.43

t

CK

(AVG)

15

Cycle-to-cycle jitter

DLL locked

t

JITcc

200

180

160

140

ps

16

DLL locking

t

JITcc,lck

180

160

140

120

ps

16

Cumulative error across 2 cycles

t

ERR2per

–147

147

–132

132

–118

118

–103

103

ps

17

3 cycles

t

ERR3per

–175

175

–157

157

–140

140

–122

122

ps

17

4 cycles

t

ERR4per

–194

194

–175

175

–155

155

–136

136

ps

17

5 cycles

t

ERR5per

–209

209

–188

188

–168

168

–147

147

ps

17

6 cycles

t

ERR6per

–222

222

–200

200

–177

177

–155

155

ps

17

7 cycles

t

ERR7per

–232

232

–209

209

–186

186

–163

163

ps

17

8 cycles

t

ERR8per

–241

241

–217

217

–193

193

–169

169

ps

17

9 cycles

t

ERR9per

–249

249

–224

224

–200

200

–175

175

ps

17

10 cycles

t

ERR10per

–257

257

–231

231

–205

205

–180

180

ps

17

11 cycles

t

ERR11per

–263

263

–237

237

–210

210

–184

184

ps

17

12 cycles

t

ERR12per

–269

269

–242

242

–215

215

–188

188

ps

17

= 13, 14 . . . 49, 50

cycles

t

ERR

n

per

t

ERR

n

per MIN = (1 + 0.68ln[

n

]) × 

t

JITper MIN

t

ERR

n

per MAX = (1 + 0.68ln[

n

]) × 

t

JITper MAX

ps

17

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

09005aef85af8fa8

4Gb_DDR3L.pdf - Rev

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

DQ Input Timing

Data setup time to
DQS, DQS#

Base (specification)

t

DS

(AC160)

90

40

ps

18, 19, 

44

V

REF

 @ 1 V/ns

250

200

ps

19, 20

Data setup time to
DQS, DQS#

Base (specification)

t

DS

(AC135)

140

90

45

25

ps

18, 19, 

44

V

REF

 @ 1 V/ns

275

250

180

160

ps

19, 20

Data hold time from
DQS, DQS#

Base (specification)

t

DH

(DC90)

160

110

75

55

ps

18, 19

V

REF

 @ 1 V/ns

250

200

165

145

ps

19, 20

Minimum data pulse width

t

DIPW

600

490

400

360

ps

41

DQ Output Timing

DQS, DQS# to DQ skew, per access

t

DQSQ

200

150

125

100

ps

 

DQ output hold time from DQS, DQS#

t

QH

0.38

0.38

0.38

0.38

t

CK

(AVG)

21

DQ Low-Z time from CK, CK#

t

LZDQ

–800

400

–600

300

–500

250

–450

225

ps

22, 23

DQ High-Z time from CK, CK#

t

HZDQ

400

300

250

225

ps

22, 23

DQ Strobe Input Timing

DQS, DQS# rising to CK, CK# rising

t

DQSS

–0.25

0.25

–0.25

0.25

–0.25

0.25

–0.27

0.27

CK

25

DQS, DQS# differential input low pulse width

t

DQSL

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK

 

DQS, DQS# differential input high pulse
width

t

DQSH

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

CK

 

DQS, DQS# falling setup to CK, CK# rising

t

DSS

0.2

0.2

0.2

0.18

CK

25

DQS, DQS# falling hold from CK, CK# rising

t

DSH

0.2

0.2

0.2

0.18

CK

25

DQS, DQS# differential WRITE preamble

t

WPRE

0.9

0.9

0.9

0.9

CK

 

DQS, DQS# differential WRITE postamble

t

WPST

0.3

0.3

0.3

0.3

CK

 

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK#

t

DQSCK

–400

400

–300

300

–255

255

–225

225

ps

23

DQS, DQS# rising to/from rising CK, CK#
when DLL is disabled

t

DQSCK

(DLL_DIS)

1

10

1

10

1

10

1

10

ns

26

DQS, DQS# differential output high time

t

QSH

0.38

0.38

0.40

0.40

CK

21

DQS, DQS# differential output low time

t

QSL

0.38

0.38

0.40

0.40

CK

21

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

09005aef85af8fa8

4Gb_DDR3L.pdf - Rev

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

DQS, DQS# Low-Z time (RL - 1)

t

LZDQS

–800

400

–600

300

–500

250

–450

225

ps

22, 23

DQS, DQS# High-Z time (RL + BL/2)

t

HZDQS

400

300

250

225

ps

22, 23

DQS, DQS# differential READ preamble

t

RPRE

0.9

Note 24

0.9

Note 24

0.9

Note 24

0.9

Note 24

CK

23, 24

DQS, DQS# differential READ postamble

t

RPST

0.3

Note 27

0.3

Note 27

0.3

Note 27

0.3

Note 27

CK

23, 27

Command and Address Timing

DLL locking time

t

DLLK

512

512

512

512

CK

28

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC160)

215

140

80

60

ps

29, 30, 

44

V

REF

 @ 1 V/ns

375

300

240

220

ps

20, 30

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC135)

365

290

205

185

ps

29, 30, 

44

V

REF

 @ 1 V/ns

500

425

340

320

ps

20, 30

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IH

(DC90

285

210

150

130

ps

29, 30, 

44

V

REF

 @ 1 V/ns

375

300

240

220

ps

20, 30

Minimum CTRL, CMD, ADDR pulse width

t

IPW

900

780

620

560

ps

41

ACTIVATE to internal READ or WRITE delay

t

RCD

See Speed Bin Tables for 

t

RCD

ns

31

PRECHARGE command period

t

RP

See Speed Bin Tables for 

t

RP

ns

31

ACTIVATE-to-PRECHARGE command period

t

RAS

See Speed Bin Tables for 

t

RAS

ns

31, 32

ACTIVATE-to-ACTIVATE command period

t

RC

See Speed Bin Tables for 

t

RC

ns

31, 43

ACTIVATE-to-ACTIVATE
minimum command
period

x4/x8 (1KB page
size)

t

RRD

MIN = greater of

4CK or 10ns

MIN = greater of

4CK or 7.5ns

MIN = greater of

4CK or 6ns

MIN = greater of

4CK or 6ns

CK

31

x16 (2KB page size)

MIN = greater of 4CK or 10ns

MIN = greater of 4CK or 7.5ns

CK

31

Four ACTIVATE
windows

x4/x8 (1KB page
size)

t

FAW

40

37.5

30

30

ns

31

x16 (2KB page size)

50

50

45

40

ns

31

Write recovery time

t

WR

MIN = 15ns; MAX = N/A

ns

31, 32, 

33,34

Delay from start of internal WRITE
transaction to internal READ command

t

WTR

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 34

READ-to-PRECHARGE time

t

RTP

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 32

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

09005aef85af8fa8

4Gb_DDR3L.pdf - Rev

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

CAS#-to-CAS# command delay

t

CCD

MIN = 4CK; MAX = N/A

CK

 

Auto precharge write recovery + precharge
time

t

DAL

MIN = WR + 

t

RP/

t

CK (AVG); MAX = N/A

CK

 

MODE REGISTER SET command cycle time

t

MRD

MIN = 4CK; MAX = N/A

CK

 

MODE REGISTER SET command update delay

t

MOD

MIN = greater of 12CK or 15ns; MAX = N/A

CK

 

MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit

t

MPRR

MIN = 1CK; MAX = N/A

CK

 

Calibration Timing

ZQCL command: Long
calibration time

POWER-UP and RE-
SET operation

t

ZQinit

512

512

512

512

CK

 

Normal operation

t

ZQoper

256

256

256

256

CK

 

ZQCS command: Short calibration time

t

ZQCS

64

64

64

64

CK

 

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command

t

XPR

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Begin power supply ramp to power supplies
stable

t

VDDPR

MIN = N/A; MAX = 200

ms

 

RESET# LOW to power supplies stable

t

RPS

MIN = 0; MAX = 200

ms

 

RESET# LOW to I/O and R

TT

 High-Z

t

IOZ

MIN = N/A; MAX = 20

ns

35

Refresh Timing

REFRESH-to-ACTIVATE or REFRESH
command period

t

RFC – 1Gb

MIN = 110; MAX = 70,200

ns

 

t

RFC – 2Gb

MIN = 160; MAX = 70,200

ns

 

t

RFC – 4Gb

MIN = 260; MAX = 70,200

ns

 

t

RFC – 8Gb

MIN = 350; MAX = 70,200

ns

 

Maximum refresh
period

T

C

 

 85°C

64 (1X)

ms

36

T

C

 > 85°C and 

95°C

32 (2X)

ms

36

T

C

 > 95°C and 

105°C

16 (4X)

ms

36

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Maximum average
periodic refresh

T

C

 

 85°C

t

REFI

7.8 (64ms/8192)

μs

36

T

C

 > 85°C and 

95°C

3.9 (32ms/8192)

μs

36

T

C

 > 95°C and 

105°C

1.95 (16ms/8192)

μs

36

Self Refresh Timing

Exit self refresh to commands not requiring a
locked DLL

t

XS

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Exit self refresh to commands requiring a
locked DLL

t

XSDLL

MIN = 

t

DLLK (MIN); MAX = N/A

CK

28

Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing

t

CKESR

MIN = 

t

CKE (MIN) + CK; MAX = N/A

CK

 

Valid clocks after self refresh entry or power-
down entry

t

CKSRE

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Valid clocks before self refresh exit,
power-down exit, or reset exit

t

CKSRX

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Power-Down Timing

CKE MIN pulse width

t

CKE (MIN)

Greater of 3CK

or 7.5ns

Greater of 3CK

or 5.625ns

Greater of 3CK

or 5.625ns

Greater of 3CK

or 5ns

CK

 

Command pass disable delay

t

CPDED

MIN = 1; MAX = N/A

CK

 

Power-down entry to power-down exit tim-
ing

t

PD

MIN = 

t

CKE (MIN); MAX = 9 * tREFI

CK

 

Begin power-down period prior to CKE
registered HIGH

t

ANPD

WL - 1CK

CK

 

Power-down entry period: ODT either
synchronous or asynchronous

PDE

Greater of 

t

ANPD or 

t

RFC - REFRESH command to CKE LOW time

CK

 

Power-down exit period: ODT either
synchronous or asynchronous

PDX

t

ANPD + 

t

XPDLL

CK

 

Power-Down Entry Minimum Timing

ACTIVATE command to power-down entry

t

ACTPDEN

MIN = 1

CK

 

PRECHARGE/PRECHARGE ALL command to
power-down entry

t

PRPDEN

MIN = 1

CK

 

REFRESH command to power-down entry

t

REFPDEN

MIN = 1

CK

37

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

MRS command to power-down entry

t

MRSPDEN

MIN = 

t

MOD (MIN)

CK

 

READ/READ with auto precharge command
to power-down entry

t

RDPDEN

MIN = RL + 4 + 1

CK

 

WRITE command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRPDEN

MIN = WL + 4 + 

t

WR/

t

CK (AVG)

CK

 

BC4MRS

t

WRPDEN

MIN = WL + 2 + 

t

WR/

t

CK (AVG)

CK

 

WRITE with auto
precharge command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRAP-

DEN

MIN = WL + 4 + WR + 1

CK

 

BC4MRS

t

WRAP-

DEN

MIN = WL + 2 + WR + 1

CK

 

Power-Down Exit Timing

DLL on, any valid command, or DLL off to
commands not requiring locked DLL

t

XP

MIN = greater of 3CK or 7.5ns;

MAX = N/A

MIN = greater of 3CK or 6ns;

MAX = N/A

CK

 

Precharge power-down with DLL off to
commands requiring a locked DLL

t

XPDLL

MIN = greater of 10CK or 24ns; MAX = N/A

CK

28

ODT Timing

R

TT

 synchronous turn-on delay

ODTLon

CWL + AL - 2CK

CK

38

R

TT

 synchronous turn-off delay

ODTLoff

CWL + AL - 2CK

CK

40

R

TT

 turn-on from ODTL on reference

t

AON

–400

400

–300

300

–250

250

–225

225

ps

23, 38

R

TT

 turn-off from ODTL off reference

t

AOF

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

CK

39, 40

Asynchronous R

TT

 turn-on delay

(power-down with DLL off)

t

AONPD

MIN = 2; MAX = 8.5

ns

38

Asynchronous R

TT

 turn-off delay

(power-down with DLL off)

t

AOFPD

MIN = 2; MAX = 8.5

ns

40

ODT HIGH time with WRITE command and
BL8

ODTH8

MIN = 6; MAX = N/A

CK

 

ODT HIGH time without WRITE command or
with WRITE command and BC4

ODTH4

MIN = 4; MAX = N/A

CK

 

Dynamic ODT Timing

R

TT,nom

-to-R

TT(WR)

 change skew

ODTLcnw

WL - 2CK

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BC4

ODTLcwn4

4CK + ODTLoff

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BL8

ODTLcwn8

6CK + ODTLoff

CK

 

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-800

DDR3L-1066

DDR3L-1333

DDR3L-1600

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

R

TT

 dynamic change skew

t

ADC

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

CK

39

Write Leveling Timing

First DQS, DQS# rising edge

t

WLMRD

40

40

40

40

CK

 

DQS, DQS# delay

t

WLDQSEN

25

25

25

25

CK

 

Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing

t

WLS

325

245

195

165

ps

 

Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing

t

WLH

325

245

195

165

ps

 

Write leveling output delay

t

WLO

0

9

0

9

0

9

0

7.5

ns

 

Write leveling output error

t

WLOE

0

2

0

2

0

2

0

2

ns

 

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Notes:

1. AC timing parameters are valid from specified T

C

 MIN to T

C

 MAX values.

2. All voltages are referenced to V

SS

.

3. Output timings are only valid for R

ON34

 output buffer selection.

4. The unit 

t

CK (AVG) represents the actual 

t

CK (AVG) of the input clock under operation.

The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.

5. AC timing and I

DD

 tests may use a V

IL

-to-V

IH

 swing of up to 900mV in the test environ-

ment, but input timing is still referenced to V

REF

 (except 

t

IS, 

t

IH, 

t

DS, and 

t

DH use the

AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between V

IL(AC)

 and V

IH(AC)

.

6. All timings that use time-based values (ns, μs, ms) should use 

t

CK (AVG) to determine the

correct number of clocks (Table 58 (page 83) uses CK or 

t

CK [AVG] interchangeably). In

the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.

7. Strobe or DQS

diff

 refers to the DQS and DQS# differential crossing point when DQS is

the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates.

The actual test load may be different. The output signal voltage reference point is
V

DDQ

/2 for single-ended signals and the crossing point for differential signals (see Figure

31 (page 75)).

9. When operating in DLL disable mode, Micron does not warrant compliance with normal

mode timings or functionality.

10. The clock’s 

t

CK (AVG) is the average clock over any 200 consecutive clocks and 

t

CK (AVG)

MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.

11. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of 

t

CK (AVG) as a long-term jitter component; however, the spread

spectrum may not use a clock rate below 

t

CK (AVG) MIN.

12. The clock’s 

t

CH (AVG) and 

t

CL (AVG) are the average half clock period over any 200 con-

secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.

13. The period jitter (

t

JITper) is the maximum deviation in the clock period from the average

or nominal clock. It is allowed in either the positive or negative direction.

14.

t

CH (ABS) is the absolute instantaneous clock high pulse width as measured from one

rising edge to the following falling edge.

15.

t

CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-

ing edge to the following rising edge.

16. The cycle-to-cycle jitter 

t

JITcc is the amount the clock period can deviate from one cycle

to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.

17. The cumulative jitter error 

t

ERRnper, where 

n

 is the number of clocks between 2 and 50,

is the amount of clock time allowed to accumulate consecutively away from the average
clock over 

n

 number of clock cycles.

18.

t

DS (base) and 

t

DH (base) values are for a single-ended 1 V/ns slew rate DQs and 2 V/ns

slew rate differential DQS, DQS#; when DQ single-ended slew rate is 2V/ns, the DQS dif-
ferential slew rate is 4V/ns.

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-

tion edge to its respective data strobe signal (DQS, DQS#) crossing.

20. The setup and hold times are listed converting the base specification values (to which

derating tables apply) to V

REF

 when the slew rate is 1 V/ns. These values, with a slew rate

of 1 V/ns, are for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated

by the actual 

t

JITper (larger of 

t

JITper (MIN) or 

t

JITper (MAX) of the input clock (output

deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-

rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting 

t

ERR10per (MAX): 

t

DQSCK

(MIN), 

t

LZDQS (MIN), 

t

LZDQ (MIN), and 

t

AON (MIN). The following parameters are re-

quired to be derated by subtracting 

t

ERR10per (MIN): 

t

DQSCK (MAX), 

t

HZ (MAX), 

t

LZDQS

(MAX), 

t

LZDQ MAX, and 

t

AON (MAX). The parameter 

t

RPRE (MIN) is derated by subtract-

ing 

t

JITper (MAX), while 

t

RPRE (MAX) is derated by subtracting 

t

JITper (MIN).

24. The maximum preamble is bound by 

t

LZDQS (MAX).

25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-

spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.

26. The 

t

DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.

27. The maximum postamble is bound by 

t

HZDQS (MAX).

28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-

mands. In addition, after any change of latency 

t

XPDLL, timing must be met.

29.

t

IS (base) and 

t

IH (base) values are for a single-ended 1 V/ns control/command/address

slew rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its

respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.

31. For these parameters, the DDR3L SDRAM device supports 

t

n

PARAM (

n

CK) = RU(

t

PARAM

[ns]/

t

CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-

ple, the device will support 

t

n

RP (

n

CK) = RU(

t

RP/

t

CK[AVG]) if all input clock jitter specifi-

cations are met. This means that for DDR3-800 6-6-6, of which 

t

RP = 5ns, the device will

support 

t

n

RP = RU(

t

RP/

t

CK[AVG]) = 6 as long as the input clock jitter specifications are

met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.

32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-

ternal PRECHARGE command until 

t

RAS (MIN) has been satisfied.

33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for 

t

WR.

34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL

• For BC4 (OTF): Rising clock edge four clock cycles after WL

• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL

35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in

High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.

36. The refresh period is 64ms when T

C

 is less than or equal to 85°C. This equates to an aver-

age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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least once every 70.3μs. When T

C

 is greater than 85°C, but less the 95°C, the refresh peri-

od is 32ms. When T

C

 is greater than 95°C, but less the 105°C, the refresh period is 16ms.

37. Although CKE is allowed to be registered LOW after a REFRESH command when

t

REFPDEN (MIN) is satisfied, there are cases where additional time such as 

t

XPDLL (MIN)

is required.

38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to

turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 24 (page 63). This output load is used for ODT timings
(see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-
mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.

39. Half-clock output parameters must be derated by the actual 

t

ERR10per and 

t

JITdty when

input clock jitter is present. This results in each parameter becoming larger. The parame-
ters 

t

ADC (MIN) and

 t

AOF (MIN) are each required to be derated by subtracting both

t

ERR10per (MAX) and 

t

JITdty (MAX). The parameters 

t

ADC (MAX) and 

t

AOF (MAX) are

required to be derated by subtracting both 

t

ERR10per (MAX) and 

t

JITdty (MAX).

40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT

turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31
(page 75)).

41. Pulse width of a input signal is defined as the width between the first crossing of

V

REF(DC)

 and the consecutive crossing of V

REF(DC)

.

42. Should the clock rate be larger than 

t

RFC (MIN), an AUTO REFRESH command should

have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.

43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.

44. When two V

IH(AC)

 values (and two corresponding V

IL(AC)

 values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
V

IH(AC)

 value may be used for address/command inputs and the other V

IH(AC)

 value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC175),min

 and

V

IH(AC150),min

 (corresponding V

IL(AC175),min

 and V

IL(AC150),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC175),min

 with 

t

IS(AC175) of 200ps or V

IH(AC150),min

with 

t

IS(AC150) of 350ps; independently, the data inputs must use either V

IH(AC175),min

with 

t

DS(AC175) of 75ps or V

IH(AC150),min

 with 

t

DS(AC150) of 125ps.

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Electrical Characteristics and AC Operating Conditions

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Electrical Characteristics and AC Operating Conditions

Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Clock Timing

Clock period average:
DLL disable mode

T

= 0°C to 85°C

t

CK

(DLL_DIS)

8

7800

8

7800

ns

9, 42

T

C

 = >85°C to 95°C

8

3900

8

3900

ns

42

Clock period average: DLL enable mode

t

CK (AVG)

See Speed Bin Tables for 

t

CK range allowed ns

10, 11

High pulse width average

t

CH (AVG)

0.47

0.53

0.47

0.53

CK

12

Low pulse width average

t

CL (AVG)

0.47

0.53

0.47

0.53

CK

12

Clock period jitter

DLL locked

t

JITper

–60

60

–50

50

ps

13

DLL locking

t

JITper,lck

–50

50

–40

40

ps

13

Clock absolute period

t

CK (ABS)

MIN = 

t

CK (AVG) MIN +

t

JITper MIN; MAX =

t

CK (AVG) MAX +

t

JITper MAX ps

 

Clock absolute high pulse width

t

CH (ABS)

0.43

0.43

t

CK

(AVG)

14

Clock absolute low pulse width

t

CL (ABS)

0.43

0.43

t

CK

(AVG)

15

Cycle-to-cycle jitter

DLL locked

t

JITcc

120

120

ps

16

DLL locking

t

JITcc,lck

100

100

ps

16

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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4Gb_DDR3L.pdf - Rev

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Cumulative error across 2 cycles

t

ERR2per

–88

88

–74

74

ps

17

3 cycles

t

ERR3per

–105

105

–87

87

ps

17

4 cycles

t

ERR4per

–117

117

–97

97

ps

17

5 cycles

t

ERR5per

–126

126

–105

105

ps

17

6 cycles

t

ERR6per

–133

133

–111

111

ps

17

7 cycles

t

ERR7per

–139

139

–116

116

ps

17

8 cycles

t

ERR8per

–145

145

–121

121

ps

17

9 cycles

t

ERR9per

–150

150

–125

125

ps

17

10 cycles

t

ERR10per

–154

154

–128

128

ps

17

11 cycles

t

ERR11per

–158

158

–132

132

ps

17

12 cycles

t

ERR12per

–161

161

–134

134

ps

17

= 13, 14 . . . 49, 50

cycles

t

ERR

n

per

t

ERR

n

per MIN = (1 + 0.68ln[

n

]) × 

t

JITper MIN

t

ERR

n

per MAX = (1 + 0.68ln[

n

]) × 

t

JITper MAX

ps

17

DQ Input Timing

Data setup time to
DQS, DQS#

Base (specification)
@ 2 V/ns

t

DS

(AC130)

70

55

ps

18, 19

V

REF

 @ 2 V/ns

135

120.5

ps

19, 20

Data hold time from
DQS, DQS#

Base (specification)
@ 2 V/ns

t

DH

(DC90)

75

60

ps

18, 19

V

REF

 @ 2 V/ns

110

105

ps

19, 20

Minimum data pulse width

t

DIPW

320

280

ps

41

DQ Output Timing

DQS, DQS# to DQ skew, per access

t

DQSQ

85

75

ps

 

DQ output hold time from DQS, DQS#

t

QH

0.38

0.38

t

CK

(AVG)

21

DQ Low-Z time from CK, CK#

t

LZDQ

–390

195

–360

180

ps

22, 23

DQ High-Z time from CK, CK#

t

HZDQ

195

180

ps

22, 23

DQ Strobe Input Timing

DQS, DQS# rising to CK, CK# rising

t

DQSS

–0.27

0.27

–0.27

0.27

CK

25

DQS, DQS# differential input low pulse width

t

DQSL

0.45

0.55

0.45

0.55

CK

 

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

DQS, DQS# differential input high pulse
width

t

DQSH

0.45

0.55

0.45

0.55

CK

 

DQS, DQS# falling setup to CK, CK# rising

t

DSS

0.18

0.18

CK

25

DQS, DQS# falling hold from CK, CK# rising

t

DSH

0.18

0.18

CK

25

DQS, DQS# differential WRITE preamble

t

WPRE

0.9

0.9

CK

 

DQS, DQS# differential WRITE postamble

t

WPST

0.3

0.3

CK

 

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK#

t

DQSCK

–195

195

–180

180

ps

23

DQS, DQS# rising to/from rising CK, CK#
when DLL is disabled

t

DQSCK

(DLL_DIS)

1

10

1

10

ns

26

DQS, DQS# differential output high time

t

QSH

0.40

0.40

CK

21

DQS, DQS# differential output low time

t

QSL

0.40

0.40

CK

21

DQS, DQS# Low-Z time (RL - 1)

t

LZDQS

–390

195

–360

180

ps

22, 23

DQS, DQS# High-Z time (RL + BL/2)

t

HZDQS

195

180

ps

22, 23

DQS, DQS# differential READ preamble

t

RPRE

0.9

Note 24

0.9

Note 24

CK

23, 24

DQS, DQS# differential READ postamble

t

RPST

0.3

Note 27

0.3

Note 27

CK

23, 27

Command and Address Timing

DLL locking time

t

DLLK

512

512

CK

28

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC135)

65

60

ps

29, 30, 

44

V

REF

 @ 1 V/ns

200

195

ps

20, 30

CTRL, CMD, ADDR
setup to CK,CK#

Base (specification)

t

IS

(AC125)

150

135

ps

29, 30, 

44

V

REF

 @ 1 V/ns

275

260

ps

20, 30

CTRL, CMD, ADDR hold
from CK,CK#

Base (specification)

t

IH

(DC90)

110

105

ps

29, 30

V

REF

 @ 1 V/ns

200

195

ps

20, 30

Minimum CTRL, CMD, ADDR pulse width

t

IPW

535

470

ps

41

ACTIVATE to internal READ or WRITE delay

t

RCD

See Speed Bin Tables for 

t

RCD

ns

31

PRECHARGE command period

t

RP

See Speed Bin Tables for 

t

RP

ns

31

ACTIVATE-to-PRECHARGE command period

t

RAS

See Speed Bin Tables for 

t

RAS

ns

31, 32

ACTIVATE-to-ACTIVATE command period

t

RC

See Speed Bin Tables for 

t

RC

ns

31, 43

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

ACTIVATE-to-ACTIVATE
minimum command pe-
riod

1KB page size

t

RRD

MIN = greater of 4CK or 5ns

CK

31

2KB page size

MIN = greater of 4CK or 6ns

CK

31

Four ACTIVATE
windows

1KB page size

t

FAW

27

25

ns

31

2KB page size

35

35

ns

31

Write recovery time

t

WR

MIN = 15ns; MAX = N/A

ns

31, 32, 

33

Delay from start of internal WRITE transac-
tion to internal READ command

t

WTR

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 34

READ-to-PRECHARGE time

t

RTP

MIN = greater of 4CK or 7.5ns; MAX = N/A

CK

31, 32

CAS#-to-CAS# command delay

t

CCD

MIN = 4CK; MAX = N/A

CK

 

Auto precharge write recovery + precharge
time

t

DAL

MIN = WR + 

t

RP/

t

CK (AVG); MAX = N/A

CK

 

MODE REGISTER SET command cycle time

t

MRD

MIN = 4CK; MAX = N/A

CK

 

MODE REGISTER SET command update delay

t

MOD

MIN = greater of 12CK or 15ns; MAX = N/A

CK

 

MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit

t

MPRR

MIN = 1CK; MAX = N/A

CK

 

Calibration Timing

ZQCL command: Long
calibration time

POWER-UP and RE-
SET operation

t

ZQinit

MIN = N/A

MAX = MAX(512nCK, 640ns)

CK

 

Normal operation

t

ZQoper

MIN = N/A

MAX = max(256nCK, 320ns)

CK

 

ZQCS command: Short calibration time

MIN = N/A

MAX = max(64nCK, 80ns) 

t

ZQCS

CK

 

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command

t

XPR

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Begin power supply ramp to power supplies
stable

t

VDDPR

MIN = N/A; MAX = 200

ms

 

RESET# LOW to power supplies stable

t

RPS

MIN = 0; MAX = 200

ms

 

RESET# LOW to I/O and R

TT

 High-Z

t

IOZ

MIN = N/A; MAX = 20

ns

35

Refresh Timing

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Electrical Characteristics and AC Operating Conditions

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

REFRESH-to-ACTIVATE or REFRESH
command period

t

RFC – 1Gb

MIN = 110; MAX = 70,200

ns

 

t

RFC – 2Gb

MIN = 160; MAX = 70,200

ns

 

t

RFC – 4Gb

MIN = 260; MAX = 70,200

ns

 

t

RFC – 8Gb

MIN = 350; MAX = 70,200

ns

 

Maximum refresh
period

T

C

 

 85°C

64 (1X)

ms

36

T

C

 > 85°C and 

95°C

32 (2X)

ms

36

T

C

 > 95°C and 

105°C

16 (4X)

ms

36

Maximum average
periodic refresh

T

C

 

 85°C

t

REFI

7.8 (64ms/8192)

μs

36

T

C

 > 85°C and 

95°C

3.9 (32ms/8192)

μs

36

T

C

 > 95°C and 

105°C

1.95 (16ms/8192)

μs

36

Self Refresh Timing

Exit self refresh to commands not requiring a
locked DLL

t

XS

MIN = greater of 5CK or 

t

RFC + 10ns; MAX = N/A

CK

 

Exit self refresh to commands requiring a
locked DLL

t

XSDLL

MIN = 

t

DLLK (MIN);

MAX = N/A

CK

28

Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing

t

CKESR

MIN = 

t

CKE (MIN) + CK; MAX = N/A

CK

 

Valid clocks after self refresh entry or power-
down entry

t

CKSRE

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Valid clocks before self refresh exit,
power-down exit, or reset exit

t

CKSRX

MIN = greater of 5CK or 10ns; MAX = N/A

CK

 

Power-Down Timing

CKE MIN pulse width

t

CKE (MIN)

Greater of 3CK or 5ns

CK

 

Command pass disable delay

t

CPDED

MIN = 2;

MAX = N/A

CK

 

Power-down entry to power-down exit tim-
ing

t

PD

MIN = 

t

CKE (MIN);

MAX = 9 * tREFI

CK

 

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Begin power-down period prior to CKE
registered HIGH

t

ANPD

WL - 1CK

CK

 

Power-down entry period: ODT either
synchronous or asynchronous

PDE

Greater of 

t

ANPD or 

t

RFC - REFRESH command to CKE LOW time

CK

 

Power-down exit period: ODT either
synchronous or asynchronous

PDX

t

ANPD + 

t

XPDLL

CK

 

Power-Down Entry Minimum Timing

ACTIVATE command to power-down entry

t

ACTPDEN

MIN = 2

CK

 

PRECHARGE/PRECHARGE ALL command to
power-down entry

t

PRPDEN

MIN = 2

CK

 

REFRESH command to power-down entry

t

REFPDEN

MIN = 2

CK

37

MRS command to power-down entry

t

MRSPDEN

MIN = 

t

MOD (MIN)

CK

 

READ/READ with auto precharge command
to power-down entry

t

RDPDEN

MIN = RL + 4 + 1

CK

 

WRITE command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRPDEN

MIN = WL + 4 +

t

WR/

t

CK (AVG)

CK

 

BC4MRS

t

WRPDEN

MIN = WL + 2 +

t

WR/

t

CK (AVG)

CK

 

WRITE with auto pre-
charge command to
power-down entry

BL8 (OTF, MRS)
BC4OTF

t

WRAP-

DEN

MIN = WL + 4 + WR + 1

CK

 

BC4MRS

t

WRAP-

DEN

MIN = WL + 2 + WR + 1

CK

 

Power-Down Exit Timing

DLL on, any valid command, or DLL off to
commands not requiring locked DLL

t

XP

MIN = greater of 3CK or 6ns;

MAX = N/A

CK

 

Precharge power-down with DLL off to
commands requiring a locked DLL

t

XPDLL

MIN = greater of 10CK or 24ns; MAX = N/A

CK

28

ODT Timing

R

TT

 synchronous turn-on delay

ODTL on

CWL + AL - 2CK

CK

38

R

TT

 synchronous turn-off delay

ODTL off

CWL + AL - 2CK

CK

40

R

TT

 turn-on from ODTL on reference

t

AON

–195

195

–180

180

ps

23, 38

R

TT

 turn-off from ODTL off reference

t

AOF

0.3

0.7

0.3

0.7

CK

39, 40

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Table 59: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter

Symbol

DDR3L-1866

DDR3L-2133

Unit

Notes

Min

Max

Min

Max

Asynchronous R

TT

 turn-on delay

(power-down with DLL off)

t

AONPD

MIN = 2; MAX = 8.5

ns

38

Asynchronous R

TT

 turn-off delay

(power-down with DLL off)

t

AOFPD

MIN = 2; MAX = 8.5

ns

40

ODT HIGH time with WRITE command and
BL8

ODTH8

MIN = 6; MAX = N/A

CK

 

ODT HIGH time without WRITE command or
with WRITE command and BC4

ODTH4

MIN = 4; MAX = N/A

CK

 

Dynamic ODT Timing

R

TT,nom

-to-R

TT(WR)

 change skew

ODTLcnw

WL - 2CK

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BC4

ODTLcwn4

4CK + ODTLoff

CK

 

R

TT(WR)

-to-R

TT,nom

 change skew - BL8

ODTLcwn8

6CK + ODTLoff

CK

 

R

TT

 dynamic change skew

t

ADC

0.3

0.7

0.3

0.7

CK

39

Write Leveling Timing

First DQS, DQS# rising edge

t

WLMRD

40

40

CK

 

DQS, DQS# delay

t

WLDQSEN

25

25

CK

 

Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing

t

WLS

140

125

ps

 

Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing

t

WLH

140

125

ps

 

Write leveling output delay

t

WLO

0

7.5

0

7

ns

 

Write leveling output error

t

WLOE

0

2

0

2

ns

 

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Notes:

1. AC timing parameters are valid from specified T

C

 MIN to T

C

 MAX values.

2. All voltages are referenced to V

SS

.

3. Output timings are only valid for R

ON34

 output buffer selection.

4. The unit 

t

CK (AVG) represents the actual 

t

CK (AVG) of the input clock under operation.

The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.

5. AC timing and I

DD

 tests may use a V

IL

-to-V

IH

 swing of up to 900mV in the test environ-

ment, but input timing is still referenced to V

REF

 (except 

t

IS, 

t

IH, 

t

DS, and 

t

DH use the

AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
(DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in
the range between V

IL(AC)

 and V

IH(AC)

.

6. All timings that use time-based values (ns, μs, ms) should use 

t

CK (AVG) to determine the

correct number of clocks (Table 59 (page 93) uses CK or 

t

CK [AVG] interchangeably). In

the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.

7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is

the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates.

The actual test load may be different. The output signal voltage reference point is
V

DDQ

/2 for single-ended signals and the crossing point for differential signals (see Figure

31 (page 75)).

9. When operating in DLL disable mode, Micron does not warrant compliance with normal

mode timings or functionality.

10. The clock’s 

t

CK (AVG) is the average clock over any 200 consecutive clocks and 

t

CK (AVG)

MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.

11. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of 

t

CK (AVG) as a long-term jitter component; however, the spread

spectrum may not use a clock rate below 

t

CK (AVG) MIN.

12. The clock’s 

t

CH (AVG) and 

t

CL (AVG) are the average half clock period over any 200 con-

secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.

13. The period jitter (

t

JITper) is the maximum deviation in the clock period from the average

or nominal clock. It is allowed in either the positive or negative direction.

14.

t

CH (ABS) is the absolute instantaneous clock high pulse width as measured from one

rising edge to the following falling edge.

15.

t

CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-

ing edge to the following rising edge.

16. The cycle-to-cycle jitter 

t

JITcc is the amount the clock period can deviate from one cycle

to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.

17. The cumulative jitter error 

t

ERRnper, where 

n

 is the number of clocks between 2 and 50,

is the amount of clock time allowed to accumulate consecutively away from the average
clock over 

n

 number of clock cycles.

18.

t

DS (base) and 

t

DH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at

2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#; when
DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns.

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19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-

tion edge to its respective data strobe signal (DQS, DQS#) crossing.

20. The setup and hold times are listed converting the base specification values (to which

derating tables apply) to V

REF

 when the slew rate is 1 V/ns (DQs are at 2V/ns for

DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns
for DDR3-1866 and DDR3-2133), are for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated

by the actual 

t

JITper (larger of 

t

JITper (MIN) or 

t

JITper (MAX) of the input clock (output

deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-

rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting 

t

ERR10per (MAX): 

t

DQSCK

(MIN), 

t

LZDQS (MIN), 

t

LZDQ (MIN), and 

t

AON (MIN). The following parameters are re-

quired to be derated by subtracting 

t

ERR10per (MIN): 

t

DQSCK (MAX), 

t

HZ (MAX), 

t

LZDQS

(MAX), 

t

LZDQ (MAX), and 

t

AON (MAX). The parameter 

t

RPRE (MIN) is derated by sub-

tracting 

t

JITper (MAX), while 

t

RPRE (MAX) is derated by subtracting 

t

JITper (MIN).

24. The maximum preamble is bound by 

t

LZDQS (MAX).

25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-

spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.

26. The 

t

DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.

27. The maximum postamble is bound by 

t

HZDQS (MAX).

28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-

mands. In addition, after any change of latency 

t

XPDLL, timing must be met.

29.

t

IS (base) and 

t

IH (base) values are for a single-ended 1 V/ns control/command/address

slew rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its

respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.

31. For these parameters, the DDR3L SDRAM device supports 

t

n

PARAM (

n

CK) = RU(

t

PARAM

[ns]/

t

CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-

ple, the device will support 

t

n

RP (

n

CK) = RU(

t

RP/

t

CK[AVG]) if all input clock jitter specifi-

cations are met. This means that for DDR3-800 6-6-6, of which 

t

RP = 5ns, the device will

support 

t

n

RP = RU(

t

RP/

t

CK[AVG]) = 6 as long as the input clock jitter specifications are

met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.

32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-

ternal PRECHARGE command until 

t

RAS (MIN) has been satisfied.

33. When operating in DLL disable mode, the greater of 5CK or 15ns is satisfied for 

t

WR.

34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL

• For BC4 (OTF): Rising clock edge four clock cycles after WL

• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL

35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in

High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.

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36. The refresh period is 64ms when T

C

 is less than or equal to 85°C. This equates to an aver-

age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at
least once every 70.3μs. When T

C

 is greater than 85°C, but less the 95°C, the refresh peri-

od is 32ms. When T

C

 is greater than 95°C, but less the 105°C, the refresh period is 16ms.

37. Although CKE is allowed to be registered LOW after a REFRESH command when

t

REFPDEN (MIN) is satisfied, there are cases where additional time such as 

t

XPDLL (MIN)

is required.

38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to

turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 24 (page 63). This output load is used for ODT timings
(see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-
mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.

39. Half-clock output parameters must be derated by the actual 

t

ERR10per and 

t

JITdty when

input clock jitter is present. This results in each parameter becoming larger. The parame-
ters 

t

ADC (MIN) and

 t

AOF (MIN) are each required to be derated by subtracting both

t

ERR10per (MAX) and 

t

JITdty (MAX). The parameters 

t

ADC (MAX) and 

t

AOF (MAX) are

required to be derated by subtracting both 

t

ERR10per (MAX) and 

t

JITdty (MAX).

40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT

turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31
(page 75)).

41. Pulse width of a input signal is defined as the width between the first crossing of

V

REF(DC)

 and the consecutive crossing of V

REF(DC)

.

42. Should the clock rate be larger than 

t

RFC (MIN), an AUTO REFRESH command should

have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.

43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.

44. When two V

IH(AC)

 values (and two corresponding V

IL(AC)

 values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
V

IH(AC)

 value may be used for address/command inputs and the other V

IH(AC)

 value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC175),min

 and

V

IH(AC150),min

 (corresponding V

IL(AC175),min

 and V

IL(AC150),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC175),min

 with 

t

IS(AC175) of 200ps or V

IH(AC150),min

with 

t

IS(AC150) of 350ps; independently, the data inputs must use either V

IH(AC175),min

with 

t

DS(AC175) of 75ps or V

IH(AC150),min

 with 

t

DS(AC150) of 125ps.

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Command and Address Setup, Hold, and Derating

The total 

t

IS (setup time) and 

t

IH (hold time) required is calculated by adding the data

sheet 

t

IS (base) and 

t

IH (base) values (see Table 60; values come from the Electrical

Characteristics and AC Operating Conditions table) to the 

ǻ

t

IS and 

ǻ

t

IH derating values

(see Table 61 (page 104), Table 62 (page 104) or Table 63 (page 104)) respectively. Ex-
ample: 

t

IS (total setup time) = 

t

IS (base) + 

ǻ

t

IS. For a valid transition, the input signal

has to remain above/below V

IH(AC)

/V

IL(AC)

 for some time 

t

VAC (see Table 64 (page 105)).

Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V

IH(AC)

/V

IL(AC)

 at the time of the rising clock transi-

tion), a valid input signal is still required to complete the transition and to reach
V

IH(AC)

/V

IL(AC)

 (see Figure 15 (page 53) for input signal requirements). For slew rates that

fall between the values listed in Table 61 (page 104) and Table 63 (page 104), the derat-
ing values may be obtained by linear interpolation.

Setup (

t

IS) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

REF(DC)

 and the first crossing of V

IH(AC)min

. Setup (

t

IS) nominal slew rate

for a falling signal is defined as the slew rate between the last crossing of V

REF(DC)

 and

the first crossing of V

IL(AC)max

. If the actual signal is always earlier than the nominal slew

rate line between the shaded V

REF(DC)

-to-AC region, use the nominal slew rate for derat-

ing value (see Figure 34 (page 106)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded V

REF(DC)

-to-AC region, the slew rate of a tangent

line to the actual signal from the AC level to the DC level is used for derating value (see 
Figure 36 (page 108)).

Hold (

t

IH) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

IL(DC)max

 and the first crossing of V

REF(DC)

. Hold (

t

IH) nominal slew rate

for a falling signal is defined as the slew rate between the last crossing of V

IH(DC)min

 and

the first crossing of V

REF(DC)

. If the actual signal is always later than the nominal slew

rate line between the shaded DC-to-V

REF(DC)

 region, use the nominal slew rate for derat-

ing value (see Figure 35 (page 107)). If the actual signal is earlier than the nominal slew
rate line anywhere between the shaded DC-to-V

REF(DC)

 region, the slew rate of a tangent

line to the actual signal from the DC level to the V

REF(DC)

 level is used for derating value

(see Figure 37 (page 109)).

Table 60: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based

Symbol

800

1066

1333

1600

1866

2133

Unit

Reference

t

IS(base, AC160)

215

140

80

60

ps

V

IH(AC)

/V

IL(AC)

t

IS(base, AC135)

365

290

205

185

65

60

ps

V

IH(AC)

/V

IL(AC)

t

IS(base, AC125)

150

135

ps

V

IH(AC)

/V

IL(AC)

t

IH(base, DC90)

285

210

150

130

110

105

ps

V

IH(DC)

/V

IL(DC)

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Table 61: DDR3L-800/1066 Derating Values 

t

IS/

t

IH – AC160/DC90-Based

˂

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

2.0

80

45

80

45

80

45

88

53

96

61

104

69

112

79

120

95

1.5

53

30

53

30

53

30

61

38

69

46

77

54

85

64

93

80

1.0

0

0

0

0

0

0

8

8

16

16

24

24

32

34

40

50

0.9

–1

–3

–1

–3

–1

–3

7

5

15

13

23

21

31

31

39

47

0.8

–3

–8

–3

–8

–3

–8

5

1

13

9

21

17

29

27

37

43

0.7

–5

–13

–5

–13

–5

–13

3

–5

11

3

19

11

27

21

35

37

0.6

–8

–20

–8

–20

–8

–20

0

–12

8

–4

16

4

24

14

32

30

0.5

–20

–30

–20

–30

–20

–30

–12

–22

–4

–14

4

–6

12

4

20

20

0.4

–40

–45

–40

–45

–40

–45

–32

–37

–24

–29

–16

–21

–8

–11

0

5

Table 62: DDR3L-800/1066/1333/1600 Derating Values for 

t

IS/

t

IH – AC135/DC90-Based

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

2.0

68

45

68

45

68

45

76

53

84

61

92

69

100

79

108

95

1.5

45

30

45

30

45

30

53

38

61

46

69

54

77

64

85

80

1.0

0

0

0

0

0

0

8

8

16

16

24

24

32

34

40

50

0.9

2

–3

2

–3

2

–3

10

5

18

13

26

21

34

31

42

47

0.8

3

–8

3

–8

3

–8

11

1

19

9

27

17

35

27

43

43

0.7

6

–13

6

–13

6

–13

14

–5

22

3

30

11

38

21

46

37

0.6

9

–20

9

–20

9

–20

17

–12

25

–4

33

4

41

14

49

30

0.5

5

–30

5

–30

5

–30

13

–22

21

–14

29

–6

37

4

45

20

0.4

–3

–45

–3

–45

–3

–45

6

–37

14

–29

22

–21

30

–11

38

5

Table 63: DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

2.0

63

45

63

45

63

45

71

53

79

61

87

69

95

79

103

95

1.5

42

30

42

30

42

30

50

38

58

46

66

54

74

64

82

80

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Table 63: DDR3L-1866/2133 Derating Values for 

t

IS/

t

IH – AC125/DC90-Based (Continued)

˂

˂

t

IS, 

˂

t

IH Derating (ps) – AC/DC-Based

CMD/ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

˂

t

IS

˂

t

IH

1.0

0

0

0

0

0

0

8

8

16

16

24

24

32

34

40

50

0.9

3

–3

3

–3

3

–3

11

5

19

13

27

21

35

31

43

47

0.8

6

–8

6

–8

6

–8

14

1

22

9

30

17

38

27

46

43

0.7

10

–13

10

–13

10

–13

18

–5

26

3

34

11

42

21

50

37

0.6

16

–20

16

–20

16

–20

24

–12

32

–4

40

4

48

14

56

30

0.5

15

–30

15

–30

15

–30

23

–22

31

–14

39

–6

47

4

55

20

0.4

13

–45

13

–45

13

–45

21

–37

29

–29

37

–21

45

–11

53

5

Table 64: DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL[AC]

) for Valid ADD/CMD

Transition

Slew Rate (V/ns)

DDR3L-800/1066/1333/1600

DDR3L-1866/2133

t

VAC at 160mV (ps)

t

VAC at 135mV (ps)

t

VAC at 135mV (ps)

t

VAC at 125mV (ps)

>2.0

200

213

200

205

2.0

200

213

200

205

1.5

173

190

178

184

1.0

120

145

133

143

0.9

102

130

118

129

0.8

80

111

99

111

0.7

51

87

75

89

0.6

13

55

43

59

0.5

Note 1

10

Note 1

18

<0.5

Note 1

10

Note 1

18

Note:

1. Rising input signal shall become equal to or greater than V

IH(AC)

 level and Falling input

signal shall become equal to or less than V

IL(AC)

 level.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Figure 34: Nominal Slew Rate and 

t

VAC for 

t

IS (Command and Address – Clock)

V

SS

Setup slew rate

rising signal

Setup slew rate

falling signal

¨

TF

¨

TR

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal

slew rate

V

REF

 to AC

region

tVAC

tVAC

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

Nominal

slew rate

V

REF

 to AC

region

V

REF(DC)

 - V

IL(AC)max

¨

TF

V

IH(AC)min

 - V

REF(DC)

¨

TR

Note:

1. The clock and the strobe are drawn on different time scales.

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Command and Address Setup, Hold, and Derating

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Figure 35: Nominal Slew Rate for 

t

IH (Command and Address – Clock)

V

SS

Hold slew rate

falling signal

Hold slew rate

rising signal 

ǻ

TR

ǻ

TF

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal

slew rate

DC to V

REF

region

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

DC to V

REF

region

Nominal

slew rate

V

REF(DC)

 - V

IL(DC)max

ǻ

TR

V

IH(DC)min

 - V

REF(DC)

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

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Command and Address Setup, Hold, and Derating

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Figure 36: Tangent Line for 

t

IS (Command and Address – Clock)

V

SS

Setup slew rate

rising signal

Setup slew rate

falling signal =

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Tangent

line

V

REF

 to AC

region

Nominal

line

tVAC

tVAC

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

V

REF

 to AC

region

Tangent

line

Nominal

line

Tangent line (V

IH(DC)min

 - V

REF(DC)

)

Tangent line (V

REF(DC)

 - V

IL(AC)max

)

¨

TR

¨

TR

¨

TF

¨

TF

Note:

1. The clock and the strobe are drawn on different time scales.

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Command and Address Setup, Hold, and Derating

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Figure 37: Tangent Line for 

t

IH (Command and Address – Clock)

V

SS

Hold slew rate

falling signal =

V

DDQ

 V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL( DC)max

V

IL( AC)max

Tangen t

line

DC to V

REF

region

Hold slew rate

rising signal

=

DQS

DQS#

CK#

CK

tIS

tIH

tIS

tIH

DC to V

REF

region

Tangen t

line

Nominal

line

Nominal

line

Tangent line (V

REF(DC)

 - V

IL(DC)max

)

Tangent line (V

IH(DC)min

 - V

REF(DC)

)

ǻ

TR

ǻ

TR

ǻ

TR

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

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Data Setup, Hold, and Derating

The total 

t

DS (setup time) and 

t

DH (hold time) required is calculated by adding the data

sheet 

t

DS (base) and 

t

DH (base) values (see Table 65 (page 110); values come from the

Electrical Characteristics and AC Operating Conditions table) to the 

ǻ

t

DS and 

ǻ

t

DH de-

rating values (see Table 66 (page 111), Table 67 (page 111), or Table 68 (page 112)) re-
spectively. Example: 

t

DS (total setup time) = 

t

DS (base) + 

ǻ

t

DS. For a valid transition, the

input signal has to remain above/below V

IH(AC)

/V

IL(AC)

 for some time 

t

VAC (see Table 69

(page 113)).

Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V

IH(AC)

/V

IL(AC)

) at the time of the rising clock transi-

tion), a valid input signal is still required to complete the transition and to reach
V

IH

/V

IL(AC)

. For slew rates that fall between the values listed in Table 66 (page 111), Ta-

ble 67 (page 111), or Table 68 (page 112), the derating values may obtained by linear
interpolation.

Setup (

t

DS) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

REF(DC)

 and the first crossing of V

IH(AC)min

. Setup (

t

DS) nominal slew

rate for a falling signal is defined as the slew rate between the last crossing of V

REF(DC)

and the first crossing of V

IL(AC)max

. If the actual signal is always earlier than the nominal

slew rate line between the shaded V

REF(DC)

-to-AC region, use the nominal slew rate for

derating value (see Figure 38 (page 114)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded V

REF(DC)

-to-AC region, the slew rate of a

tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 40 (page 116)).

Hold (

t

DH) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of V

IL(DC)max

 and the first crossing of V

REF(DC)

. Hold (

t

DH) nominal slew

rate for a falling signal is defined as the slew rate between the last crossing of V

IH(DC)min

and the first crossing of V

REF(DC)

. If the actual signal is always later than the nominal

slew rate line between the shaded DC-to-V

REF(DC)

 region, use the nominal slew rate for

derating value (see Figure 39 (page 115)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-V

REF(DC)

 region, the slew rate of a

tangent line to the actual signal from the DC-to-V

REF(DC)

 region is used for derating val-

ue (see Figure 41 (page 117)).

Table 65: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based

Symbol

800

1066

1333

1600

1866

2133

Unit

Reference

t

DS (base) AC160

90

40

ps

V

IH(AC)

/V

IL(AC)

t

DS (base) AC135

140

90

45

25

ps

t

DS (base) AC130

-

-

-

-

70

55

ps

t

DH (base) DC90

160

110

75

55

ps

t

DH (base) DC90

75

60

ps

Slew Rate Referenced

1

1

1

1

2

2

V/ns

4Gb: x4, x8, x16 DDR3L SDRAM

Data Setup, Hold, and Derating

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Table 66: DDR3L Derating Values for 

t

DS/

t

DH – AC160/DC90-Based

˂

˂

t

DS, 

˂

t

DH Derating (ps) – AC/DC-Based

DQ Slew

Rate V/ns

DQS, DQS# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

2.0

80

45

80

45

80

45

 

 

 

 

 

 

 

 

 

 

1.5

53

30

53

30

53

30

61

38

 

 

 

 

 

 

 

 

1.0

0

0

0

0

0

0

8

8

16

16

 

 

 

 

 

 

0.9

 

 –1

–3

–1

–3

7

5

15

13

23

21

 

 

 

 

0.8

 

 

 

 –3

–8

5

1

13

9

21

17

29

27

 

 

0.7

 

 

 

 

 

 –3

–5

11

3

19

11

27

21

35

37

0.6

 

 

 

 

 

 

 

 8

–4

16

4

24

14

32

30

0.5

 

 

 

 

 

 

 

 

 

 

4

6

12

4

20

20

0.4

 

 

 

 

 

 

 

 

 

 

 

 –8

–11

0

5

Table 67: DDR3L Derating Values for 

t

DS/

t

DH – AC135/DC90-Based

˂

t

DS, 

˂

t

DH Derating (ps) – AC/DC-Based

DQ Slew

Rate V/ns

DQS, DQS# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

2.0

68

45

68

45

68

45

 

 

 

 

 

 

 

 

 

 

1.5

45

30

45

30

45

30

53

38

 

 

 

 

 

 

 

 

1.0

0

0

0

0

0

0

8

8

16

16

 

 

 

 

 

 

0.9

 

 

2

–3

2

–3

10

5

18

13

26

21

 

 

 

 

0.8

 

 

 

 3

–8

11

1

19

9

27

17

35

27

 

 

0.7

 

 

 

 

 

 14

–5

22

3

30

11

38

21

46

37

0.6

 

 

 

 

 

 

 

 25

–4

33

4

41

14

49

30

0.5

 

 

 

 

 

 

 

 

 

 39

–6

37

4

45

20

0.4

 

 

 

 

 

 

 

 

 

 

 

 30

–11

38

5

4Gb: x4, x8, x16 DDR3L SDRAM

Data Setup, Hold, and Derating

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Table 68: DDR3L Derating Values for 

t

DS/

t

DH – AC130/DC90-Based at 2V/ns

Shaded cells indicate slew rate combinations not supported

˂

˂

t

DS, 

˂

t

DH Derating (ps) – AC/DC-Based

DQ Slew Rate V/ns

DQS, DQS# Differential Slew Rate

8.0 V/ns

7.0 V/ns

6.0 V/ns

5.0 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

˂

t

DS

˂

t

DH

4.0

33

23

33

23

33

23

3.5

28

19

28

19

28

19

28

19

3.0

22

15

22

15

22

15

22

15

22

15

2.5

13

9

13

9

13

9

13

9

13

9

2.0

0

0

0

0

0

0

0

0

0

0

1.5

–22

–15

–22

–15

–22

–15

–22

–15

–14

–7

1.0

–65

–45

–65

–45

–65

–45

–57

–37

–49

–29

0.9

–62

–48

–62

–48

–54

–40

–46

–32

–38

–24

0.8

–61

–53

–53

–45

–45

–37

–37

–29

–29

–19

0.7

–49

–50

–41

-42

–33

–34

–25

–24

–17

–8

0.6

–37

-49

–29

–41

–21

–31

–13

–15

0.5

–31

–51

–23

–41

–15

–25

0.4

–28

–56

–20

–40

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Table 69: DDR3L Minimum Required Time 

t

VAC Above V

IH(AC)

 (Below V

IL(AC)

) for Valid DQ Transition

Slew Rate (V/ns)

DDR3L-800/1066 160mV

(ps) min

DDR3L-800/1066/1333

135mV (ps) min

DDR3L-1866/2133

130mV (ps) min

>2.0

165

113

95

2.0

165

113

95

1.5

138

90

73

1.0

85

45

30

0.9

67

30

16

0.8

45

11

Note 1

0.7

16

Note 1

0.6

Note 1

Note 1

0.5

Note 1

Note 1

<0.5

Note 1

Note 1

Note:

1. Rising input signal shall become equal to or greater than V

IH(AC)

 level and Falling input

signal shall become equal to or less than V

IL(AC)

 level.

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Figure 38: Nominal Slew Rate and 

t

VAC for 

t

DS (DQ – Strobe)

V

SS

Setup slew rate
rising signal

Setup slew rate
falling signal

ǻ

TF

ǻ

TR

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal

slew rate

V

REF

 to AC

 region

tVAC

tVAC

tDH

tDS

DQS

DQS#

tDH

tDS

CK#

CK

V

REF

 to AC

 region

Nominal

slew rate

V

IH(AC)min

 - V

REF(DC)

ǻ

TR

V

REF(DC)

 - V

IL(AC)max

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

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Figure 39: Nominal Slew Rate for 

t

DH (DQ – Strobe)

V

SS

Hold slew rate
falling signal

Hold slew rate
rising signal

=

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Nominal 

slew rate

DC to V

REF

region

tDH

tDS

DQS

DQS#

tDH

tDS

CK#

CK

DC to V

REF

region

Nominal 

slew rate

V

REF(DC)

 - V

IL(DC)max

V

IL(DC)min

 - V

REF(DC)

ǻ

TR

ǻ

TF

ǻ

TF

ǻ

TR

Note:

1. The clock and the strobe are drawn on different time scales.

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Figure 40: Tangent Line for 

t

DS (DQ – Strobe)

V

SS

Setup slew rate

rising signal

Setup slew rate

falling signal =

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Tangent

line

V

REF

 to AC

region

Nominal

line

tVAC

tVAC

tDH

tDS

DQS

DQS#

tDH

tDS

CK#

CK

V

REF

 to AC

region

Tangent

line

Nominal

line

Tangent line (V

REF(DC)

 - V

IL(AC)max

)

Tangent line (V

IH(AC)min

 - V

REF(DC)

)

ǻ

TR

ǻ

TR

ǻ

TF

ǻ

TF

Note:

1. The clock and the strobe are drawn on different time scales.

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Figure 41: Tangent Line for 

t

DH (DQ – Strobe)

V

SS

Hold slew rate

falling signal

ǻ

TF

ǻ

TR

=

V

DDQ

V

IH(AC)min

V

IH(DC)min

V

REF(DC)

V

IL(DC)max

V

IL(AC)max

Tangent

line

DC to V

REF

region

Hold slew rate

rising signal

=

DQS

DQS#

CK#

CK

DC to V

REF

region

Tangent

line

Nominal

line

Nominal

line

Tangent line (V

IH(DC)min

 - V

REF(DC)

)

ǻ

TF

Tangent line (V

REF(DC)

 - V

IL(DC)max

)

ǻ

TR

tDS

tDH

tDS

tDH

Note:

1. The clock and the strobe are drawn on different time scales.

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Commands – Truth Tables

Table 70: Truth Table – Command

Notes 1–5 apply to the entire table

Function

Symbol

CKE

CS# RAS# CAS# WE#

BA

[2:0]

A

n

A12

A10

A[11,

9:0]

Notes

Prev.

Cycle

Next

Cycle

MODE REGISTER SET

MRS

H

H

L

L

L

L

BA

OP code

 

REFRESH

REF

H

H

L

L

L

H

V

V

V

V

V

 

Self refresh entry

SRE

H

L

L

L

L

H

V

V

V

V

V

6

Self refresh exit

SRX

L

H

H

V

V

V

V

V

V

V

V

6, 7

L

H

H

H

Single-bank PRECHARGE

PRE

H

H

L

L

H

L

BA

V

V

L

V

 

PRECHARGE all banks

PREA

H

H

L

L

H

L

V

V

H

V

 

Bank ACTIVATE

ACT

H

H

L

L

H

H

BA

Row address (RA)

 

WRITE

BL8MRS,
BC4MRS

WR

H

H

L

H

L

L

BA

RFU

V

L

CA

8

BC4OTF

WRS4

H

H

L

H

L

L

BA

RFU

L

L

CA

8

BL8OTF

WRS8

H

H

L

H

L

L

BA

RFU

H

L

CA

8

WRITE
with auto
precharge

BL8MRS,
BC4MRS

WRAP

H

H

L

H

L

L

BA

RFU

V

H

CA

8

BC4OTF

WRAPS4

H

H

L

H

L

L

BA

RFU

L

H

CA

8

BL8OTF

WRAPS8

H

H

L

H

L

L

BA

RFU

H

H

CA

8

READ

BL8MRS,
BC4MRS

RD

H

H

L

H

L

H

BA

RFU

V

L

CA

8

BC4OTF

RDS4

H

H

L

H

L

H

BA

RFU

L

L

CA

8

BL8OTF

RDS8

H

H

L

H

L

H

BA

RFU

H

L

CA

8

READ
with auto
precharge

BL8MRS,
BC4MRS

RDAP

H

H

L

H

L

H

BA

RFU

V

H

CA

8

BC4OTF

RDAPS4

H

H

L

H

L

H

BA

RFU

L

H

CA

8

BL8OTF

RDAPS8

H

H

L

H

L

H

BA

RFU

H

H

CA

8

NO OPERATION

NOP

H

H

L

H

H

H

V

V

V

V

V

9

Device DESELECTED

DES

H

H

H

X

X

X

X

X

X

X

X

10

Power-down entry

PDE

H

L

L

H

H

H

V

V

V

V

V

6

H

V

V

V

Power-down exit

PDX

L

H

L

H

H

H

V

V

V

V

V

6, 11

H

V

V

V

ZQ CALIBRATION LONG

ZQCL

H

H

L

H

H

L

X

X

X

H

X

12

ZQ CALIBRATION SHORT

ZQCS

H

H

L

H

H

L

X

X

X

L

X

 

Notes:

1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising

edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-
dependent.

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2. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be

held HIGH during any normal operation.

3. The state of ODT does not affect the states described in this table.
4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of

four mode registers.

5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 71 (page 120) for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC

are defined in MR0.

9. The purpose of the NOP command is to prevent the DRAM from registering any unwan-

ted commands. A NOP will not terminate an operation that is executing.

10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initializa-

tion) or ZQoper (ZQCL command after initialization).

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Table 71: Truth Table – CKE

Notes 1–2 apply to the entire table; see Table 70 (page 118) for additional command details

Current State

3

CKE

Command

5

(RAS#, CAS#, WE#, CS#)

Action

5

Notes

Previous Cycle

4

(

n

 - 1)

Present Cycle

4

(

n

)

Power-down

L

L

“Don’t Care”

Maintain power-down

 

L

H

DES or NOP

Power-down exit

 

Self refresh

L

L

“Don’t Care”

Maintain self refresh

 

L

H

DES or NOP

Self refresh exit

 

Bank(s) active

H

L

DES or NOP

Active power-down entry

 

Reading

H

L

DES or NOP

Power-down entry

 

Writing

H

L

DES or NOP

Power-down entry

 

Precharging

H

L

DES or NOP

Power-down entry

 

Refreshing

H

L

DES or NOP

Precharge power-down entry

 

All banks idle

H

L

DES or NOP

Precharge power-down entry

6

H

L

REFRESH

Self refresh

Notes:

1. All states and sequences not shown are illegal or reserved unless explicitly described

elsewhere in this document.

2.

t

CKE (MIN) means CKE must be registered at multiple consecutive positive clock edges.

CKE must remain at the valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of 

t

IS + 

t

CKE (MIN) + 

t

IH.

3. Current state = The state of the DRAM immediately prior to clock edge 

n

.

4. CKE (

n

) is the logic state of CKE at clock edge 

n

; CKE (

n

 - 1) was the state of CKE at the

previous clock edge.

5. COMMAND is the command registered at the clock edge (must be a legal command as

defined in Table 70 (page 118)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.

6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all tim-

ings from previous operations are satisfied. All self refresh exit and power-down exit pa-
rameters are also satisfied.

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Commands

DESELECT

The DESELT (DES) command (CS# HIGH) prevents new commands from being execu-
ted by the DRAM. Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affec-
ted.

ZQ CALIBRATION LONG

The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibra-
tion during a power-up initialization and reset sequence (see Figure 50 (page 137)).
This command may be issued at any time by the controller, depending on the system
environment. The ZQCL command triggers the calibration engine inside the DRAM. Af-
ter calibration is achieved, the calibrated values are transferred from the calibration en-
gine to the DRAM I/O, which are reflected as updated R

ON

 and ODT values.

The DRAM is allowed a timing window defined by either 

t

ZQinit or 

t

ZQoper to perform

a full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter 

t

ZQinit must be satisfied. When initialization is com-

plete, subsequent ZQCL commands require the timing parameter 

t

ZQoper to be satis-

fied.

ZQ CALIBRATION SHORT

The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibra-
tions to account for small voltage and temperature variations. A shorter timing window
is provided to perform the reduced calibration and transfer of values as defined by tim-
ing parameter 

t

ZQCS. A ZQCS command can effectively correct a minimum of 0.5% R

ON

and R

TT

 impedance error within 64 clock cycles, assuming the maximum sensitivities

specified in DDR3L 34 Ohm Output Driver Sensitivity (page 69).

ACTIVATE

The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA[2:0] inputs selects the bank, and the address
provided on inputs A[

n

:0] selects the row. This row remains open (or active) for accesses

until a PRECHARGE command is issued to that bank.

A PRECHARGE command must be issued before opening a different row in the same
bank.

READ

The READ command is used to initiate a burst read access to an active row. The address
provided on inputs A[2:0] selects the starting column address, depending on the burst
length and burst type selected (see Burst Order table for additional information). The
value on input A10 determines whether auto precharge is used. If auto precharge is se-
lected, the row being accessed will be precharged at the end of the READ burst. If auto

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precharge is not selected, the row will remain open for subsequent accesses. The value
on input A12 (if enabled in the mode register) when the READ command is issued de-
termines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted.

Table 72: READ Command Summary

Function

Symbol

CKE

CS# RAS# CAS# WE#

BA

[2:0]

A

n

A12

A10

A[11,

9:0]

Prev.

Cycle

Next

Cycle

READ

BL8MRS,

BC4MRS

RD

H

L

H

L

H

BA

RFU

V

L

CA

BC4OTF

RDS4

H

L

H

L

H

BA

RFU

L

L

CA

BL8OTF

RDS8

H

L

H

L

H

BA

RFU

H

L

CA

READ with
auto
precharge

BL8MRS,

BC4MRS

RDAP

H

L

H

L

H

BA

RFU

V

H

CA

BC4OTF

RDAPS4

H

L

H

L

H

BA

RFU

L

H

CA

BL8OTF

RDAPS8

H

L

H

L

H

BA

RFU

H

H

CA

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether auto
precharge is used. The value on input A12 (if enabled in the MR) when the WRITE com-
mand is issued determines whether BC4 (chop) or BL8 is used.

Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.

Table 73: WRITE Command Summary

Function

Symbol

CKE

CS# RAS# CAS# WE#

BA

[2:0]

A

n

A12

A10

A[11,

9:0]

Prev.

Cycle

Next

Cycle

WRITE

BL8MRS,

BC4MRS

WR

H

L

H

L

L

BA

RFU

V

L

CA

BC4OTF

WRS4

H

L

H

L

L

BA

RFU

L

L

CA

BL8OTF

WRS8

H

L

H

L

L

BA

RFU

H

L

CA

WRITE with
auto
precharge

BL8MRS,

BC4MRS

WRAP

H

L

H

L

L

BA

RFU

V

H

CA

BC4OTF

WRAPS4

H

L

H

L

L

BA

RFU

L

H

CA

BL8OTF

WRAPS8

H

L

H

L

L

BA

RFU

H

H

CA

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PRECHARGE

The PRECHARGE command is used to de-activate the open row in a particular bank or
in all banks. The bank(s) are available for a subsequent row access a specified time (

t

RP)

after the PRECHARGE command is issued, except in the case of concurrent auto pre-
charge. A READ or WRITE command to a different bank is allowed during a concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] se-
lect the bank; otherwise, BA[2:0] are treated as “Don’t Care.”

After a bank is precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A PRECHARGE command is treated as
a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging. However, the precharge period is determined by
the last PRECHARGE command issued to the bank.

REFRESH

The REFRESH command is used during normal operation of the DRAM and is analo-
gous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersis-
tent, so it must be issued each time a refresh is required. The addressing is generated by
the internal refresh controller. This makes the address bits a “Don’t Care” during a RE-
FRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs
(maximum when T

C

 

”

 85°C or 3.9μs maximum when T

C

 

”

 95°C). The REFRESH period

begins when the REFRESH command is registered and ends 

t

RFC (MIN) later.

To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight REFRESH com-
mands can be posted to any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is nine times the
maximum average interval refresh rate. Self refresh may be entered with up to eight RE-
FRESH commands being posted. After exiting self refresh (when entered with posted
REFRESH commands), additional posting of REFRESH commands is allowed to the ex-
tent that the maximum number of cumulative posted REFRESH commands (both pre-
and post-self refresh) does not exceed eight REFRESH commands.

At any given time, a maximum of 16 REFRESH commands can be issued within
2 x 

t

REFI.

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Figure 42: Refresh Mode

NOP

1

NOP

1

NOP

1

PRE

RA

Bank(s)

3

BA

REF

NOP

5

REF

2

NOP

5

ACT

NOP

5

One bank

All banks

t

CK

t

CH

t

CL

RA

t

RFC

2

t

RP

t

RFC (MIN)

T0

T1

T2

T3

T4

Ta0

Tb0

Ta1

Tb1

Tb2

Don’t Care

Indicates break
in time scale

Valid

5

Valid

5

Valid

5

CK

CK#

Command

CKE

Address

A10

BA[2:0]

DQ

4

DM

4

DQS, DQS#

4

Notes:

1. NOP commands are shown for ease of illustration; other valid commands may be possi-

ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 187)).

2. The second REFRESH is not required, but two back-to-back REFRESH commands are

shown.

3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one

bank is active (must precharge all active banks).

4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until 

t

RFC

(MIN) is satisfied.

SELF REFRESH

The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without ex-
ternal clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous oper-
ating range (see Input Clock Frequency Change (page 129)). All power supply inputs
(including V

REFCA

 and V

REFDQ

) must be maintained at valid levels upon entry/exit and

during self refresh mode operation. V

REFDQ

 may float or not drive V

DDQ

/2 while in self

refresh mode under the following conditions:

• V

SS

 < V

REFDQ

 < V

DD

 is maintained

• V

REFDQ

 is valid and stable prior to CKE going back HIGH

• The first WRITE operation may not occur earlier than 512 clocks after V

REFDQ

 is valid

• All other self refresh mode exit timing requirements are met

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Commands

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DLL Disable Mode

If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode, with a few notable exceptions:

• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS

WRITE latency (CWL = 6).

• DLL disable mode affects the read data clock-to-data strobe relationship (

t

DQSCK),

but not the read data-to-data strobe relationship (

t

DQSQ, 

t

QH). Special attention is

required to line up the read data with the controller time domain when the DLL is dis-
abled.

• In normal operation (DLL on), 

t

DQSCK starts from the rising clock edge AL + CL

cycles after the READ command. In DLL disable mode, 

t

DQSCK starts AL + CL - 1 cy-

cles after the READ command. Additionally, with the DLL disabled, the value of

t

DQSCK could be larger than 

t

CK.

The ODT feature (including dynamic ODT) is not supported during DLL disable mode.
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming R

TT,nom

 MR1[9, 6, 2] and R

TT(WR)

 MR2[10, 9] to 0 while in the DLL disable

mode.

Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (

t

CK [AVG] MAX

and 

t

CK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross this

clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh:

1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT

is turned off, and R

TT,nom

 and R

TT(WR)

 are High-Z), set MR1[0] to 1 to disable the

DLL.

2. Enter self refresh mode after 

t

MOD has been satisfied.

3. After 

t

CKSRE is satisfied, change the frequency to the desired clock rate.

4. Self refresh may be exited when the clock is stable with the new frequency for

t

CKSRX. After 

t

XS is satisfied, update the mode registers with appropriate values.

5. The DRAM will be ready for its next command in the DLL disable mode after the

greater of 

t

MRD or 

t

MOD has been satisfied. A ZQCL command should be issued

with appropriate timings met.

4Gb: x4, x8, x16 DDR3L SDRAM

Commands

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Figure 43: DLL Enable Mode to DLL Disable Mode

Command

T0

T1

Ta0

Ta1

Tb0

Tc0

Td0

Td1

Te0

Te1

Tf0

CK

CK#

ODT

9

Valid

1

Don’t Care

Valid1

SRE

3

NOP

MRS

2

NOP

SRX

4

MRS

5

Valid

1

NOP

NOP

Indicates break
in time scale

t

MOD

t

CKSRE

t

MOD

t

XS

t

CKESR 

CKE

t

CKSRX

8

7

6

Notes:

1. Any valid command.
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R

TT

 is in the High-Z state.

7. Change frequency.
8. Clock must be stable 

t

CKSRX.

9. Static LOW in the case that R

TT,nom

 or R

TT(WR)

 is enabled; otherwise, static LOW or HIGH.

A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 44 (page 127)).

1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT

is turned off, and R

TT,nom

 and R

TT(WR)

 are High-Z), enter self refresh mode.

2. After 

t

CKSRE is satisfied, change the frequency to the new clock rate.

3. Self refresh may be exited when the clock is stable with the new frequency for

t

CKSRX. After 

t

XS is satisfied, update the mode registers with the appropriate val-

ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait 

t

MRD, then set MR0[8]

to 1 to enable DLL RESET.

4. After another 

t

MRD delay is satisfied, update the remaining mode registers with

the appropriate values.

5. The DRAM will be ready for its next command in the DLL enable mode after the

greater of 

t

MRD or 

t

MOD has been satisfied. However, before applying any com-

mand or function requiring a locked DLL, a delay of 

t

DLLK after DLL RESET must

be satisfied. A ZQCL command should be issued with the appropriate timings
met.

4Gb: x4, x8, x16 DDR3L SDRAM

Commands

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Figure 44: DLL Disable Mode to DLL Enable Mode

CKE

T0

Ta0

Ta1

Tb0

Tc0

Tc1

Td0

Te0

Tf0

Tg0

CK

CK#

ODT

10

SRE

1

NOP

Command

NOP

SRX

2

MRS

3

MRS

4

MRS

5

Valid

6

Valid

Don’t Care

Indicates break
in time scale

t

CKSRE

t

CKSRX

9

8

7

t

XS

t

MRD

t

MRD

t

CKESR 

ODTLoff + 1 × 

t

CK

Th0

t

DLLK

Notes:

1. Enter SELF REFRESH.
2. Exit SELF REFRESH.
3. Wait 

t

XS, then set MR1[0] to 0 to enable DLL.

4. Wait 

t

MRD, then set MR0[8] to 1 to begin DLL RESET.

5. Wait 

t

MRD, update registers (CL, CWL, and write recovery may be necessary).

6. Wait 

t

MOD, any valid command.

7. Starting with the idle state.
8. Change frequency.
9. Clock must be stable at least 

t

CKSRX.

10. Static LOW in the case that R

TT,nom

 or R

TT(WR)

 is enabled; otherwise, static LOW or HIGH.

The clock frequency range for the DLL disable mode is specified by the parameter 

t

CK

(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.

DLL disable mode will affect the read data clock to data strobe relationship (

t

DQSCK)

but not the data strobe to data relationship (

t

DQSQ, 

t

QH). Special attention is needed to

line up read data to the controller time domain.

Compared to the DLL on mode where 

t

DQSCK starts from the rising clock edge AL + CL

cycles after the READ command, the DLL disable mode 

t

DQSCK starts AL + CL - 1 cycles

after the READ command.

WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.

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Commands

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Figure 45: DLL Disable 

t

DQSCK

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

Don’t Care

Transitioning Data

Valid

NOP

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

Address

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

DQ BL8 DLL on

DQS, DQS# DLL on

DQ BL8 DLL disable

DQS, DQS# DLL off

DQ BL8 DLL disable

DQS, DQS# DLL off

RL = AL + CL = 6 (CL = 6, AL = 0)

CL = 6 

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

t

DQSCK (DLL_DIS) MIN

t

DQSCK (DLL_DIS) MAX

RL (DLL_DIS) = AL + (CL - 1) = 5 

Table 74: READ Electrical Characteristics, DLL Disable Mode

Parameter

Symbol

Min

Max

Unit

Access window of DQS from CK, CK#

t

DQSCK (DLL_DIS)

1

10

ns

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Input Clock Frequency Change

When the DDR3 SDRAM is initialized, the clock must be stable during most normal
states of operation. This means that after the clock frequency has been set to the stable
state, the clock period is not allowed to deviate, except for what is allowed by the clock
jitter and spread spectrum clocking (SSC) specifications.

The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. It is illegal to
change the clock frequency outside of those two modes. For the self refresh mode con-
dition, when the DDR3 SDRAM has been successfully placed into self refresh mode and

t

CKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the

clock becomes a “Don’t Care,” changing the clock frequency is permissible if the new
clock frequency is stable prior to 

t

CKSRX. When entering and exiting self refresh mode

for the sole purpose of changing the clock frequency, the self refresh entry and exit
specifications must still be met.

The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or R

TT,nom

 and R

TT(WR)

 must be disabled via MR1 and MR2. This ensures

R

TT,nom

 and R

TT(WR)

 are in an off state prior to entering precharge power-down mode,

and CKE must be at a logic LOW. A minimum of 

t

CKSRE must occur after CKE goes LOW

before the clock frequency can change. The DDR3 SDRAM input clock frequency is al-
lowed to change only within the minimum and maximum operating frequency speci-
fied for the particular speed grade (

t

CK [AVG] MIN to 

t

CK [AVG] MAX). During the input

clock frequency change, CKE must be held at a stable LOW level. When the input clock
frequency is changed, a stable clock must be provided to the DRAM 

t

CKSRX before pre-

charge power-down may be exited. After precharge power-down is exited and 

t

XP has

been satisfied, the DLL must be reset via the MRS. Depending on the new clock fre-
quency, additional MRS commands may need to be issued. During the DLL lock time,
R

TT,nom

 and R

TT(WR)

 must remain in an off state. After the DLL lock time, the DRAM is

ready to operate with a new clock frequency.

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Input Clock Frequency Change

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Figure 46: Change Frequency During Precharge Power-Down

CK

CK#

Command

NOP

NOP

NOP

Address

CKE

DQ

DM

DQS, DQS#

NOP

t

CK

Enter precharge

power-down mode

Exit precharge

power-down mode

T0

T1

Ta0

Tc0

Tb0

T2

Don’t Care

t

CKE

t

XP

MRS

DLL RESET

Valid

Valid

NOP

t

CH

t

IH

t

IS

t

CL

Tc1

Td0

Te1

Td1

t

CKSRE

t

CH

b

t

CL

b

t

CK

b

t

CH

b

t

CL

b

t

CK

b

t

CH

b

t

CL

b

t

CK

b

t

CPDED

ODT

NOP

Te0

Previous clock frequency

New clock frequency

Frequency

change

Indicates break
in time scale

t

IH

t

IS

t

IH

t

IS

t

DLLK

t

AOFPD/

t

AOF

t

CKSRX

High-Z

High-Z

Notes:

1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2.

t

AOFPD and 

t

AOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-

tion (ODT) (page 197)for exact requirements).

3. If the R

TT,nom

 feature was enabled in the mode register prior to entering precharge

power-down mode, the ODT signal must be continuously registered LOW, ensuring R

TT

is in an off state. If the R

TT,nom

 feature was disabled in the mode register prior to enter-

ing precharge power-down mode, R

TT

 will remain in the off state. The ODT signal can

be registered LOW or HIGH in this case.

4Gb: x4, x8, x16 DDR3L SDRAM

Input Clock Frequency Change

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Write Leveling

For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topolo-
gy for the commands, addresses, control signals, and clocks. Write leveling is a scheme
for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK rela-
tionship at the DRAM with a simple feedback feature provided by the DRAM. Write lev-
eling is generally used as part of the initialization process, if required. For normal
DRAM operation, this feature must be disabled. This is the only DRAM operation where
the DQS functions as an input (to capture the incoming clock) and the DQ function as
outputs (to report the state of the clock). Note that nonstandard ODT schemes are re-
quired.

The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established by
this procedure helps ensure 

t

DQSS, 

t

DSS, and 

t

DSH specifications in systems that use

fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this
procedure is shown in Figure 47.

Figure 47: Write Leveling Concept

CK

CK#

Source

Differential DQS

Differential DQS

Differential DQS

DQ

DQ

CK

CK#

Destination

Destination

Push DQS to capture 

0–1 transition

T0

T1

T2

T3

T4

T5

T6

T7

T0

T1

T2

T3

T4

T5

T6

Tn

CK

CK#

T0

T1

T2

T3

T4

T5

T6

Tn

Don’t Care

1

1

0

0

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the
lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS
and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a
x16 enable each byte lane to be leveled independently.

The write leveling mode register interacts with other mode registers to correctly config-
ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-
ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst
length, and so forth need to be selected as well. This interaction is shown in Table 75. It
should also be noted that when the outputs are enabled during write leveling mode, the
DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write
leveling mode, only the DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the ODT ball.

Table 75: Write Leveling Matrix

Note 1 applies to the entire table

MR1[7]

MR1[12]

MR1[2, 6, 9]

DRAM

ODT Ball

DRAM

R

TT,nom

DRAM State

Case Notes

Write

Leveling

Output

Buffers

R

TT,nom

Value

DQS

DQ

Disabled

See normal operations

Write leveling not enabled

0

 

Enabled

(1)

Disabled

(1)

n/a

Low

Off

Off

DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated

1

2



˖



˖



˖



˖

, or

120

˖

High

On

DQS not receiving: terminated by R

TT

Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated

2

Enabled

(0)

n/a

Low

Off

DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated

3

3



˖



˖

, or

120

˖

High

On

DQS receiving: terminated by R

TT

Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated

4

Notes:

1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a

dual-rank module and on the rank not being leveled or on any rank of a module not
being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of
a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is
generally used when DRAM are on the rank that is being leveled.

2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,

and all R

TT,nom

 values are allowed. This simulates a normal standby state to DQS.

3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and

only some R

TT,nom

 values are allowed. This simulates a normal write state to DQS.

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Write Leveling

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Write Leveling Procedure

A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, as-
suming the other programable features (MR0, MR1, MR2, and MR3) are first set and the
DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a
High-Z state to an undefined driving state, so the DQ bus should not be driven. During
write leveling mode, only the NOP or DES commands are allowed. The memory con-
troller should attempt to level only one rank at a time; thus, the outputs of other ranks
should be disabled by setting MR1[12] to 1 in the other ranks. The memory controller
may assert ODT after a 

t

MOD delay, as the DRAM will be ready to process the ODT tran-

sition. ODT should be turned on prior to DQS being driven LOW by at least ODTLon
delay (WL - 2 

t

CK), provided it does not violate the aforementioned 

t

MOD delay require-

ment.

The memory controller may drive DQS LOW and DQS# HIGH after 

t

WLDQSEN has

been satisfied. The controller may begin to toggle DQS after 

t

WLMRD (one DQS toggle

is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a
HIGH state to a LOW state, then both transition back to their original states). At a mini-
mum, ODTLon and 

t

AON must be satisfied at least one clock prior to DQS toggling.

After 

t

WLMRD and a DQS LOW preamble (

t

WPRE) have been satisfied, the memory

controller may provide either a single DQS toggle or multiple DQS toggles to sample CK
for a given DQS-to-CK skew. Each DQS toggle must not violate 

t

DQSL (MIN) and 

t

DQSH

(MIN) specifications. 

t

DQSL (MAX) and 

t

DQSH (MAX) specifications are not applicable

during write leveling mode. The DQS must be able to distinguish the CK’s rising edge
within 

t

WLS and 

t

WLH. The prime DQ will output the CK’s status asynchronously from

the associated DQS rising edge CK capture within 

t

WLO. The remaining DQ that always

drive LOW when DQS is toggling must be LOW within 

t

WLOE after the first 

t

WLO is sat-

isfied (the prime DQ going LOW). As previously noted, DQS is an input and not an out-
put during this process. Figure 48 (page 134) depicts the basic timing parameters for
the overall write leveling procedure.

The memory controller will most likely sample each applicable prime DQ state and de-
termine whether to increment or decrement its DQS delay setting. After the memory
controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memo-
ry controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting is locked, leveling for the rank will have been achieved, and the write leveling
mode for the rank should be disabled or reprogrammed (if write leveling of another
rank follows).

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Figure 48: Write Leveling Sequence

CK

CK#

Command

T1

T2

Early remaining DQ

Late remaining DQ

t

WLOE

NOP

2

NOP

MRS

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

WLS

t

WLH

Don’t Care

Undefined Driving Mode

Indicates break
in time scale

Prime DQ

5

Differential DQS

4

ODT

t

MOD

t

DQSL

3

t

DQSL

3

t

DQSH

3

t

DQSH

3

t

WLO

t

WLMRD

t

WLDQSEN

t

WLO

t

WLO

t

WLO

Notes:

1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements 

t

DQSH (MIN) and 

t

DQSL

(MIN) as defined for regular writes. The maximum pulse width is system-dependent.

4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are

the zero crossings. The solid line represents DQS; the dotted line represents DQS#.

5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ

are driven LOW and remain in this state throughout the leveling procedure.

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Write Leveling Mode Exit Procedure

After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 49 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
driving the DQS signals after 

t

WLO (MAX) delay plus enough delay to enable the memo-

ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until 

t

MOD

after the MRS command (at Te1).

The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies 

t

IS, ODT must be kept LOW (at

~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After 

t

MOD is satisfied (at Te1), any valid com-

mand may be registered by the DRAM. Some MRS commands may be issued after 

t

MRD

(at Td1).

Figure 49: Write Leveling Exit Procedure

NOP

CK

T0

T1

T2

Ta0

Tb0

Tc0

Tc1

Tc2

Td0

Td1

Te0

Te1

CK#

Command

ODT

R

TT(DQ)

NOP

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Address

MR1

Valid

Valid

Valid

Valid

Don’t Care

Transitioning

R

TT

 DQS, R

TT

 DQS#

R

TT,nom

Undefined Driving Mode

t

AOF (MAX)

t

MRD

Indicates break
in time scale

DQS, DQS#

CK = 1

DQ

t

IS

t

AOF (MIN)

t

MOD

t

WLO + 

t

WLOE

ODTLoff

Note:

1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing

CK HIGH just after the T0 state.

4Gb: x4, x8, x16 DDR3L SDRAM

Write Leveling

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Initialization

The following sequence is required for power-up and initialization, as shown in Figure
50 (page 137):

1. Apply power. RESET# is recommended to be below 0.2 × V

DDQ

 during power ramp

to ensure the outputs remain disabled (High-Z) and ODT off (R

TT

 is also High-Z).

All other inputs, including ODT, may be undefined.

During power-up, either of the following conditions may exist and must be met:

• Condition A:

– V

DD

 and V

DDQ

 are driven from a single-power converter output and are

ramped with a maximum delta voltage between them of 

ǻ

”

 300mV. Slope re-

versal of any power supply signal is allowed. The voltage levels on all balls oth-
er than V

DD

, V

DDQ

, V

SS

, V

SSQ

 must be less than or equal to V

DDQ

 and V

DD

 on

one side, and must be greater than or equal to V

SSQ

 and V

SS

 on the other side.

– Both V

DD

 and V

DDQ

 power supplies ramp to V

DD,min

 and V

DDQ,min

 within

t

V

DDPR

 = 200ms.

– V

REFDQ

 tracks V

DD

 × 0.5, V

REFCA

 tracks V

DD

 × 0.5.

– V

TT

 is limited to 0.95V when the power ramp is complete and is not applied

directly to the device; however, 

t

VTD should be greater than or equal to 0 to

avoid device latchup.

• Condition B:

– V

DD

 may be applied before or at the same time as V

DDQ

.

– V

DDQ

 may be applied before or at the same time as V

TT

, V

REFDQ

, and V

REFCA

.

– No slope reversals are allowed in the power supply ramp for this condition.

2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled

(High-Z). After the power is stable, RESET# must be LOW for at least 200μs to be-
gin the initialization process. ODT will remain in the High-Z state while RESET# is
LOW and until CKE is registered HIGH.

3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500μs (minus one clock) with CKE LOW.
5. After the CKE LOW time, CKE may be brought HIGH (synchronously) and only

NOP or DES commands may be issued. The clock must be present and valid for at
least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least

t

IS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be

continuously registered HIGH until the full initialization process is complete.

6. After CKE is registered HIGH and after 

t

XPR has been satisfied, MRS commands

may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applica-
ble settings (provide LOW to BA2 and BA0 and HIGH to BA1).

7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling

the DLL and configuring ODT.

9. Issue an MRS command to MR0 with the applicable settings, including a DLL RE-

SET command. 

t

DLLK (512) cycles of clock input are required to lock the DLL.

10. Issue a ZQCL command to calibrate R

TT

 and R

ON

 values for the process voltage

temperature (PVT). Prior to normal operation, 

t

ZQinit must be satisfied.

11. When 

t

DLLK and 

t

ZQinit have been satisfied, the DDR3 SDRAM will be ready for

normal operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Initialization

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Figure 50: Initialization Sequence

CKE

R

TT

BA[2:0]

All voltage
supplies valid
and stable

T = 200μs (MIN)

DM

DQS

Address

A10

CK

CK#

t

CL

Command

NOP

T0

Ta0

Don’t Care

t

CL

t

IS

t

CK

ODT

DQ

Tb0

t

DLLK

MR1 with

DLL enable

MR0 with

DLL reset

t

MRD

t

MOD

MRS

MRS

BA0 = H
BA1 = L
BA2 = L

BA0 = L
BA1 = L
BA2 = L

Code Code 

Code Code 

Valid

Valid

Valid

Valid

Normal

operation

MR2

MR3

t

MRD

t

MRD

MRS

MRS

BA0 = L
BA1 = H
BA2 = L

BA0 = H
BA1 = H
BA2 = L

Code Code 

Code Code 

Tc0

Td0

V

TT

V

REF

V

DDQ

V

DD

RESET#

T = 500μs (MIN)

t

CKSRX

Stable and
valid clock

Valid

Power-up
ramp

T (MAX) = 200ms

DRAM ready for 
external commands

T1

t

ZQinit

ZQ calibration

A10 = H

ZQCL

t

IS

See power-up

conditions 

in the 

initialization

sequence text, 

set up 1 

t

XPR

Valid

t

IOZ = 20ns

Indicates break
in time scale

T (MIN) = 10ns

t

VTD

4Gb: x4, x8, x16 DDR3L SDRAM

Initialization

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Voltage Initialization/Change

If the SDRAM is powered up and initialized for the 1.35V operating voltage range, volt-
age can be increased to the 1.5V operating range provided the following conditions are
met (See Figure 51 (page 139)):

• Just prior to increasing the 1.35V operating voltages, no further commands are issued,

other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.

• The 1.5V operating voltages are stable prior to issuing new commands, other than

NOPs or COMMAND INHIBITs.

• The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to

any READ command.

• The ZQ calibration is performed. 

t

ZQinit must be satisfied after the 1.5V operating

voltages are stable and prior to any READ command.

If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage
can be reduced to the 1.35V operation range provided the following conditions are met
(See Figure 51 (page 139)) :

• Just prior to reducing the 1.5V operating voltages, no further commands are issued,

other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.

• The 1.35V operating voltages are stable prior to issuing new commands, other than

NOPs or COMMAND INHIBITs.

• The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to

any READ command.

• The ZQ calibration is performed. 

t

ZQinit must be satisfied after the 1.35V operating

voltages are stable and prior to any READ command.

4Gb: x4, x8, x16 DDR3L SDRAM

Voltage Initialization/Change

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V

DD

 Voltage Switching

After the DDR3L DRAM is powered up and initialized, the power supply can be altered
between the DDR3L and DDR3 levels, provided the sequence in Figure 51 is main-
tained.

Figure 51: V

DD

 Voltage Switching

(

)

(

)

(

)

(

)

CKE

R

TT

BA

(

)

(

)

(

)

(

)

CK, CK#

Command

Note 1 

Note 1 

(

)

(

)

(

)

(

)

Td

Tc

Tg

Don’t Care

(

)

(

)

(

)

(

)

(

)

(

)

t

IS

ODT

(

)

(

)

(

)

(

)

Th

t

MRD

t

MOD

(

)

(

)

(

)

(

)

MRS

MRS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

MRD

t

MRD

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

MRS

MR0

MR1

MR3

MRS

MR2

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Ti

Tj

Tk

(

)

(

)

(

)

(

)

RESET#

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

T = 500μs

(

)

(

)

(

)

(

)

(

)

(

)

Te

Ta

Tb

Tf

(

)

(

)

(

)

(

)

ZQCL

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

IS

Static LOW in case R

TT,nom

 is enabled at time Tg, otherwise static HIGH or LOW 

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

IS

t

IS

t

XPR

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Time break

T

MIN

 = 10ns

T

MIN

 = 10ns

T

MIN

 = 10ns

T

MIN

 = 

200μs 

t

CKSRX

V

DD

, V

DDQ

 (DDR3)

(

)

(

)

(

)

(

)

t

DLLK

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

t

ZQinit

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

V

DD

, V

DDQ

 (DDR3L)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Valid

Valid

Valid

Valid

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Note:

1. From time point Td until Tk, NOP or DES commands must be applied between MRS and

ZQCL commands.

4Gb: x4, x8, x16 DDR3L SDRAM

Voltage Initialization/Change

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Mode Registers

Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.

Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode register’s variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed cor-
rectly.

The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (

t

RP is satisfied and no data bursts are in progress). After an MRS com-

mand has been issued, two parameters must be satisfied: 

t

MRD and 

t

MOD. The control-

ler must wait 

t

MRD before initiating any subsequent MRS commands.

Figure 52: MRS to MRS Command Timing (

t

MRD)

Valid

Valid

MRS

1

MRS

2

NOP

NOP

NOP

NOP

T0

T1

T2

Ta0

Ta1

Ta2

CK#

CK

Command

Address

CKE

3

Don’t Care

Indicates break
in time scale

t

MRD

Notes:

1. Prior to issuing the MRS command, all banks must be idle and precharged, 

t

RP (MIN)

must be satisfied, and no data bursts can be in progress.

2.

t

MRD specifies the MRS to MRS command minimum cycle time.

3. CKE must be registered HIGH from the MRS command until 

t

MRSPDEN (MIN) (see Pow-

er-Down Mode (page 187)).

4. For a CAS latency change, 

t

XPDLL timing must be met before any non-MRS command.

The controller must also wait 

t

MOD before initiating any non-MRS commands (exclud-

ing NOP and DES). The DRAM requires 

t

MOD in order to update the requested features,

with the exception of DLL RESET, which requires additional time. Until 

t

MOD has been

satisfied, the updated features are to be assumed unavailable.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Registers

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Figure 53: MRS to nonMRS Command Timing (

t

MOD)

Valid

Valid

MRS

non

MRS

NOP

NOP

NOP

NOP

T0

T1

T2

Ta0

Ta1

Ta2

CK#

CK

Command

Address

CKE

Valid

Old 

setting

New 

setting

Indicates break
in time scale

t

MOD

Updating setting

Don’t Care

Notes:

1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, 

t

RP

must be satisfied, and no data bursts can be in progress).

2. Prior to Ta2 when 

t

MOD (MIN) is being satisfied, no commands (except NOP/DES) may be

issued.

3. If R

TT

 was previously enabled, ODT must be registered LOW at T0 so that ODTL is satis-

fied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until

t

MODmin is satisfied at Ta2.

4. CKE must be registered HIGH from the MRS command until 

t

MRSPDEN (MIN), at which

time power-down may occur (see Power-Down Mode (page 187)).

Mode Register 0 (MR0)

The base register, mode register 0 (MR0), is used to define various DDR3 SDRAM modes
of operation. These definitions include the selection of a burst length, burst type, CAS
latency, operating mode, DLL RESET, write recovery, and precharge power-down mode
(see Figure 54 (page 142)).

Burst Length

Burst length is defined by MR0[1:0]. Read and write accesses to the DDR3 SDRAM are
burst-oriented, with the burst length being programmable to 4 (chop) mode, 8 (fixed)
mode, or selectable using A12 during a READ/WRITE command (on-the-fly). The burst
length determines the maximum number of column locations that can be accessed for
a given READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE
command, if A12 = 0, then BC4 mode is selected. If A12 = 1, then BL8 mode is selected.
Specific timing diagrams, and turnaround between READ/WRITE, are shown in the
READ/WRITE sections of this document.

When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[

i

:2] when the burst length is set to 4 and by A[

i

:3] when the burst

length is set to 8, where A

i

 is the most significant column address bit for a given config-

uration. The remaining (least significant) address bit(s) is (are) used to select the start-

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.

Figure 54: Mode Register 0 (MR0) Definitions

BL

CAS# latency

CL

BT

PD

A9

A7 A6 A5 A4 A3

A8

A2 A1 A0

Mode register 0 (MR0)

Address bus

9

7

6

5

4

3

8

2

1

0

A10

A12 A11

BA0

BA1

10

11

12

15–13

M3

 

0

1

READ Burst Type

 

Sequential (nibble)

Interleaved

CAS Latency

Reserved

5

6

7

8

9

10

11

12

13

14

M2

0

0

0

0

0

0

0

0

1

1

1

M4

0

1

0

1

0

1

0

1

0

1

0

M5

0

0

1

1

0

0

1

1

0

0

1

M6

0

0

0

0

1

1

1

1

0

0

0

17

DLL

Write Recovery

16

5

6

7

8

10

12

14

WR

0

0

M12

1

Precharge PD

DLL off (slow exit)

DLL on (fast exit)

BA2

18

0

1

Burst Length

Fixed BL8

4 or 8 (on-the-fly via A12)

Fixed BC4 (chop)

Reserved

M0

0

1

0

1

M1

0

0

1

1

M9

0

1

0

1

0

1

0

1

M10

0

0

1

1

0

0

1

1

M11

0

0

0

0

1

1

1

1

M14

 

0

1

0

1

M15

0

0

1

1

Mode Register 

Mode register 0 (MR0)

Mode register 1 (MR1)

Mode register 2 (MR2)

Mode register 3 (MR3)

A[15:13]

16

0

1

0

1

M8

0

1

DLL Reset

No

Yes

Note:

1. MR0[18, 15:13, 7] are reserved for future use and must be programmed to 0.

Burst Type

Accesses within a given burst can be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR0[3] (see Figure 54 (page 142)). The order-
ing of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are re-
stricted to nibble (BC4) or word (BL8) boundaries.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Table 76: Burst Order

Burst

Length

READ/
WRITE

Starting

Column Address

(A[2, 1, 0])

Burst Type = Sequential

(Decimal)

Burst Type = Interleaved

(Decimal)

Notes

4 (chop)

READ

0 0 0

0, 1, 2, 3, Z, Z, Z, Z

0, 1, 2, 3, Z, Z, Z, Z

1, 2

0 0 1

1, 2, 3, 0, Z, Z, Z, Z

1, 0, 3, 2, Z, Z, Z, Z

1, 2

0 1 0

2, 3, 0, 1, Z, Z, Z, Z

2, 3, 0, 1, Z, Z, Z, Z

1, 2

0 1 1

3, 0, 1, 2, Z, Z, Z, Z

3, 2, 1, 0, Z, Z, Z, Z

1, 2

1 0 0

4, 5, 6, 7, Z, Z, Z, Z

4, 5, 6, 7, Z, Z, Z, Z

1, 2

1 0 1

5, 6, 7, 4, Z, Z, Z, Z

5, 4, 7, 6, Z, Z, Z, Z

1, 2

1 1 0

6, 7, 4, 5, Z, Z, Z, Z

6, 7, 4, 5, Z, Z, Z, Z

1, 2

1 1 1

7, 4, 5, 6, Z, Z, Z, Z

7, 6, 5, 4, Z, Z, Z, Z

1, 2

WRITE

0 V V

0, 1, 2, 3, X, X, X, X

0, 1, 2, 3, X, X, X, X

1, 3, 4

1 V V

4, 5, 6, 7, X, X, X, X

4, 5, 6, 7, X, X, X, X

1, 3, 4

8 (fixed)

READ

0 0 0

0, 1, 2, 3, 4, 5, 6, 7

0, 1, 2, 3, 4, 5, 6, 7

1

0 0 1

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

1

0 1 0

2, 3, 0, 1, 6, 7, 4, 5

2, 3, 0, 1, 6, 7, 4, 5

1

0 1 1

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

1

1 0 0

4, 5, 6, 7, 0, 1, 2, 3

4, 5, 6, 7, 0, 1, 2, 3

1

1 0 1

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

1

1 1 0

6, 7, 4, 5, 2, 3, 0, 1

6, 7, 4, 5, 2, 3, 0, 1

1

1 1 1

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

1

WRITE

V V V

0, 1, 2, 3, 4, 5, 6, 7

0, 1, 2, 3, 4, 5, 6, 7

1, 3

Notes:

1. Internal READ and WRITE operations start at the same point in time for BC4 as they do

for BL8.

2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input

pins.

4. X = “Don’t Care.”

DLL RESET

DLL RESET is defined by MR0[8] (see Figure 54 (page 142)). Programming MR0[8] to 1
activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value
of 0 after the DLL RESET function has been initiated.

Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
stable for 512 (

t

DLLK) clock cycles before a READ command can be issued. This is to

allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization can result in invalid output timing specifications, such as

t

DQSCK timings.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Write Recovery

WRITE recovery time is defined by MR0[11:9] (see Figure 54 (page 142)). Write recovery
values of 5, 6, 7, 8, 10, or 12 can be used by programming MR0[11:9]. The user is re-
quired to program the correct value of write recovery, which is calculated by dividing

t

WR (ns) by 

t

CK (ns) and rounding up a noninteger value to the next integer:

WR (cycles) = roundup (

t

WR (ns)/

t

CK (ns)).

Precharge Power-Down (Precharge PD)

The precharge power-down (precharge PD) bit applies only when precharge power-
down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge
power-down, providing a lower standby current mode; however, 

t

XPDLL must be satis-

fied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge
power-down mode to enable a faster exit of precharge power-down mode; however, 

t

XP

must be satisfied when exiting (see Power-Down Mode (page 187)).

CAS Latency (CL)

CAS latency (CL) is defined by MR0[6:4], as shown in Figure 54 (page 142). CAS latency
is the delay, in clock cycles, between the internal READ command and the availability of
the first bit of output data. CL can be set to 5 through 14. DDR3 SDRAM do not support
half-clock latencies.

Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge 

n

, and the CAS latency is 

m

 clocks, the data will be available nomi-

nally coincident with clock edge 

n

 + 

m.

 See Speed Bin Tables for the CLs supported at

various operating frequencies.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 0 (MR0)

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Figure 55: READ Latency

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ

DQS, DQS#

DQS, DQS#

T0

T1

T2

T3

T4

T5

T6

T7

T8

Don’t Care

CK

CK#

Command

DQ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

DI

 n + 3

DI

 n + 1

DI

 n + 2

DI

 n + 4

DI

n

DI

n

NOP

NOP

AL = 0, CL = 8

AL = 0, CL = 6

Transitioning Data

Notes:

1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal 

t

DQSCK and nominal 

t

DSDQ.

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Mode Register 0 (MR0)

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Mode Register 1 (MR1)

The mode register 1 (MR1) controls additional functions and features not available in
the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
only), DLL ENABLE/DLL DISABLE, R

TT,nom

 value (ODT), WRITE LEVELING, POSTED

CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are control-
led via the bits shown in Figure 56 (page 146). The MR1 register is programmed via the
MRS command and retains the stored information until it is reprogrammed, until RE-
SET# goes LOW, or until the device loses power. Reprogramming the MR1 register will
not alter the contents of the memory array, provided it is performed correctly.

The MR1 register must be loaded when all banks are idle and no bursts are in progress.
The controller must satisfy the specified timing parameters 

t

MRD and 

t

MOD before ini-

tiating a subsequent operation.

Figure 56: Mode Register 1 (MR1) Definition

AL

R

TT

Q Off

A9

A7 A6 A5 A4 A3

A8

A2

A1 A0

Mode register 1 (MR1)

Address bus

9

7

6

5

4

3

8

2

1

0

A10

A12 A11

BA0

BA1

10

11

12

13

M0

0

1

DLL Enable

Enable (normal)

Disable

M5

0

0

1

1

Output Drive St rength

RZQ/6 (40

ȍ

 [NOM])

RZQ/7 (34

ȍ

 [NOM])

Reserved

Reserved

14

WL

01

01

1

0

ODS DLL

R

TT

TDQS

M12

0

1

Q Off

Enabled

Disabled

BA2

15

01

M7

0

1

Write Levelization

Disable (normal)

Enable

Additive Latency (AL)

Disabled (AL = 0)

AL = CL - 1

AL = CL - 2

Reserved

M3

0

1

0

1

M4

0

0

1

1

R

TT

ODS

M1

0

1

0

1

A13

A14

A15

16

17

18

01

M11

0

1

TDQS 

Disabled

Enabled

01

01

R

TT,nom

 (ODT) 2

Non- Writes

R

TT,nom 

disabled

RZQ/4 (60

ȍ

 [NOM])

RZQ/2 (120

ȍ

 [NOM])

RZQ/6 (40

ȍ

 [NOM])

RZQ/12 (20

ȍ

 [NOM])

RZQ/8 (30

ȍ

 [NOM])

Reserved

Reserved

R

TT,nom 

(ODT) 3

Writes

R

TT,nom 

disabled

RZQ/4 (60

ȍ

 [NOM])

RZQ/2 (120

ȍ

 [NOM])

RZQ/6 (40

ȍ

 [NOM])

n/a

n/a

Reserved

Reserved

M2

0

1

0

1

0

1

0

1

M6

0

0

1

1

0

0

1

1

M9

0

0

0

0

1

1

1

1

Mode Register 

Mode register set 0 (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

M16

 

0

1

0

1

M17 

0

0

1

1

Notes:

1. MR1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.
2. During write leveling, if MR1[7] and MR1[12] are 1, then all R

TT,nom

 values are available

for use.

3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only R

TT,nom

 write values

are available for use.

DLL Enable/DLL Disable

The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE
command, as shown in Figure 56 (page 146). The DLL must be enabled for normal oper-
ation. DLL enable is required during power-up initialization and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debugging or evalua-
tion. Enabling the DLL should always be followed by resetting the DLL using the appro-
priate LOAD MODE command.

If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-
bled when entering SELF REFRESH operation and is automatically re-enabled and reset
upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self re-

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 1 (MR1)

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fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until
it is re-enabled and reset.

The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:

• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks

When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see DLL Disable Mode (page 125)). Disabling
the DLL also implies the need to change the clock frequency (see Input Clock Frequen-
cy Change (page 129)).

Output Drive Strength

The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/7 (34

ȍ

 [NOM]) is the primary output

driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-
pedance, an external precision resistor (RZQ) is connected between the ZQ ball and
V

SSQ

. The value of the resistor must be 240

ȍ

 ±1%.

The output impedance is set during initialization. Additional impedance calibration up-
dates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.

To meet the 34

ȍ

 specification, the output drive strength must be set to 34

ȍ

 during initi-

alization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset proce-
dure.

OUTPUT ENABLE/DISABLE

The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 (page
146). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the
normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during I

DD

 characterization of the READ current and during 

t

DQSS margining (write

leveling) only.

TDQS Enable

Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (R

TT

) and may be useful in some system configurations.

TDQS is not supported in x4 or x16 configurations. When enabled via the mode register
(MR1[11]), the R

TT

 that is applied to DQS and DQS# is also applied to TDQS and TDQS#.

In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-
tion resistance R

TT

 only. The OUTPUT DATA STROBE function of RDQS is not provided

by TDQS; thus, R

ON

 does not apply to TDQS and TDQS#. The TDQS and DM functions

share the same ball. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is pro-
vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 1 (MR1)

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SDRAM configuration only and must be disabled via the mode register for the x4 and
x16 configurations.

On-Die Termination

ODT resistance R

TT,nom

 is defined by MR1[9, 6, 2] (see Figure 56 (page 146)). The R

TT

termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple R

TT

 termination values based on RZQ/

n

 where 

n

 can be 2, 4, 6, 8, or

12 and RZQ is 240

ȍ

.

Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. R

TT,nom

 termination is allowed any time after the DRAM is ini-

tialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT (R

TT(WR)

) enabled temporarily re-

places R

TT,nom

 with R

TT(WR)

.

The actual effective termination, R

TT(EFF)

, may be different from the R

TT

 targeted due to

nonlinearity of the termination. For R

TT(EFF)

 values and calculations (see On-Die Termi-

nation (ODT) (page 197)).

The ODT feature is designed to improve signal integrity of the memory channel by ena-
bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devi-
ces. The ODT input control pin is used to determine when R

TT

 is turned on (ODTL on)

and off (ODTL off ), assuming ODT has been enabled via MR1[9, 6, 2].

Timings for ODT are detailed in On-Die Termination (ODT) (page 197).

WRITE LEVELING

The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 56 (page 146).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.

The fly-by topology benefits from a reduced number of stubs and their lengths. Howev-
er, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining

t

DQSS, 

t

DSS, and 

t

DSH specifications without supporting write leveling in systems

which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 131).

POSTED CAS ADDITIVE Latency

POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus
efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL,
as shown in Figure 57 (page 149). MR1[4, 3] enable the user to program the DDR3
SDRAM with AL = 0, CL - 1, or CL - 2.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 1 (MR1)

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Figure 57: READ Latency (AL = 5, CL = 6)

CK

CK#

Command

DQ

DQS, DQS#

ACTIVE n

T0

T1

Don’t Care

NOP

NOP

T6

T12

NOP

READ n

T13

NOP

DO

n + 3

DO

n + 2

DO

n + 1

RL = AL + CL = 11

T14

NOP

DO

n

t

RCD (MIN)

AL = 5

CL = 6

T11

BC4

Indicates break
in time scale

Transitioning Data

T2

NOP

Mode Register 2 (MR2)

The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AU-
TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(R

TT(WR)

). These functions are controlled via the bits shown in Figure 58. The MR2 is

programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time 

t

MRD and 

t

MOD before initiating a sub-

sequent operation.

Figure 58: Mode Register 2 (MR2) Definition

0

0

0RGH5HJLVWHU

0RGHUHJLVWHUVHW05

0RGHUHJLVWHUVHW05

0RGHUHJLVWHUVHW05

0RGHUHJLVWHUVHW05

$

$ $ $ $ $

$

$ $ $

0RGHUHJLVWHU05

$GGUHVVEXV

$

$ $

%$

%$

&:/

%$

$65

$

$

$

657

5

77:5

0


$XWR6HOI5HIUHVK

2SWLRQDO

'LVDEOHG0DQXDO

(QDEOHG$XWRPDWLF

0


6HOI5HIUHVK7HPSHUDWXUH

1RUPDOƒ&WRƒ&
([WHQGHG •ƒ&WRƒ&

&$6:ULWH/DWHQF\&:/

&.W&.•QV

&.QV!W&.•QV
&.QV!W&.•QV

&.QV!W&.•QV
&.QV!W&.QV

&.QV!

W

&.•QV

5HVHUYHG
5HVHUYHG

0








0








0








0




0




'\QDPLF2'7

5

77:5

5

77:5

GLVDEOHG

5=4:>120@
5=4:>120@

5HVHUYHG

•

Note:

1. MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 2 (MR2)

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CAS Write Latency (CWL)

CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 58 (page 149)). The overall WRITE la-
tency (WL) is equal to CWL + AL (See Figure below).

Figure 59: CAS Write Latency

CK

CK#

Command

DQ

DQS, DQS#

ACTIVE n

T0

T1

Don’t Care

NOP

NOP

T6

T12

NOP

WRITE n

T13

NOP

DI

 n + 3

DI

 n + 2

DI

 n + 1

T14

NOP

DI

 n

t

RCD (MIN)

NOP

AL = 5

T11

Indicates break
in time scale

WL = AL + CWL = 11

Transitioning Data

T2

CWL = 6

AUTO SELF REFRESH (ASR)

Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
sure the DRAM never exceeds a T

C

 of 85°C while in self refresh unless the user enables

the SRT feature listed below when the T

C

 is between 85°C and 105°C.

Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to
2x when the case temperature exceeds 85°C. This enables the user to operate the DRAM
beyond the standard 85°C limit up to the optional extended temperature range of 105°C
while in self refresh mode.

The standard self refresh current test specifies test conditions to normal case tempera-
ture (85°C) only, meaning if ASR is enabled, the standard self refresh current specifica-
tions do not apply (see Extended Temperature Usage).

SELF REFRESH TEMPERATURE (SRT)

Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, SRT requires the user to en-
sure the DRAM never exceeds a T

of 85°C while in self refresh mode unless the user en-

ables ASR.

When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regard-
less of the case temperature. This enables the user to operate the DRAM beyond the
standard 85°C limit up to the optional extended temperature range of 105°C while in
self refresh mode. The standard self refresh current test specifies test conditions to nor-

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 2 (MR2)

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mal case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh
current specifications do not apply (see Extended Temperature Usage).

SRT vs. ASR

If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR
is required, and both can be disabled throughout operation. However, if the extended
temperature option of up to 105°C is needed, the user is required to provide a 2x refresh
rate during (manual) refreshes when the device is (>85°C but less than 95°C) or 4X re-
freshes (>95°C but less than 105°C) and enable either the SRT or the ASR to ensure self
refresh is performed at the 2x rate.

SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is
performed at the 2x refresh rate regardless of the case temperature.

ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. Howev-
er, while in self refresh mode, ASR enables the refresh rate to automatically adjust be-
tween 1x to 2x over the supported temperature range. One other disadvantage with ASR
is the DRAM cannot always switch from a 1x to a 2x refresh rate at an exact case temper-
ature of 85°C. Although the DRAM will support data integrity when it switches from a 1x
to a 2x refresh rate, it may switch at a lower temperature than 85°C.

Since only one mode is necessary, SRT and ASR cannot be enabled at the same time.

DYNAMIC ODT

The dynamic ODT (R

TT(WR)

) feature is defined by MR2[10, 9]. Dynamic ODT is enabled

when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT ter-
mination on-the-fly.

With dynamic ODT (R

TT(WR)

) enabled, the DRAM switches from normal ODT (R

TT_nom

)

to dynamic ODT (R

TT(WR)

) when beginning a WRITE burst and subsequently switches

back to ODT (R

TT_nom

) at the completion of the WRITE burst. If R

TT_nom

 is disabled, the

R

TT_nom

 value will be High-Z. Special timing parameters must be adhered to when dy-

namic ODT (R

TT(WR)

) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,

and 

t

ADC.

Dynamic ODT is only applicable during WRITE cycles. If ODT (R

TT_nom

) is disabled, dy-

namic ODT (R

TT(WR)

) is still permitted. R

TT_nom

 and R

TT(WR)

 can be used independent of

one other. Dynamic ODT is not available during write leveling mode, regardless of the
state of ODT (R

TT_nom

). For details on dynamic ODT operation, refer to Dynamic ODT

(page 199).

Mode Register 3 (MR3)

The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 60 (page 152). The MR3 is pro-
grammed via the LOAD MODE command and retains the stored information until it is
programmed again or until the device loses power. Reprogramming the MR3 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR3 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time 

t

MRD and 

t

MOD before initiating a sub-

sequent operation.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 60: Mode Register 3 (MR3) Definition

A9

A7

A6 A5

A4 A3

A8

A2

A1

A0

Mode register 3 (MR3)

Address bus

9

7

6

5

4

3

8

2

1

0

A10

A12 A11

BA0

BA1

10

11

12

13

14

15

A13

A14

A15

01

01

01

01

01 01 01

01

01

MPR 

1

1

BA2

16

17

18

01

01

01

01

01

M2

0

1

MPR Enable

Normal DRAM operations2

Dataflow from MPR

MPR_RF

M16

0

1

0

1

M17

0

0

1

1

Mode Register 

Mode register set (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

MPR READ Function

Predefined  pattern3

Reserved

Reserved

Reserved

M0

0

1

0

1

M1

0

0

1

1

Notes:

1. MR3[18 and 15:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.

MULTIPURPOSE REGISTER (MPR)

The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 61 (page 153).

If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a prede-
fined read pattern for system calibration is selected.

To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-
ing the MRS command, all banks must be in the idle state (all banks are precharged,
and 

t

RP is met). When the MPR is enabled, any subsequent READ or RDAP commands

are redirected to the multipurpose register. The resulting operation when either a READ
or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see 
Table 78 (page 154)). When the MPR is enabled, only READ or RDAP commands are al-
lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-
lowed during MPR enable mode. The RESET function is supported during MPR enable
mode.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 61: Multipurpose Register (MPR) Block Diagram

Memory core

MR3[2] = 0 (MPR off)

DQ, DM, DQS, DQS#

Multipurpose register

predefined data for READs

MR3[2] = 1 (MPR on)

Notes:

1. A predefined data pattern can be read out of the MPR with an external READ com-

mand.

2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When

the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.

Table 77: MPR Functional Description of MR3 Bits

MR3[2]

MR3[1:0]

Function

MPR

MPR READ Function

0

“Don’t Care”

Normal operation, no MPR transaction

All subsequent READs come from the DRAM memory array

All subsequent WRITEs go to the DRAM memory array

1

A[1:0]

(see Table 78 (page 154))

Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and

2

MPR Functional Description

The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining
DQs driven LOW, or for all DQs to output the MPR data . The MPR readout supports
fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ
latencies and AC timings applicable, provided the DLL is locked as required.

MPR addressing for a valid MPR read is as follows:

• A[1:0] must be set to 00 as the burst order is fixed per nibble
• A2 selects the burst order:

– BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7

• For burst chop 4 cases, the burst order is switched on the nibble base along with the

following:

– A2 = 0; burst order = 0, 1, 2, 3

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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– A2 = 1; burst order = 4, 5, 6, 7

• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is

assigned to MSB

• A[9:3] are a “Don’t Care”
• A10 is a “Don’t Care”
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0
• A13 is a “Don’t Care”
• BA[2:0] are a “Don’t Care”

MPR Register Address Definitions and Bursting Order

The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 0–1 bit pat-
tern.

Examples of the different types of predefined READ pattern bursts are shown in the fol-
lowing figures.

Table 78: MPR Readouts and Burst Order Bit Mapping

MR3[2]

MR3[1:0]

Function

Burst

Length

Read

A[2:0]

Burst Order and Data Pattern

1

00

READ predefined pattern

for system calibration

BL8

000

Burst order: 0, 1, 2, 3, 4, 5, 6, 7

Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1

BC4

000

Burst order: 0, 1, 2, 3

Predefined pattern: 0, 1, 0, 1

BC4

100

Burst order: 4, 5, 6, 7

Predefined pattern: 0, 1, 0, 1

1

01

RFU

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

1

10

RFU

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

1

11

RFU

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Note:

1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selec-

ted MPR agent.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout

T0

Ta0

Tb0

Tb1

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

CK

CK#

MRS

PREA

READ

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Valid

Command

t

MPRR

Don’t Care

Indicates break
in time scale

DQS, DQS#

Bank address

3

Valid

3

0

A[1:0]

Valid

0

2

1

A2

0

2

0

00

A[9:3]

Valid

00

0

1

A10/AP

Valid

0

0

A11

Valid

0

0

A12/BC#

Valid

1

0

0

A[15:13]

Valid

0

DQ 

t

MOD

t

RP

t

MOD

RL

Notes:

1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 63: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout

T0

Ta

Tb

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

CK

CK#

t

MPRR

Don’t Care

Indicates break
in time scale

RL

3

Valid

3

Bank address

Valid

A[1:0]

Valid

0

2

0

2

0

A2

1

2

0

2

1

0

0

A[15:13]

Valid

Valid

0

A[9:3]

Valid

Valid

00

00

A11

Valid

Valid

0

0

A12/BC#

Valid

1

0

0

A10/AP

Valid

Valid

0

0

1

RL

PREA

READ

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

MRS

Valid

Command

READ

1

MRS

DQ 

Valid

DQS, DQS#

t

RP

t

MOD

t

CCD

t

MOD

Notes:

1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 64: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble

T0

Ta

Tb

CK

CK#

DQ 

DQS, DQS#

t

MOD

t

MPRR

Don’t Care

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Valid

Command

MRS

PREA

READ

1

READ

1

NOP

NOP

Indicates break
in time scale

Bank address

3

Valid

3

Valid

0

A[1:0]

Valid

0

2

0

2

1

A2

1

4

0

3

0

00

A[9:3]

Valid

Valid

00

0

1

A10/AP

Valid

Valid

0

0

A11

Valid

Valid

0

0

A12/BC#

Valid

1

Valid

1

0

0

A[15:13]

Valid

Valid

0

RL

RL

t

RF

t

MOD

t

CCD

Notes:

1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
4. A2 = 1 selects upper 4 nibble bits 4 . . . 7.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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Figure 65: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble

T0

Ta

Tb

0

1

A10/AP

Valid

Valid

0

CK

CK#

MRS

PREA

READ

1

READ

1

NOP

NOP

NOP

NOP

NOP

NOP

NOP

MRS

NOP

NOP

Valid

Command

0

0

4

1

3

1

A2

t

MOD

t

MPRR

3

Valid

3

Bank address

Valid

0

2

0

2

0

A[1:0]

Valid

0

0

A[15:13]

Valid

Valid

0

0

A11

Valid

Valid

00

00

A[9:3]

Valid

Valid

Don’t Care

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

Indicates break
in time scale

RL

DQ 

DQS, DQS#

0

A12/BC#

Valid

1

Valid

1

0

RL

t

RF

t

MOD

t

CCD

Notes:

1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

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MPR Read Predefined Pattern

The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The
following is an example of using the read out predetermined read calibration pattern.
The example is to perform multiple reads from the multipurpose register to do system
level read timing calibration based on the predetermined and standardized pattern.

The following protocol outlines the steps used to perform the read calibration:

1. Precharge all banks
2. After 

t

RP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all sub-

sequent reads and loads the predefined pattern into the MPR. As soon as 

t

MRD

and 

t

MOD are satisfied, the MPR is available

3. Data WRITE operations are not allowed until the MPR returns to the normal

DRAM state

4. Issue a read with burst order information (all other address pins are “Don’t Care”):

• A[1:0] = 00 (data burst order is fixed starting at nibble)
• A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
• A12 = 1 (use BL8)

5. After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern

(0, 1, 0, 1, 0, 1, 0, 1)

6. The memory controller repeats the calibration reads until read data capture at

memory controller is optimized

7. After the last MPR READ burst and after 

t

MPRR has been satisfied, issue MRS,

MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subse-
quent read and write accesses will be regular reads and writes from/to the DRAM
array

8. When 

t

MRD and 

t

MOD are satisfied from the last MRS, the regular DRAM com-

mands (such as activate a memory bank for regular read or write access) are per-
mitted

MODE REGISTER SET (MRS) Command

The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which
mode register is programmed:

• BA2 = 0, BA1 = 0, BA0 = 0 for MR0
• BA2 = 0, BA1 = 0, BA0 = 1 for MR1
• BA2 = 0, BA1 = 1, BA0 = 0 for MR2
• BA2 = 0, BA1 = 1, BA0 = 1 for MR3

The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (

t

RP is satisfied and no data bursts are in progress). The controller

must wait the specified time 

t

MRD before initiating a subsequent operation such as an

ACTIVATE command (see Figure 52 (page 140)). There is also a restriction after issuing
an MRS command with regard to when the updated functions become available. This
parameter is specified by 

t

MOD. Both 

t

MRD and 

t

MOD parameters are shown in Figure

52 (page 140) and Figure 53 (page 141). Violating either of these requirements will result
in unspecified operation.

4Gb: x4, x8, x16 DDR3L SDRAM

MODE REGISTER SET (MRS) Command

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ZQ CALIBRATION Operation

The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R

ON

)

and ODT values (R

TT

) over process, voltage, and temperature, provided a dedicated

240

ȍ

 (±1%) external resistor is connected from the DRAM’s ZQ ball to V

SSQ

.

DDR3 SDRAM require a longer time to calibrate R

ON

 and ODT at power-up initialization

and self refresh exit, and a relatively shorter time to perform periodic calibrations.
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example
of ZQ calibration timing is shown below.

All banks must be precharged and 

t

RP must be met before ZQCL or ZQCS commands

can be issued to the DRAM. No other activities (other than issuing another ZQCL or
ZQCS command) can be performed on the DRAM channel by the controller for the du-
ration of 

t

ZQinit or 

t

ZQoper. The quiet time on the DRAM channel helps accurately cali-

brate R

ON

 and ODT. After DRAM calibration is achieved, the DRAM should disable the

ZQ ball’s current consumption path to reduce power.

ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.

In dual-rank systems that share the ZQ resistor between devices, the controller must not
enable overlap of 

t

ZQinit, 

t

ZQoper, or 

t

ZQCS between ranks.

Figure 66: ZQ CALIBRATION Timing (ZQCL and ZQCS)

NOP

ZQCL

NOP

NOP

Valid

Valid

ZQCS

NOP

NOP

NOP

Valid

Command

Indicates break
in time scale

T0

T1

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tc0

Tc1

Tc2

Address

Valid

Valid

Valid

A10

Valid

Valid

Valid

CK

CK#

Don’t Care

DQ

High-Z

High-Z

3

3

Activities

Activ-
ities

Valid

Valid

ODT

2

2

Valid

1

CKE

1

Valid

Valid

Valid

t

ZQCS

t

ZQinit or 

t

ZQoper

Notes:

1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.

4Gb: x4, x8, x16 DDR3L SDRAM

ZQ CALIBRATION Operation

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ACTIVATE Operation

Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE com-
mand, which selects both the bank and the row to be activated.

After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the 

t

RCD specification. However, if the additive latency

is programmed correctly, a READ or WRITE command may be issued prior to 

t

RCD

(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to 

t

RCD (MIN) with the require-

ment that (ACTIVATE-to-READ/WRITE) + AL 

•

 

t

RCD (MIN) (see Posted CAS Additive

Latency). 

t

RCD (MIN) should be divided by the clock period and rounded up to the next

whole number to determine the earliest clock edge after the ACTIVATE command on
which a READ or WRITE command can be entered. The same procedure is used to con-
vert other specification limits from time units to clock cycles.

When at least one bank is open, any READ-to-READ command delay or WRITE-to-
WRITE command delay is restricted to 

t

CCD (MIN).

A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time in-
terval between successive ACTIVATE commands to the same bank is defined by 

t

RC.

A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is de-
fined by 

t

RRD. No more than four bank ACTIVATE commands may be issued in a given

t

FAW (MIN) period, and the 

t

RRD (MIN) restriction still applies. The 

t

FAW (MIN) param-

eter applies, regardless of the number of banks already opened or closed.

Figure 67: Example: Meeting 

t

RRD (MIN) and 

t

RCD (MIN)

Command

Don’t Care

T1

T0

T2

T3

T4

T5

T8

T9

t

RRD

Row

Row

Col

Bank x

Bank y

Bank y

NOP

ACT

NOP

NOP

ACT

NOP

NOP

RD/WR

t

RCD

BA[2:0]

CK#

Address

CK

T10

T11

NOP

NOP

Indicates break
in time scale

4Gb: x4, x8, x16 DDR3L SDRAM

ACTIVATE Operation

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Figure 68: Example: 

t

FAW

Command

Don’t Care

T1

T0

T4

T5

T8

T9

T10

T11

t

RRD

Row

Row

Bank a

Bank b

Row

Bank c

Row

Bank d

Bank y

Row

Bank y

NOP

ACT

NOP

ACT

ACT

NOP

NOP

t

FAW

BA[2:0]

CK#

Address

CK

T19

T20

NOP

ACT

ACT

Bank e

Indicates break
in time scale

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ACTIVATE Operation

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READ Operation

READ bursts are initiated with a READ command. The starting column and bank ad-
dresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-
ble in the mode register via the MRS command. Each subsequent data-out element is
valid nominally at the next positive or negative clock edge (that is, at the next crossing
of CK and CK#). Figure 69 shows an example of RL based on a CL setting of 8 and an AL
setting of 0.

Figure 69: READ Latency

CK

CK#

Command

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Address

Bank a,

Col n

CL = 8, AL = 0

DQ

DQS, DQS#

DO

n

T0

T7

T8

T9

T10

T11

Don’t Care

Transitioning Data

T12

T12

Indicates break
in time scale

Notes:

1. DO 

n

 = data-out from column 

n

.

2. Subsequent elements of data-out appear in the programmed order following DO 

n

.

DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS and HIGH state on DQS# is known as the READ preamble (

t

RPRE). The LOW state

on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (

t

RPST). Upon completion of a burst, assuming no other

commands have been initiated, the DQ goes High-Z. A detailed explanation of 

t

DQSQ

(valid data-out skew), 

t

QH (data-out window hold), and the valid data window are de-

picted in Figure 80 (page 171). A detailed explanation of 

t

DQSCK (DQS transition skew

to CK) is also depicted in Figure 80 (page 171).

Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued 

t

CCD cycles after the first READ command. This is shown for BL8 in Figure 70

(page 165). If BC4 is enabled, 

t

CCD must still be met, which will cause a gap in the data

output, as shown in Figure 71 (page 165). Nonconsecutive READ data is reflected in 
Figure 72 (page 166). DDR3 SDRAM does not allow interrupting or truncating any
READ burst.

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READ Operation

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Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Fig-
ure 73 (page 166) (BC4 is sho
wn in Figure 74 (page 167)). To ensure the READ data is
completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing
is RL + 

t

CCD - WL + 2

t

CK.

A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called 

t

RTP (READ-to-PRECHARGE). 

t

RTP starts AL

cycles later than the READ command. Examples for BL8 are shown in Figure 75 (page
167) and BC4 in Figure 76 (page 168). Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until 

t

RP is met. The PRECHARGE

command followed by another PRECHARGE command to the same bank is allowed.
However, the precharge period will be determined by the last PRECHARGE command
issued to the bank.

If A10 is HIGH when a READ command is issued, the READ with auto precharge func-
tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL + 

t

RTP cycles after the READ command. DRAM support a 

t

RAS lockout feature (see 

Figure 78 (page 168)). I

t

RAS (MIN) is not satisfied at the edge, the starting point of the

auto precharge operation will be delayed until 

t

RAS (MIN) is satisfied. If 

t

RTP (MIN) is

not satisfied at the edge, the starting point of the auto precharge operation is delayed
until 

t

RTP (MIN) is satisfied. In case the internal precharge is pushed out by 

t

RTP, 

t

RP

starts at the point at which the internal precharge happens (not at the next rising clock
edge after this event). The time from READ with auto precharge to the next ACTIVATE
command to the same bank is AL + (

t

RTP + 

t

RP)*, where * means rounded up to the next

integer. In any event, internal precharge does not start earlier than four clocks after the
last 8

n

-bit prefetch.

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READ Operation

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Figure 70: Consecutive READ Bursts (BL8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

t

RPST

NOP

READ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ3

DQS, DQS#

Bank,

Col n

Bank,

Col b

Address

2

RL = 5

t

RPRE

t

CCD

RL = 5

DO

 n + 3

DO

 n + 2

DO

 n + 1

DO

 n

DO

 n + 7

DO

 n + 6

DO

 n + 5

DO 

n + 4

DO

 b + 3

DO

 b + 2

DO

 b + 1

DO

 b

DO

 b + 7

DO

 b + 6

DO

 b + 5

DO 

b + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0

and T4.

3. DO 

n

 (or 

b

) = data-out from column 

n

 (or column 

b

).

4. BL8, RL = 5 (CL = 5, AL = 0).

Figure 71: Consecutive READ Bursts (BC4)

NOP

CK

CK#

Command

1

DQ3

DQS, DQS#

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Address

2

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

READ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Bank,

Col n

Bank,

Col b

t

RPST

t

RPRE

t

RPST

t

RPRE

RL = 5

DO

 n + 3

DO

 n + 2

DO

 n + 1

DO

 n

DO

 b + 3

DO

 b + 2

DO

 b + 1

DO

 b

RL = 5

t

CCD

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0

and T4.

3. DO 

n

 (or 

b

) = data-out from column 

n

 (or column 

b

).

4. BC4, RL = 5 (CL = 5, AL = 0).

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READ Operation

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Figure 72: Nonconsecutive READ Bursts

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

DQS, DQS#

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

READ

NOP

READ

Address

Bank a,

Col n

Bank a,

Col b

CK

CK#

DQ

DO

n

DO

b

CL = 8 

CL = 8 

Notes:

1. AL = 0, RL = 8.
2. DO 

n

 (or 

b

) = data-out from column 

n

 (or column 

b

).

3. Seven subsequent elements of data-out appear in the programmed order following DO 

n

.

4. Seven subsequent elements of data-out appear in the programmed order following DO 

b

.

Figure 73: READ (BL8) to WRITE (BL8)

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

CK

CK#

Command

1

NOP

NOP

NOP

NOP

NOP

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

WPST

t

RPRE

t

WPRE

t

RPST

DQS, DQS#

DQ3

WL = 5

t

WR

t

WR

READ

DO

 n

DO

 n + 1

DO

 n + 2

DO

 n + 3

DO

 n + 4

DO

 n + 5

DO

 n + 6

DO

 n + 7

DI

 n

DI

 n + 1

DI

 n + 2

DI

 n + 3

DI

 n + 4

DI

 n + 5

DI

 n + 6

DI

 n + 7

READ-to-WRITE command delay = RL + 

t

CCD + 2

t

CK - WL

t

BL = 4 clocks

Address

2

Bank,

Col b

Bank,

Col n

RL = 5

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at

T0, and the WRITE command at T6.

3. DO 

n

 = data-out from column, DI 

b

 = data-in for column 

b

.

4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

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Figure 74: READ (BC4) to WRITE (BC4) OTF

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

CK

CK#

Address

2

Command

1

t

WPST

t

WPRE

t

RPST

DQS, DQS#

DQ3

WL = 5

t

WR

t

WTR

t

BL = 4 clocks

t

RPRE

RL = 5

READ-to-WRITE command delay = RL + 

t

CCD/2 + 2

t

CK - WL

READ

DO

n

DO

n +  1

DO

n +  2

DO

n + 3

DI

n

DI

n + 1

DI

n + 2

DI

n +  3

Bank,

Col b

Bank,

Col n

NOP

NOP

NOP

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at

T4.

3. DO 

n

 = data-out from column 

n

; DI 

n

 = data-in from column 

b

.

4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

Figure 75: READ to PRECHARGE (BL8)

t

RAS

t

RTP

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

DQ

DQS, DQS#

Don’t Care

Transitioning Data

NOP

NOP

NOP

NOP

NOP

ACT

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

NOP

READ

Bank a,

Col n

NOP

PRE

Bank a,

(or all)

Bank a,

Row b

t

RP

DO

n

DO

n + 1

DO

n + 2

DO

n + 3

DO

n + 4

DO

n + 5

DO

n + 6

DO

n + 7

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READ Operation

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Figure 76: READ to PRECHARGE (BC4)

CK

CK#

Don’t Care

Transitioning Data

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

ACT

NOP

NOP

NOP

NOP

NOP

READ

NOP

PRE

Address

Bank a,

Col n

Bank a,

(or all)

Bank a,

Row b

t

RP

t

RTP

DQS, DQS#

DQ

DO

n

DO

n + 1

DO

n + 2

DO

n + 3

t

RAS

Figure 77: READ to PRECHARGE (AL = 5, CL = 6)

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

DQ

DQS, DQS#

Don’t Care

Transitioning Data

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

NOP

READ

Bank a,

Col n

NOP

PRE

Bank a,

(or all)

ACT

Bank a,

Row b

NOP

NOP

t

RAS

CL = 6

AL = 5

t

RTP

t

RP

DO

n + 3

DO

n + 2

DO

n

DO

n + 1

Figure 78: READ with Auto Precharge (AL = 4, CL = 6)

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

DQ

DQS, DQS#

Don’t Care

Transitioning Data

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

Ta0

t

RTP (MIN)

NOP

READ

NOP

AL = 4

NOP

NOP

CL = 6

NOP

t

RAS (MIN)

ACT

Indicates break
in time scale

t

RP

Bank a,

Col n

Bank a,

Row b

DO

n

DO

n + 1

DO

n + 2

DO

n + 3

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DQS to DQ output timing is shown in Figure 79 (page 170). The DQ transitions between
valid data outputs must be within 

t

DQSQ of the crossing point of DQS, DQS#. DQS must

also maintain a minimum HIGH and LOW time of 

t

QSH and 

t

QSL. Prior to the READ

preamble, the DQ balls will either be floating or terminated, depending on the status of
the ODT signal.

Figure 80 (page 171) shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±

t

DQSCK of the clock crossing point. The data

out has no timing relationship to CK, only to DQS, as shown in Figure 80 (page 171).

Figure 80 (page 171) also shows the READ preamble and postamble. Typically, both
DQS and DQS# are High-Z to save power (V

DDQ

). Prior to data output from the DRAM,

DQS is driven LOW and DQS# is HIGH for 

t

RPRE. This is known as the READ preamble.

The READ postamble, 

t

RPST, is one half clock from the last DQS, DQS# transition. Dur-

ing the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the
DQ is disabled or continues terminating, depending on the state of the ODT signal. Fig-
ure 83 (page 173) demonstr
ates how to measure 

t

RPST.

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Figure 79: Data Output Timing – 

t

DQSQ and Data Valid Window

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

Bank,

Col n

t

RPST

NOP

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

Address

2

t

DQSQ (MAX)

DQS, DQS#

DQ

3

 (last data valid)

DQ

3

 (first data no longer valid)

All DQ collectively

DO

n

DO

n + 3

DO

n + 2

DO

n + 1

DO

n + 7

DO

n + 6

DO

n + 5

DO

n + 4

DO

n + 2

DO

n + 1

DO

n + 7

DO

n + 6

DO

n + 5

DO

n + 4

DO

 n + 3

DO

 n + 2

DO

 n + 1

DO

 n

DO

 n + 7

DO

 n + 6

DO

 n + 5

DO

 n

DO

n + 3

t

RPRE

Don’t Care

Data valid

Data valid

t

QH

t

QH

t

HZDQ (MAX)

DO 

n + 4

RL = AL + CL

t

DQSQ (MAX)

t

LZDQ (MIN)

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at

T0.

3. DO 

n

 = data-out from column 

n

.

4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to V

DDQ

/2 and DLL on and locked.

6.

t

DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.

7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within

a burst.

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READ Operation

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t

HZ and 

t

LZ transitions occur in the same access time as valid data transitions. These

parameters are referenced to a specific voltage level that specifies when the device out-
put is no longer driving 

t

HZDQS and 

t

HZDQ, or begins driving 

t

LZDQS, 

t

LZDQ. Figure

81 (page 172) shows a method of calculating the point when the device is no longer
driving 

t

HZDQS and 

t

HZDQ, or begins driving 

t

LZDQS, 

t

LZDQ, by measuring the signal

at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters 

t

LZDQS, 

t

LZDQ, 

t

HZDQS, and 

t

HZDQ

are defined as single-ended.

Figure 80: Data Strobe Timing – READs

RL measured

to this point

DQS, DQS#

early strobe

CK

t

LZDQS (MIN)

t

HZDQS (MIN)

DQS, DQS#

late strobe

t

LZDQS (MAX)

t

HZDQS (MAX)

t

DQSCK (MAX)

t

DQSCK (MAX)

t

DQSCK (MAX)

t

DQSCK (MAX)

t

DQSCK (MIN)

t

DQSCK (MIN)

t

DQSCK (MIN)

t

DQSCK (MIN)

CK#

t

RPRE

t

QSH

t

QSH

t

QSL

t

QSL

t

QSL

t

QSL

t

QSH

t

QSH

Bit 0

Bit 1

Bit 2

Bit 7

t

RPRE

Bit 0

Bit 1

Bit 2

Bit 7

Bit 6

Bit 3

Bit 4

Bit 5

Bit 6

Bit 4

Bit 3

Bit 5

t

RPST

t

RPST

T0

T1

T2

T3

T4

T5

T6

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Figure 81: Method for Calculating 

t

LZ and 

t

HZ

t

HZDQS, 

t

HZDQ

t

HZDQS, 

t

HZDQ end point = 2 × T1 - T2

V

OH

 - xmV

V

TT

 - xmV

V

OL

 + xmV

V

TT

 + xmV

V

OH

 - 2xmV

V

TT

 - 2xmV

V

OL

 + 2xmV

V

TT

 + 2xmV

t

LZDQS, 

t

LZDQ

t

LZDQS, 

t

LZDQ begin point = 2 × T1 - T2

T1

T1

T2

T2

Notes:

1. Within a burst, the rising strobe edge is not necessarily fixed at 

t

DQSCK (MIN) or 

t

DQSCK

(MAX). Instead, the rising strobe edge can vary between 

t

DQSCK (MIN) and 

t

DQSCK

(MAX).

2. The DQS HIGH pulse width is defined by 

t

QSH, and the DQS LOW pulse width is defined

by 

t

QSL. Likewise, 

t

LZDQS (MIN) and 

t

HZDQS (MIN) are not tied to 

t

DQSCK (MIN) (early

strobe case), and 

t

LZDQS (MAX) and 

t

HZDQS (MAX) are not tied to 

t

DQSCK (MAX) (late

strobe case); however, they tend to track one another.

3. The minimum pulse width of the READ preamble is defined by 

t

RPRE (MIN). The mini-

mum pulse width of the READ postamble is defined by 

t

RPST (MIN).

Figure 82: 

t

RPRE Timing

tRPRE

DQS - DQS# 

DQS

DQS#

T1

t

RPRE begins

T2

t

RPRE ends

CK

CK#

V

TT

Resulting differential 
signal relevant for 

t

RPRE specification

t

C

t

A

t

B

t

D

Single-ended signal provided
as background information

0V

Single-ended signal provided
as background information

V

TT

V

TT

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Figure 83: 

t

RPST Timing

t

RPST

DQS - DQS#

DQS 

DQS#

T1

t

RPST begins

T2

t

RPST ends

Resulting differential 
signal relevant for 

t

RPST specification

CK

CK#

V

TT

t

C

t

A

t

B

t

D

Single-ended signal, provided
as background information

Single-ended signal, provided
as background information

0V

V

TT

V

TT

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WRITE Operation

WRITE bursts are initiated with a WRITE command. The starting column and bank ad-
dresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the row being accessed is pre-
charged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in Figure
86 (page 176) thr
ough Figure 94 (page 181), auto precharge is disabled.

During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,
DQS#) and specified as the WRITE preamble shown in Figure 86 (page 176). The half
cycle on DQS following the last data-in element is known as the WRITE postamble.

The time between the WRITE command and the first valid edge of DQS is WL clocks
±

t

DQSS. Figure 87 (page 177) through Figure 94 (page 181) show the nominal case

where 

t

DQSS = 0ns; however, Figure 86 (page 176) includes 

t

DQSS (MIN) and 

t

DQSS

(MAX) cases.

Data may be masked from completing a WRITE using data mask. The data mask occurs
on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal-
ly. If DM is HIGH, that bit of data is masked.

Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide a continuous flow of input data. The new WRITE command can be 

t

CCD clocks

following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figure 87 (page 177) and Figure 88
(page 177) show concatenated bursts. An example of nonconsecutive WRITEs is shown
in Figure 89 (page 178).

Data for any WRITE burst may be followed by a subsequent READ command after 

t

WTR

has been met (see Figure 90 (page 178), Figure 91 (page 179), and Figure 92 (page
180)).

Data for any WRITE burst may be followed by a subsequent PRECHARGE command,
providing 

t

WR has been met, as shown in Figure 93 (page 181) and Figure 94 (page

181).

Both 

t

WTR and 

t

WR starting time may vary, depending on the mode register settings

(fixed BC4, BL8 versus OTF).

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WRITE Operation

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Figure 84: 

t

WPRE Timing

DQS - DQS#

T1

t

WPRE begins

T2

t

WPRE ends

t

WPRE

Resulting differential 

signal relevant for 

t

WPRE specification

0V

CK

CK#

V

TT

Figure 85: 

t

WPST Timing

t

WPST

DQS - DQS#

T1

t

WPST begins

T2

t

WPST ends

Resulting differential 

signal relevant for 

t

WPST specification

0V

CK

CK#

V

TT

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WRITE Operation

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Figure 86: WRITE Burst

DI

n + 3

DI

 n + 2

DI

n + 1

DI

n

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

Don’t Care

Transitioning Data

DI

n + 7

DI

 n + 6

DI

n + 5

DI

n + 4

Bank,

Col n

NOP

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

3

DQS, DQS#

Address

2

t

WPST

t

WPRE

t

WPST

t

DQSL

DQ

3

DQ

3

t

WPST

DQS, DQS#

DQS, DQS#

t

DQSL

t

WPRE

t

DQSS

t

DQSS

t

DSH

t

DSH

t

DSH

t

DSH

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSS

t

DSH

t

DSH

t

DSH

t

DSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSH

t

DQSL

t

DQSL

t

DQSL

t

DQSL

t

DQSH

t

DQSH

t

DQSH

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSL

t

DQSH

t

DQSH

WL = AL + CWL

t

DQSS (MIN)

t

DQSS (NOM)

t

DQSS (MAX)

t

DQSL

t

WPRE

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

DI

n + 7

DI

 n + 6

DI

 n + 5

DI

n + 4

DI

n + 3

DI

n + 2

DI

n + 1

DI

 n

DI

n + 7

DI

n + 6

DI

n + 5

DI

n + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

the WRITE command at T0.

3. DI 

n

 = data-in for column 

n

.

4. BL8, WL = 5 (AL = 0, CWL = 5).
5.

t

DQSS must be met at each rising clock edge.

6.

t

WPST is usually depicted as ending at the crossing of DQS, DQS#; however, 

t

WPST ac-

tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.

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Figure 87: Consecutive WRITE (BL8) to WRITE (BL8)

WL = 5

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CCD

t

WPRE

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

Valid

Valid

NOP

WRITE

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

3

DQS, DQS#

Address

2

t

WPST

t

WR

t

WTR

t

BL = 4 clocks

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

DI

 n + 7

DI

 n + 6

DI

n + 5

DI

n + 4

DI

 b + 3

DI

 b + 2

DI

 b + 1

DI

 b

DI

 b + 7

DI

 b + 6

DI

 b + 5

DI

b + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at

T0 and T4.

3. DI 

n

 (or 

b

) = data-in for column 

n

 (or column 

b

).

4. BL8, WL = 5 (AL = 0, CWL = 5).

Figure 88: Consecutive WRITE (BC4) to WRITE (BC4) via OTF

WL = 5

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CCD

t

WPRE

T10

T11

Don’t Care

Transitioning Data

T12

T13

T14

Valid

Valid

NOP

WRITE

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

3

DQS, DQS#

Address

2

t

WPST

t

WR

t

WTR

t

WPST

t

WPRE

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

n

DI

 b + 3

DI

 b + 2

DI

 b + 1

DI

 b

t

BL = 4 clocks

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. BC4, WL = 5 (AL = 0, CWL = 5).
3. DI 

n

 (or 

b

) = data-in for column 

n

 (or column 

b

).

4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
5. If set via MRS (fixed) 

t

WR and 

t

WTR would start T11 (2 cycles earlier).

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Figure 89: Nonconsecutive WRITE to WRITE

CK

CK#

Command

NOP

NOP

NOP

Address

DQ

DM

DQS, DQS#

Transitioning Data

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

NOP

WRITE

NOP

WRITE

Valid

Valid

NOP

DI

n

DI

n + 1

DI

n + 2

DI

n + 3

DI

n + 4

DI

n + 5

DI

n + 6

Don't Care

DI

n + 7

DI

b

DI

b + 1

DI

b + 2

DI

b + 3

DI

b + 4

DI

b + 5

DI

b + 6

DI

b + 7

WL = CWL + AL  = 7

WL = CWL + AL  = 7

Notes:

1. DI 

n

 (or 

b

) = data-in for column

 n

 (or column 

b

).

2. Seven subsequent elements of data-in are applied in the programmed order following DO 

n

.

3. Each WRITE command may be to any bank.
4. Shown for WL = 7 (CWL = 7, AL = 0).

Figure 90: WRITE (BL8) to READ (BL8)

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

WPRE

T10

T11

Don’t Care

Transitioning Data

Ta0

NOP

WRITE

READ

Valid

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

4

DQS, DQS#

Address

3

t

WPST

t

WTR

2

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

DI

n + 7

DI

n + 6

DI

n + 5

DI

n + 4

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.

t

WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last

write data shown at T9.

3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command

at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.

4. DI 

n

 = data-in for column 

n

.

5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

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Figure 91: WRITE to READ (BC4 Mode Register Setting)

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Ta0

Don’t Care

Transitioning Data

NOP

WRITE

Valid

READ

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

4

DQS, DQS#

Address

3

t

WPST

t

WTR

2

t

WPRE

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.

t

WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last

write data shown at T7.

3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at

Ta0.

4. DI 

n

 = data-in for column 

n

.

5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).

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Figure 92: WRITE (BC4 OTF) to READ (BC4 OTF)

WL = 5

RL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

WPRE

T10

T11

Don’t Care

Transitioning Data

Tn

NOP

WRITE

READ

Valid

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

1

DQ

4

DQS, DQS#

Address

3

t

WPST

t

BL = 4 clocks

NOP

t

WTR

2

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.

t

WTR controls the WRITE-to-READ delay to the same device and starts after 

t

BL.

3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ

command at T

n

.

4. DI 

n

 = data-in for column 

n

.

5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

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Figure 93: WRITE (BL8) to PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

Ta0

Ta1

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

DI

n + 6

DI

n + 7

DI

n + 5

DI

n + 4

NOP

WRITE

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

PRE

CK

CK#

Command

DQ BL8

DQS, DQS#

Address

Don’t Care

Transitioning Data

Indicates break
in time scale

t

WR

WL = AL + CWL

Valid

Notes:

1. DI 

n

 = data-in from column 

n

.

2. Seven subsequent elements of data-in are applied in the programmed order following

DO 

n

.

3. Shown for WL = 7 (AL = 0, CWL = 7).

Figure 94: WRITE (BC4 Mode Register Setting) to PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

Ta0

Ta1

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

NOP

WRITE

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

PRE

CK

CK#

Command

DQ BC4

DQS, DQS#

Address

Don’t Care

Transitioning Data

Indicates break
in time scale

t

WR

WL = AL + CWL

Valid

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. The write recovery time (

t

WR) is referenced from the first rising clock edge after the last

write data is shown at T7. 

t

WR specifies the last burst WRITE cycle until the PRECHARGE

command can be issued to the same bank.

3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI 

n

 = data-in for column 

n

.

5. BC4 (fixed), WL = 5, RL = 5.

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Figure 95: WRITE (BC4 OTF) to PRECHARGE

WL = 5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Tn

Don’t Care

Transitioning Data

Bank,

Col n

NOP

WRITE

PRE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command1

DQ4

DQS, DQS#

Address3

t

WPST

t

WPRE

Indicates break
in time scale

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

t

WR

2

Valid

Notes:

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. The write recovery time (

t

WR) is referenced from the rising clock edge at T9. 

t

WR speci-

fies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.

3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command

at T0.

4. DI 

n

 = data-in for column 

n

.

5. BC4 (OTF), WL = 5, RL = 5.

DQ Input Timing

Figure 86 (page 176) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25

t

CK of the clock transitions, as limited by 

t

DQSS. All

data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.

The WRITE preamble and postamble are also shown in Figure 86 (page 176). One clock
prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for
a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,

t

WPRE. Likewise, DQS must be kept LOW by the controller after the last data is written

to the DRAM during the WRITE postamble, 

t

WPST.

Data setup and hold times are also shown in Figure 86 (page 176). All setup and hold
times are measured from the crossing points of DQS and DQS#. These setup and hold
values pertain to data input and data mask input.

Additionally, the half period of the data input strobe is specified by 

t

DQSH and 

t

DQSL.

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Figure 96: Data Input Timing

t

DH

t

DH

t

DS

t

DS

DM

DQ

DI

b

DQS, DQS#

Don’t Care

Transitioning Data

t

DQSH

t

DQSL

t

WPRE

t

WPST

4Gb: x4, x8, x16 DDR3L SDRAM

WRITE Operation

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PRECHARGE Operation

Input A10 determines whether one bank or all banks are to be precharged and, in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.

When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.

SELF REFRESH Operation

The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.

All power supply inputs (including V

REFCA

 and V

REFDQ

) must be maintained at valid lev-

els upon entry/exit and during self refresh mode operation. V

REFDQ

 may float or not

drive V

DDQ

/2 while in self refresh mode under certain conditions:

• V

SS

 < V

REFDQ

 < V

DD

 is maintained.

• V

REFDQ

 is valid and stable prior to CKE going back HIGH.

• The first WRITE operation may not occur earlier than 512 clocks after V

REFDQ

 is valid.

• All other self refresh mode exit timing requirements are met.

The DRAM must be idle with all banks in the precharge state (

t

RP is satisfied and no

bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) ( for timing requirements).
If R

TT,nom

 and R

TT(WR)

 are disabled in the mode registers, ODT can be a “Don’t Care.”

After the self refresh entry command is registered, CKE must be held LOW to keep the
DRAM in self refresh mode.

After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-
mand internally within the 

t

CKE period when it enters self refresh mode.

The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting

t

CK specifications) when self refresh mode is entered. If the clock remains stable and

the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after 

t

CKESR is satisfied (CKE is allowed to transition HIGH 

t

CKESR

later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change), 

t

CKSRE and 

t

CKSRX are not required. However, if the

clock is altered during self refresh mode (if it is turned-off or its frequency changes),
then 

t

CKSRE and 

t

CKSRX must be satisfied. When entering self refresh mode, 

t

CKSRE

must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh
mode, 

t

CKSRX must be satisfied prior to registering CKE HIGH.

When CKE is HIGH during self refresh exit, NOP or DES must be issued for 

t

XS time. 

t

XS

is required for the completion of any internal refresh already in progress and must be
satisfied before a valid command not requiring a locked DLL can be issued to the de-
vice. 

t

XS is also the earliest time self refresh re-entry may occur. Before a command re-

quiring a locked DLL can be applied, a ZQCL command must be issued, 

t

ZQOPER tim-

ing must be met, and 

t

XSDLL must be satisfied. ODT must be off during 

t

XSDLL.

4Gb: x4, x8, x16 DDR3L SDRAM

PRECHARGE Operation

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Figure 97: Self Refresh Entry/Exit Timing

CK

CK#

Command

NOP

NOP

4

SRE (REF)

3

Address

CKE

ODT

2

RESET#

2

Valid

Valid

6

SRX (NOP)

NOP

5

t

RP

8

t

XSDLL

7, 9

ODTL

t

IS

t

CPDED

t

IS

t

IS

Enter self refresh mode

(synchronous)

Exit self refresh mode

(asynchronous)

T0

T1

T2

Tc0

Tc1

Td0

Tb0

Don’t Care

Te0

Valid

Valid

7

Valid

Valid

Valid

t

IH

Ta0

Tf0

Indicates break
in time scale

t

CKSRX

1

t

CKSRE

1

t

XS

6, 9

t

CKESR (MIN)

1

Notes:

1. The clock must be valid and stable, meeting 

t

CK specifications at least 

t

CKSRE after en-

tering self refresh mode, and at least 

t

CKSRX prior to exiting self refresh mode, if the

clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then 

t

CKSRE and 

t

CKSRX do not

apply; however, 

t

CKESR must be satisfied prior to exiting at SRX.

2. ODT must be disabled and R

TT

 off prior to entering self refresh at state T1. If both

R

TT,nom

 and R

TT(WR)

 are disabled in the mode registers, ODT can be a “Don’t Care.”

3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the

inputs becoming “Don’t Care.”

5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.

t

XS is required before any commands not requiring a locked DLL.

7.

t

XSDLL is required before any commands requiring a locked DLL.

8. The device must be in the all banks idle state prior to entering self refresh mode. For

example, all banks must be precharged, 

t

RP must be met, and no data bursts can be in

progress.

9. Self refresh exit is asynchronous; however, 

t

XS and 

t

XSDLL timings start at the first rising

clock edge where CKE HIGH satisfies 

t

ISXR at Tc1. 

t

CKSRX timing is also measured so that

t

ISXR is satisfied at Tc1.

4Gb: x4, x8, x16 DDR3L SDRAM

SELF REFRESH Operation

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Extended Temperature Usage

Micron’s DDR3 SDRAM support the optional extended case temperature (T

C

) range of

0°C to 105°C. Thus, the SRT and ASR options must be used at a minimum for tempera-
tures above 85°C (and does not exceed 105°C).

The extended temperature range DRAM must be refreshed manually at 2x (double re-
fresh) anytime the case temperature is above 85°C (and does not exceed 95°C) and 4x
(four times refresh) anytime the case temperature is above 95°C (and does not exceed
105°C). The manual refresh requirement is accomplished by reducing the refresh period
from 64ms to 32ms (2x refresh) or 64ms to 16ms (4x refresh). However, self refresh mode
requires either ASR or SRT to support the extended temperature. Thus, either ASR or
SRT must be enabled when T

C

 is above 85°C or self refresh cannot be used until T

C

 is at

or below 85°C. Table 79 summarizes the two extended temperature options and Table
80 summar
izes how the two extended temperature options relate to one another.

Table 79: Self Refresh Temperature and Auto Self Refresh Description

Field

MR2 Bits

Description

Self Refresh Temperature (SRT)

SRT

7

If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate T

OPER 

during self refresh:

*MR2[7] = 0: Normal operating temperature range (0°C to 85°C)
*MR2[7] = 1: Extended operating temperature range (0°C to 105°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is
supported
*MR2[7] = 0: SRT is disabled

Auto Self Refresh (ASR)

ASR

6

When ASR is enabled, the DRAM automatically provides SELF REFRESH power management func-
tions, (refresh rate for all supported operating temperature values)
* MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate T

OPER 

during SELF REFRESH

operation
* MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)

Table 80: Self Refresh Mode Summary

MR2[6]

(ASR)

MR2[7]

(SRT)

SELF REFRESH Operation

Permitted Operating Temperature
Range for Self Refresh Mode

0

0

Self refresh mode is supported in the normal temperature
range

Normal (0°C to 85°C)

0

1

Self refresh mode is supported in normal and extended temper-
ature ranges; When SRT is enabled, it increases self refresh
power consumption

Normal and extended (0°C to 105°C)

1

0

Self refresh mode is supported in normal and extended temper-
ature ranges; Self refresh power consumption may be tempera-
ture-dependent

Normal and extended (0°C to 105°C)

1

1

Illegal

4Gb: x4, x8, x16 DDR3L SDRAM

Extended Temperature Usage

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Power-Down Mode

Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-
FRESH) are in progress. However, the power-down I

DD

 specifications are not applicable

until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 81). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 98 (page 189) through Figure 107 (page 193).

Table 81: Command to Power-Down Entry Parameters

DRAM Status

Last Command Prior to

CKE LOW

1

Parameter (Min)

Parameter Value

Figure

Idle or active

ACTIVATE

t

ACTPDEN

1

t

CK

Figure 105 (page 192)

Idle or active

PRECHARGE

t

PRPDEN

1

t

CK

Figure 106 (page 193)

Active

READ or READAP

t

RDPDEN

RL + 4

t

CK + 1

t

CK

Figure 101 (page 190)

Active

WRITE: BL8OTF, BL8MRS,

BC4OTF

t

WRPDEN

WL + 4

t

CK + 

t

WR/

t

CK

Figure 102 (page 191)

Active

WRITE: BC4MRS

WL + 2

t

CK + 

t

WR/

t

CK

Figure 102 (page 191)

Active

WRITEAP: BL8OTF, BL8MRS,

BC4OTF

t

WRAPDEN

WL + 4

t

CK + WR + 1

t

CK

Figure 103 (page 191)

Active

WRITEAP: BC4MRS

WL + 2

t

CK + WR + 1

t

CK

Figure 103 (page 191)

Idle

REFRESH

t

REFPDEN

1

t

CK

Figure 104 (page 192)

Power-down

REFRESH

t

XPDLL

Greater of 10

t

CK or 24ns

Figure 108 (page 194)

Idle

MODE REGISTER SET

t

MRSPDEN

t

MOD

Figure 107 (page 193)

Note:

1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-

chronous 

t

ANPD prior to CKE going LOW and remains asynchronous until 

t

ANPD +

t

XPDLL after CKE goes HIGH.

Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until 

t

CPDED has been satis-

fied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.

During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.

The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 210) for detailed ODT usage requirements in slow

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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exit mode precharge power-down. A summary of the two power-down modes is listed in 
Table 82 (page 188).

While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
remain LOW until 

t

PD (MIN) has been satisfied. The maximum time allowed for power-

down duration is 

t

PD (MAX) (9 × 

t

REFI).

The power-down states are synchronously exited when CKE is registered HIGH (with a
required NOP or DES command). CKE must be maintained HIGH until 

t

CKE has been

satisfied. A valid, executable command may be applied after power-down exit latency,

t

XP, and 

t

XPDLL have been satisfied. A summary of the power-down modes is listed be-

low.

For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-
to-power-down-entry sequence, the number of clock cycles between power-down exit
and power-down entry may not be sufficient to keep the DLL properly updated. In addi-
tion to meeting 

t

PD when the REFRESH command is used between power-down exit

and power-down entry, two other conditions must be met. First, 

t

XP must be satisfied

before issuing the REFRESH command. Second, 

t

XPDLL must be satisfied before the

next power-down may be entered. An example is shown in Figure 108 (page 194).

Table 82: Power-Down Modes

DRAM State

MR0[12]

DLL State

Power-

Down Exit

Relevant Parameters

Active (any bank open)

“Don’t Care”

On

Fast

t

XP to any other valid command

Precharged
(all banks precharged)

1

On

Fast

t

XP to any other valid command

0

Off

Slow

t

XPDLL to commands that require the DLL to be

locked (READ, RDAP, or ODT on);

t

XP to any other valid command

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Power-Down Mode

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Figure 98: Active Power-Down Entry and Exit

CK

CK#

Command

NOP

NOP

NOP

NOP

Address

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Exit power-down

mode

Don’t Care

Valid

Valid

Valid

t

CPDED

Valid

t

IS

t

IH

t

IH

t

IS

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

NOP

t

XP

t

CKE (MIN)

Indicates break
in time scale

t

PD

Figure 99: Precharge Power-Down (Fast-Exit Mode) Entry and Exit

CK

CK#

Command

NOP

NOP

NOP

NOP

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Exit power-down

mode

t

PD

Valid

t

CPDED

t

IS

t

IH

t

IS

T0

T1

T2

T3

T4

T5

Ta0

Ta1

NOP

Don’t Care

Indicates break
in time scale

t

XP

t

CKE (MIN)

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 100: Precharge Power-Down (Slow-Exit Mode) Entry and Exit

CK

CK#

Command

NOP

NOP

NOP

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Exit power-down

mode

t

PD

Valid

2

Valid

1

PRE

t

XPDLL

t

CPDED

t

IS

t

IH

t

IS

T0

T1

T2

T3

T4

Ta

Ta1

Tb

NOP

Don’t Care

Indicates break
in time scale

t

XP

t

CKE (MIN)

Notes:

1. Any valid command not requiring a locked DLL.
2. Any valid command requiring a locked DLL.

Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP)

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Ta9

Don’t Care

Transitioning Data

Ta10

Ta11

Ta12

NOP

Valid

READ/

RDAP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

CKE

t

CPDED

t

IS

t

PD

Power-down or

self refresh entry

Indicates break
in time scale

t

RDPDEN

DI

n + 3

DI

n + 1

DI

n + 2

DI

n

RL = AL + CL

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

DI

n + 6

DI

n + 7

DI

n+ 5

DI

n + 4

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 102: Power-Down Entry After WRITE

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

Tb2

Tb3

Tb4

NOP

WRITE

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

CKE

t

CPDED

Power-down or

self refresh entry

1

Don’t Care

Transitioning Data

t

WRPDEN

DI

n + 3

DI

n + 1

DI

n + 2

DI

n

t

PD

Indicates break
in time scale

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

DI

 n + 6

DI

 n + 7

DI

 n + 5

DI

 n + 4

t

IS

WL = AL + CWL

t

WR

Note:

1. CKE can go LOW 2

t

CK earlier if BC4MRS.

Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP)

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

Don’t Care

Transitioning Data

Tb2

Tb3

Tb4

NOP

WRAP

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

A10

CKE

t

PD

t

WRAPDEN

Power-down or

self refresh entry

2

Start internal

precharge

t

CPDED

t

IS

Indicates break
in time scale

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

n

DI

 n + 6

DI

 n + 7

DI

 n + 5

DI

 n + 4

DI

 n + 3

DI

 n + 2

DI

 n + 1

DI

 n

WR

1

WL = AL + CWL

Notes:

1.

t

WR is programmed through MR0[11:9] and represents 

t

WRmin (ns)/

t

CK rounded up to

the next integer 

t

CK.

2. CKE can go LOW 2

t

CK earlier if BC4MRS.

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 104: REFRESH to Power-Down Entry

CK

CK#

Command

REFRESH

NOP

NOP

NOP

NOP

Valid

CKE

t

CK

t

CH

t

CL

t

CPDED

t

REFPDEN

t

IS

T0

T1

T2

T3

Ta0

Ta1

Ta2

Tb0

t

XP (MIN)

t

RFC (MIN)

1

Don’t Care

Indicates break
in time scale

t

CKE (MIN)

t

PD

Note:

1. After CKE goes HIGH during 

t

RFC, CKE must remain HIGH until 

t

RFC is satisfied.

Figure 105: ACTIVATE to Power-Down Entry

CK

CK#

Command

Address

ACTIVE

NOP

NOP

CKE

t

CK

t

CH

t

CL

Don’t Care

t

CPDED

t

ACTPDEN

Valid

t

IS

T0

T1

T2

T3

T4

T5

T6

T7

t

PD

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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Figure 106: PRECHARGE to Power-Down Entry

CK

CK#

Command

Address

CKE

t

CK

t

CH

t

CL

Don’t Care

t

CPDED

t

PREPDEN

t

IS

T0

T1

T2

T3

T4

T5

T6

T7

t

PD

All/single

bank

PRE

NOP

NOP

Figure 107: MRS Command to Power-Down Entry

CK

CK#

CKE

t

CK

t

CH

t

CL

t

CPDED

Address

t

IS

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

t

PD

Don’t Care

Indicates break
in time scale

Valid

Command

MRS

NOP

NOP

NOP

NOP

NOP

t

MRSPDEN

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Power-Down Mode

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Figure 108: Power-Down Exit to Refresh to Power-Down Entry

CK

CK#

CKE

t

CK

t

CH

t

CL

Enter power-down

mode

Enter power-down

mode

Exit power-down

mode

t

PD

t

CPDED

t

IS

t

IH

t

IS

T0

T1

T2

T3

T4

Ta0

Ta1

Tb0

Don’t Care

Indicates break
in time scale

Command

NOP

NOP

NOP

NOP

REFRESH

NOP

NOP

t

XP

1

t

XPDLL

2

Notes:

1.

t

XP must be satisfied before issuing the command.

2.

t

XPDLL must be satisfied (referenced to the registration of power-down exit) before the

next power-down can be entered.

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

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RESET Operation

The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it
drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes
LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT
(R

TT

) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to

RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized
as though a normal power-up was executed. All counters, except refresh counters, on
the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET#
has gone LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

RESET Operation

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Figure 109: RESET Sequence

T = 10ns  (MIN)

T = 100ns (MIN)

T = 500μs (MIN)

t

XPR

t

MRD

t

MRD

t

MRD

t

MOD

t

CK

t

IOZ = 20ns

CKE

R

TT

BA[2:0]

All voltage
supplies valid
and stable

High-Z

DM

DQS

High-Z

Address

A10

CK

CK#

t

CL

Command

NOP

T0

Ta0

Don’t Care

t

CL

ODT

DQ

High-Z

Tb0

t

DLLK

MR1 with

DLL ENABLE

MRS

MRS

BA0 = H

BA1 = L
BA2 = L

BA0 = L
BA1 = L
BA2 = L

Code Code 

Code Code 

Valid

Valid

Valid

Valid

 Normal

operation

MR2

MR3

MRS

MRS

BA0 = L

BA1 = H

BA2 = L

BA0 = H
BA1 = H

BA2 = L

Code Code 

Code Code 

Tc0

Td0

RESET#

Stable and

valid clock

Valid

DRAM ready

for external

commands

T1

t

ZQinit

A10 = H

ZQCL

t

IS

Valid

System RESET

(warm boot)

ZQCAL

MR0 with

DLL RESET

Indicates break
in time scale

t

CKSRX

1

t

IS

t

IS

t

IS

Static LOW in case R

TT_Nom

 is enabled at time Ta0, otherwise static HIGH or LOW

Note:

1. The minimum time required is the longer of 10ns or 5 clocks.

4Gb: x4, x8, x16 DDR3L SDRAM

RESET Operation

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On-Die Termination (ODT)

On-die termination (ODT) is a feature that enables the DRAM to enable/disable and
turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8
configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is ap-
plied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 con-
figuration.

ODT is designed to improve signal integrity of the memory channel by enabling the
DRAM controller to independently turn on/off the DRAM’s internal termination resist-
ance for any grouping of DRAM devices. ODT is not supported during DLL disable
mode (simple functional representation shown below). The switch is enabled by the in-
ternal ODT control logic, which uses the external ODT ball and other control informa-
tion.

Figure 110: On-Die Termination

ODT

V

DDQ

/2

R

TT

Switch

DQ, DQS, DQS#, 
DM, TDQS, TDQS#

To other
circuitry
such as
RCV, 
. . . 

Functional Representation of ODT

The value of R

TT

 (ODT termination resistance value) is determined by the settings of

several mode register bits (see Table 88 (page 201)). The ODT ball is ignored while in
self refresh mode (must be turned off prior to self refresh entry) or if mode registers
MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and
dynamic ODT modes and either of these can function in synchronous or asynchronous
mode (when the DLL is off during precharge power-down or when the DLL is synchro-
nizing). Nominal ODT is the base termination and is used in any allowable ODT state.
Dynamic ODT is applied only during writes and provides OTF switching from no R

TT

 or

R

TT,nom

 to R

TT(WR)

.

The actual effective termination, R

TT(EFF)

, may be different from R

TT

 targeted due to

nonlinearity of the termination. For R

TT(EFF)

 values and calculations, see Table 33 (page

61).

Nominal ODT

ODT (NOM) is the base termination resistance for each applicable ball; it is enabled or
disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or
off via the ODT ball.

4Gb: x4, x8, x16 DDR3L SDRAM

On-Die Termination (ODT)

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Table 83: Truth Table – ODT (Nominal)

Note 1 applies to the entire table

MR1[9, 6, 2]

ODT Pin

DRAM Termination State

DRAM State

Notes

000

0

R

TT,nom

 disabled, ODT off

Any valid

2

000

1

R

TT,nom

 disabled, ODT on

Any valid except self refresh, read

3

000–101

0

R

TT,nom

 enabled, ODT off

Any valid

2

000–101

1

R

TT,nom

 enabled, ODT on

Any valid except self refresh, read

3

110 and 111

X

R

TT,nom

 reserved, ODT on or off

Illegal

 

Notes:

1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 199) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal

for it to be off during writes.

3. ODT must be disabled during reads. The R

TT,nom

 value is restricted during writes. Dynam-

ic ODT is applicable if enabled.

Nominal ODT resistance R

TT,nom

 is defined by MR1[9, 6, 2], as shown in Mode Register 1

(MR1) Definition. The R

TT,nom

 termination value applies to the output pins previously

mentioned. DDR3 SDRAM supports multiple R

TT,nom

 values based on RZQ/

n

 where 

n

can be 2, 4, 6, 8, or 12 and RZQ is 240

ȍ

. R

TT,nom

 termination is allowed any time after the

DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.

Write accesses use R

TT,nom

 if dynamic ODT (R

TT(WR)

) is disabled. If R

TT,nom

 is used dur-

ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 87 (page 200)). ODT
timings are summarized in Table 84 (page 198), as well as listed in the Electrical Char-
acteristics and AC Operating Conditions table.

Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 205).

Table 84: ODT Parameters

Symbol

Description

Begins at

Defined to

Definition for All

DDR3L Speed Bins

Unit

ODTLon

ODT synchronous turn-on delay

ODT registered HIGH

R

TT(ON)

 ±

t

AON

CWL + AL - 2

t

CK

ODTLoff

ODT synchronous turn-off delay

ODT registered HIGH

R

TT(OFF)

 ±

t

AOF

CWL + AL - 2

t

CK

t

AONPD

ODT asynchronous turn-on delay

ODT registered HIGH

R

TT(ON)

2–8.5

ns

t

AOFPD

ODT asynchronous turn-off delay

ODT registered HIGH

R

TT(OFF)

2–8.5

ns

ODTH4

ODT minimum HIGH time after ODT

assertion or write (BC4)

ODT registered HIGH

or write registration

with ODT HIGH

ODT registered

LOW

4

t

CK

t

CK

ODTH8

ODT minimum HIGH time after

write (BL8)

Write registration

with ODT HIGH

ODT registered

LOW

6

t

CK

t

CK

t

AON

ODT turn-on relative to ODTLon

completion

Completion of

ODTLon

R

TT(ON)

See Electrical Charac-

teristics and AC Oper-

ating Conditions table

ps

t

AOF

ODT turn-off relative to ODTLoff

completion

Completion of

ODTLoff

R

TT(OFF)

0.5

t

CK ± 0.2

t

CK

t

CK

4Gb: x4, x8, x16 DDR3L SDRAM

On-Die Termination (ODT)

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Dynamic ODT

In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT R

TT(WR)

) enabled, the DRAM switches from nominal ODT R

TT,nom

) to dy-

namic ODT R

TT(WR)

) when beginning a WRITE burst and subsequently switches back to

nominal ODT R

TT,nom

) at the completion of the WRITE burst. This requirement is sup-

ported by the dynamic ODT feature, as described below.

Dynamic ODT Special Use Case

When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special use case: the ODT ball can be wired high (via a current limiting resistor prefer-
red) by having R

TT,nom

 disabled via MR1 and R

TT(WR)

 enabled via MR2. This will allow

the ODT signal not to have to be routed yet the DRAM can provide ODT coverage dur-
ing write accesses.

When enabling this special use case, some standard ODT spec conditions may be viola-
ted: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not
LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this
would appear to be a problem since R

TT(WR)

 can not be used (should be disabled) and

R

TT(NOM)

 should be used. For Write leveling during this special use case, with the DLL

locked, then R

TT(NOM)

 maybe enabled when entering Write Leveling mode and disabled

when exiting Write Leveling mode. More so, R

TT(NOM)

 must be enabled when enabling

Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via
same MR1 load if R

TT(NOM)

 is to be used.

ODT will turn-on within a delay of ODTLon + 

t

AON + 

t

MOD + 1CK (enabling via MR1)

or turn-off within a delay of ODTLoff + 

t

AOF + 

t

MOD + 1CK. As seen in the table below,

between the Load Mode of MR1 and the previously specified delay, the value of ODT is
uncertain. this means the DQ ODT termination could turn-on and then turn-off again
during the period of stated uncertainty.

Table 85: Write Leveling with Dynamic ODT Special Case

Begin R

TT,nom

 Uncertainty

End R

TT,nom

 Uncertainty

I/Os

R

TT,nom

 Final State

MR1 load mode command:

Enable Write Leveling and R

TT(NOM)

ODTLon + 

t

AON + 

t

MOD + 1CK

DQS, DQS#

Drive R

TT,nom

 value

DQs

No R

TT,nom

MR1 load mode command:

Disable Write Leveling and R

TT(NOM)

ODTLoff + 

t

AOFF + 

t

MOD + 1CK

DQS, DQS#

No R

TT,nom

DQs

No R

TT,nom

Functional Description

The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic
ODT is not supported during DLL disable mode so R

TT(WR)

 must be disabled. The dy-

namic ODT function is described below:

• Two R

TT

 values are available—R

TT,nom

 and R

TT(WR)

.

– The value for R

TT,nom

 is preselected via MR1[9, 6, 2].

– The value for R

TT(WR)

 is preselected via MR2[10, 9].

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Dynamic ODT

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• During DRAM operation without READ or WRITE commands, the termination is con-

trolled.

– Nominal termination strength R

TT,nom

 is used.

– Termination on/off timing is controlled via the ODT ball and latencies ODTLon and

ODTLoff.

• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,

and if dynamic ODT is enabled, the ODT termination is controlled.

– A latency of ODTLcnw after the WRITE command: termination strength R

TT,nom

switches to R

TT(WR)

– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)

after the WRITE command: termination strength R

TT(WR)

 switches back to R

TT,nom

.

– On/off termination timing is controlled via the ODT ball and determined by ODT-

Lon, ODTLoff, ODTH4, and ODTH8.

– During the 

t

ADC transition window, the value of R

TT

 is undefined.

ODT is constrained during writes and when dynamic ODT is enabled (see the table be-
low, Dynamic ODT Specific Parameters). ODT timings listed in the ODT Parameters ta-
ble in On-Die Termination (ODT) also apply to dynamic ODT mode.

Table 86: Dynamic ODT Specific Parameters

Symbol

Description

Begins at

Defined to

Definition for All

DDR3L Speed

Bins

Unit

ODTLcnw

Change from R

TT,nom

 to

R

TT(WR)

Write registration

R

TT

 switched from R

TT,nom

to R

TT(WR)

WL - 2

t

CK

ODTLcwn4

Change from R

TT(WR)

 to

R

TT,nom

 (BC4)

Write registration

R

TT

 switched from R

TT(WR)

to R

TT,nom

4

t

CK + ODTL off

t

CK

ODTLcwn8

Change from R

TT(WR)

 to

R

TT,nom

 (BL8)

Write registration

R

TT

 switched from R

TT(WR)

to R

TT,nom

6

t

CK + ODTL off

t

CK

t

ADC

R

TT

 change skew

ODTLcnw completed

R

TT

 transition complete

0.5

t

CK ± 0.2

t

CK

t

CK

Table 87: Mode Registers for R

TT,nom

MR1 (R

TT,nom

)

R

TT,nom

 (RZQ)

R

TT,nom

 (Ohm)

R

TT,nom

 Mode Restriction

M9

M6

M2

0

0

0

Off

Off

n/a

0

0

1

RZQ/4

60

Self refresh

0

1

0

RZQ/2

120

0

1

1

RZQ/6

40

1

0

0

RZQ/12

20

Self refresh, write

1

0

1

RZQ/8

30

1

1

0

Reserved

Reserved

n/a

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Dynamic ODT

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Table 87: Mode Registers for R

TT,nom

 (Continued)

MR1 (R

TT,nom

)

R

TT,nom

 (RZQ)

R

TT,nom

 (Ohm)

R

TT,nom

 Mode Restriction

M9

M6

M2

1

1

1

Reserved

Reserved

n/a

Note:

1. RZQ = 240

˖

. If R

TT,nom

 is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.

Table 88: Mode Registers for R

TT(WR)

MR2 (R

TT(WR)

)

R

TT(WR)

 (RZQ)

R

TT(WR)

 (Ohm)

M10

M9

0

0

Dynamic ODT off: WRITE does not affect R

TT,nom

0

1

RZQ/4

60

1

0

RZQ/2

120

1

1

Reserved

Reserved

Table 89: Timing Diagrams for Dynamic ODT

Figure and Page

Title

Figure 111 (page 202)

Dynamic ODT: ODT Asserted Before and After the WRITE, BC4

Figure 112 (page 202)

Dynamic ODT: Without WRITE Command

Figure 113 (page 203)

Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8

Figure 114 (page 204)

Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4

Figure 115 (page 204)

Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Figure 111: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLon

ODTLcwn4

ODTLcnw

WL

ODTLoff

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

Command

Address

R

TT

ODT

DQ 

DQS, DQS#

Valid

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Don’t Care

Transitioning

R

TT(WR)

R

TT,nom

R

TT,nom

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

ODTH4

ODTH4

t

AON (MIN)

t

ADC (MIN)

t

ADC (MIN)

t

AOF (MIN)

t

AON (MAX)

t

ADC (MAX)

t

ADC (MAX)

t

AOF (MAX)

Notes:

1. Via MRS or OTF. AL = 0, CWL = 5. R

TT,nom

 and R

TT(WR)

 are enabled.

2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,

ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).

Figure 112: Dynamic ODT: Without WRITE Command

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLoff 

T10

T11

CK

CK#

R

TT

Don’t Care

Transitioning

Command

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Address

DQS, DQS#

DQ

ODTH4

ODTLon

t

AON (MAX)

t

AON (MIN)

t

AOF (MIN)

t

AOF (MAX)

ODT

R

TT,nom

Notes:

1. AL = 0, CWL = 5. R

TT,nom

 is enabled and R

TT(WR)

 is either enabled or disabled.

2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT reg-

istered LOW at T5 is also legal.

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLcwn8

ODTLon

ODTLcnw

WL

t

AOF (MAX)

T10

T11

CK

CK#

Address

R

TT

ODT

DQ

DQS, DQS#

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

 b + 4

Valid

Don’t Care

Transitioning

Command

WRS8

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

R

TT(WR)

ODTH8

ODTLoff

t

ADC (MAX)

t

AON (MIN)

t

AOF (MIN)

Notes:

1. Via MRS or OTF; AL = 0, CWL = 5. If R

TT,nom

 can be either enabled or disabled, ODT can be HIGH. R

TT(WR)

 is enabled.

2. In this example, ODTH8 = 6 is satisfied exactly.

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLon

ODTLcnw

WL

T10

T11

CK

CK#

ODTLcwn4

DQS, DQS#

Address

Valid

Don’t Care

Transitioning

ODTLoff 

Command

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

DQ

DI

n + 3

DI

n + 2

DI

n + 1

DI

n

t

ADC (MIN)

t

AOF (MIN)

t

AOF (MAX)

t

ADC (MAX)

t

ADC (MAX)

t

AON (MIN)

ODTH4

ODT

R

TT

R

TT(WR)

R

TT,nom

Notes:

1. Via MRS or OTF. AL = 0, CWL = 5. R

TT,nom

 and R

TT(WR)

 are enabled.

2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,

ODTH4 is satisfied. ODT registered LOW at T5 is also legal.

Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

ODTLon

ODTLcnw

WL

T10

T11

CK

CK#

ODTLcwn4

DQS, DQS#

Address

Valid

Command

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Don’t Care

Transitioning

DQ

DI

n

DI

n + 3

DI

n + 2

DI

n + 1

ODTH4

t

ADC (MAX)

t

AON (MIN)

t

AOF (MIN)

t

AOF (MAX)

ODTLoff 

R

TT

R

TT(WR)

ODT

Notes:

1. Via MRS or OTF. AL = 0, CWL = 5. R

TT,nom

 can be either enabled or disabled. If disabled,

ODT can remain HIGH. R

TT(WR)

 is enabled.

2. In this example ODTH4 = 4 is satisfied exactly.

4Gb: x4, x8, x16 DDR3L SDRAM

Dynamic ODT

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Synchronous ODT Mode

Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either R

TT,nom

 or R

TT(WR)

 is enabled. Based on the power-down definition, these

modes are:

• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled by MR0[12] during precharge power-

down

ODT Latency and Posted ODT

In synchronous ODT mode, R

TT

 turns on ODTLon clock cycles after ODT is sampled

HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by 

t

AON and 

t

AOF around

each clock edge (see Table 90 (page 206)). The ODT latency is tied to the WRITE latency
(WL) by ODTLon = WL - 2 and ODTLoff = WL - 2.

Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL),
the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal.
The device’s internal ODT signal is delayed a number of clock cycles defined by the AL
relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL +
AL - 2.

Timing Parameters

Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff,
ODTH4, ODTH8, 

t

AON, and 

t

AOF. The minimum R

TT

 turn-on time (

t

AON [MIN]) is the

point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi-
mum R

TT

 turn-on time (

t

AON [MAX]) is the point at which ODT resistance is fully on.

Both are measured relative to ODTLon. The minimum R

TT

 turn-off time (

t

AOF [MIN]) is

the point at which the device starts to turn off ODT resistance. The maximum R

TT

 turn

off time (

t

AOF [MAX]) is the point at which ODT has reached High-Z. Both are measured

from ODTLoff.

When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com-
mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 117 (page 207)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Synchronous ODT Mode

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Table 90: Synchronous ODT Parameters

Symbol

Description

Begins at

Defined to

Definition for All

DDR3L Speed Bins

Unit

ODTLon

ODT synchronous turn-on delay

ODT registered HIGH

R

TT(ON)

 ±

t

AON

CWL + AL - 2

t

CK

ODTLoff

ODT synchronous turn-off delay

ODT registered HIGH

R

TT(OFF)

 ±

t

AOF

CWL +AL - 2

t

CK

ODTH4

ODT minimum HIGH time after ODT
assertion or WRITE (BC4)

ODT registered HIGH or write regis-
tration with ODT HIGH

ODT registered LOW

4

t

CK

t

CK

ODTH8

ODT minimum HIGH time after WRITE
(BL8)

Write registration with ODT HIGH

ODT registered LOW

6

t

CK

t

CK

t

AON

ODT turn-on relative to ODTLon
completion

Completion of ODTLon

R

TT(ON)

See Electrical Charac-

teristics and AC Oper-

ating Conditions ta-

ble

ps

t

AOF

ODT turn-off relative to ODTLoff
completion

Completion of ODTLoff

R

TT(OFF)

0.5

t

CK ± 0.2

t

CK

t

CK

Figure 116: Synchronous ODT

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CWL - 2

AL = 3

AL = 3

t

AON (MAX)

t

AOF (MAX)

T10

T11

T12

T13

T14

T15

CK

CK#

R

TT

ODT

Don’t Care

Transitioning

R

TT,nom

CKE

t

AOF (MIN)

ODTLoff = CWL + AL - 2

ODTLon = CWL + AL - 2

ODTH4 (MIN)

t

AON (MIN)

Note:

1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. R

TT,nom

 is enabled.

4Gb: x4, x8, x16 DDR3L SDRAM

Synchr

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Figure 117: Synchronous ODT (BC4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

AOF (MAX)

t

AOF (MIN)

t

AON (MAX)

t

AOF (MAX)

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

R

TT

CKE

NOP

WRS4

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Command

Don’t Care

Transitioning

t

AON (MIN)

R

TT,nom

ODTLoff = WL - 2

ODTH4 (MIN) 

ODTH4 

ODTLoff = WL - 2

ODTLon = WL - 2

t

AON (MIN)

t

AON (MAX)

ODTH4 

ODTLon = WL - 2

t

AOF (MIN)

ODT

R

TT,nom

Notes:

1. WL = 7. R

TT,nom

 is enabled. R

TT(WR)

 is disabled.

2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the

WRITE command with ODT HIGH to ODT registered LOW.

5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must

also be satisfied from the registration of the WRITE command at T7.

4Gb: x4, x8, x16 DDR3L SDRAM

Synchr

onous ODT Mode

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ODT Off During READs

Because the device cannot terminate and drive at the same time, R

TT

 must be disabled

at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if
either R

TT,nom

 or R

TT(WR)

 is enabled). R

TT

 may not be enabled until the end of the post-

amble, as shown in the following example.

Note: 

ODT may be disabled earlier and enabled later than shown in Figure 118

(page 209).

4Gb: x4, x8, x16 DDR3L SDRAM

Synchronous ODT Mode

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Figure 118: ODT During READs

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

Valid

Address

DI

b + 3

DI

b + 2

DI

b + 1

DI

b

DI

b + 7

DI

b + 6

DI

b + 5

DI

b + 4

DQ

DQS, DQS#

Don’t Care

Transitioning

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

READ

ODTLon = CWL + AL - 2

ODT

t

AON (MAX)

RL = AL + CL

ODTLoff = CWL + AL - 2

t

AOF (MIN)

R

TT

R

TT,nom

R

TT,nom

t

AOF (MAX)

Note:

1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL

+ CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8. R

TT,nom

 is enabled. R

TT(WR)

 is a “Don’t

Care.”

4Gb: x4, x8, x16 DDR3L SDRAM

Synchr

onous ODT Mode

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Asynchronous ODT Mode

Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when
either R

TT,nom

 or R

TT(WR)

 is enabled; however, the DLL is temporarily turned off in pre-

charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous-
ly when the DLL is synchronizing after being reset. See Power-Down Mode (page 187)
for definition and guidance over power-down details.

In asynchronous ODT timing mode, the internal ODT command is not delayed by AL
relative to the external ODT command. In asynchronous ODT mode, ODT controls R

TT

by analog time. The timing parameters 

t

AONPD and 

t

AOFPD replace ODTLon/

t

AON

and ODTLoff/

t

AOF, respectively, when ODT operates asynchronously.

The minimum R

TT

 turn-on time (

t

AONPD [MIN]) is the point at which the device termi-

nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum R

TT

 turn-

on time (

t

AONPD [MAX]) is the point at which ODT resistance is fully on. 

t

AONPD

(MIN) and 

t

AONPD (MAX) are measured from ODT being sampled HIGH.

The minimum R

TT

 turn-off time (

t

AOFPD [MIN]) is the point at which the device termi-

nation circuit starts to turn off ODT resistance. Maximum R

TT

 turn-off time (

t

AOFPD

[MAX]) is the point at which ODT has reached High-Z. 

t

AOFPD (MIN) and 

t

AOFPD

(MAX) are measured from ODT being sampled LOW.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous ODT Mode

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Figure 119: Asynchronous ODT Timing with Fast ODT Transition

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

AONPD (MAX)

t

AOFPD (MAX)

T10

T11

T12

T13

T14

T15

T17

T16

CK

CK#

R

TT

ODT

R

TT,nom

Don’t Care

Transitioning

CKE

t

IH

t

IS

t

IH

t

IS

t

AOFPD (MIN)

t

AONPD (MIN)

Note:

1. AL is ignored.

Table 91: Asynchronous ODT Timing Parameters for All Speed Bins

Symbol

Description

Min

Max

Unit

t

AONPD

Asynchronous R

TT

 turn-on delay (power-down with DLL off)

2

8.5

ns

t

AOFPD

Asynchronous R

TT

 turn-off delay (power-down with DLL off)

2

8.5

ns

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous ODT Mode

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Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)

There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period oc-
curs if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins 

t

ANPD prior to CKE first being registered LOW,

and ends when CKE is first registered LOW. 

t

ANPD is equal to the greater of ODTLoff +

1

t

CK or ODTLon + 1

t

CK. If a REFRESH command has been issued, and it is in progress

when CKE goes LOW, power-down entry ends 

t

RFC after the REFRESH command, rath-

er than when CKE is first registered LOW. Power-down entry then becomes the greater
of 

t

ANPD and 

t

RFC - REFRESH command to CKE registered LOW.

ODT assertion during power-down entry results in an R

TT

 change as early as the lesser

of 

t

AONPD (MIN) and ODTLon × 

t

CK + 

t

AON (MIN), or as late as the greater of 

t

AONPD

(MAX) and ODTLon × 

t

CK + 

t

AON (MAX). ODT de-assertion during power-down entry

can result in an R

TT

 change as early as the lesser of 

t

AOFPD (MIN) and ODTLoff × 

t

CK +

t

AOF (MIN), or as late as the greater of 

t

AOFPD (MAX) and ODTLoff × 

t

CK + 

t

AOF (MAX). 

Table 92 (page 213) summarizes these parameters.

If AL has a large value, the uncertainty of the state of R

TT

 becomes quite large. This is

because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL. 
Figure 120 (page 213) shows three different cases:

• ODT_A: Synchronous behavior before 

t

ANPD.

• ODT_B: ODT state changes during the transition period with 

t

AONPD (MIN) <

ODTLon × 

t

CK + 

t

AON (MIN) and 

t

AONPD (MAX) > ODTLon × 

t

CK + 

t

AON (MAX).

• ODT_C: ODT state changes after the transition period with asynchronous behavior.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous ODT Mode

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Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period

Description

Min

Max

Power-down entry transition period
(power-down entry)

Greater of: 

t

ANPD or 

t

RFC - refresh to CKE LOW

Power-down exit transition period
(power-down exit)

t

ANPD + 

t

XPDLL

ODT to R

TT

 turn-on delay

(ODTLon = WL - 2)

Lesser of: 

t

AONPD (MIN) (2ns) or

ODTLon × 

t

CK + 

t

AON (MIN)

Greater of: 

t

AONPD (MAX) (8.5ns) or

ODTLon × 

t

CK + 

t

AON (MAX)

ODT to R

TT

 turn-off delay

(ODTLoff = WL - 2)

Lesser of: 

t

AOFPD (MIN) (2ns) or

ODTLoff × 

t

CK + 

t

AOF (MIN)

Greater of: 

t

AOFPD (MAX) (8.5ns) or

ODTLoff × 

t

CK + 

t

AOF (MAX)

t

ANPD

WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)

Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

AOFPD (MAX)

ODTLoff

T10

T11

T12

T13

Ta0

Ta1

Ta3

Ta2

CK

CK#

DRAM R

TT

 B 

asynchronous 

or synchronous

R

TT,nom

DRAM R

TT

 C

asynchronous

R

TT,nom

Don’t Care

Transitioning

CKE

NOP

NOP

NOP

NOP

NOP

Command

NOP

REF

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

PDE transition period

Indicates break
in time scale

ODTLoff + 

t

AOFPD (MIN)

t

AOFPD (MAX)

t

AOFPD (MIN)

ODTLoff + 

t

AOFPD (MAX)

t

AOFPD (MIN)

t

ANPD

t

AOF (MIN)

t

AOF (MAX)

DRAM R

TT

 A 

synchronous

R

TT,nom

ODT A 

synchronous

ODT C 

asynchronous

ODT B 

asynchronous 

or synchronous

t

RFC (MIN)

Note:

1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous ODT Mode

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Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins

t

ANPD prior to CKE first being registered HIGH, and ends 

t

XPDLL after CKE is first reg-

istered HIGH. 

t

ANPD is equal to the greater of ODTLoff + 1

t

CK or ODTLon + 1

t

CK. The

transition period is 

t

ANPD + 

t

XPDLL.

ODT assertion during power-down exit results in an R

TT

 change as early as the lesser of

t

AONPD (MIN) and ODTLon × 

t

CK + 

t

AON (MIN), or as late as the greater of 

t

AONPD

(MAX) and ODTLon × 

t

CK + 

t

AON (MAX). ODT de-assertion during power-down exit

may result in an R

TT

 change as early as the lesser of 

t

AOFPD (MIN) and ODTLoff × 

t

CK +

t

AOF (MIN), or as late as the greater of 

t

AOFPD (MAX) and ODTLoff × 

t

CK + 

t

AOF (MAX). 

Table 92 (page 213) summarizes these parameters.

If AL has a large value, the uncertainty of the R

TT

 state becomes quite large. This is be-

cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL.  Figure
121 (page 215) sho
ws three different cases:

• ODT C: Asynchronous behavior before 

t

ANPD.

• ODT B: ODT state changes during the transition period, with 

t

AOFPD (MIN) < ODTL-

off × 

t

CK + 

t

AOF (MIN), and ODTLoff × 

t

CK + 

t

AOF (MAX) > 

t

AOFPD (MAX).

• ODT A: ODT state changes after the transition period with synchronous response.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

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Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb1

Tb2

Tc0

Tc1

Td0

Td1

Tc2

CK

CK#

Don’t Care

Transitioning

ODT C

synchronous

NOP

NOP

NOP

COMMAND

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

R

TT

 B

asynchronous

or synchronous

DRAM R

TT

 A

asynchronous

DRAM R

TT

 C

synchronous

R

TT,nom

NOP

NOP

ODT B

asynchronous

or synchronous

CKE

t

AOF (MIN)

R

TT,nom

Indicates break
in time scale

ODTLoff + 

t

AOF (MIN)

t

AOFPD (MAX)

ODTLoff + 

t

AOF (MAX)

t

XPDLL

t

AOF (MAX)

ODTLoff

ODT A

asynchronous

PDX transition period

t

AOFPD (MIN)

t

AOFPD (MAX)

R

TT,nom

t

ANPD

t

AOFPD (MIN)

Note:

1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous to Synchr

onous ODT Mode T

ransition (Power

-

Down Exit)

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Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)

If the time in the precharge power-down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods overlap. When
overlap occurs, the response of the DRAM’s R

TT

 to a change in the ODT state can be

synchronous or asynchronous from the start of the power-down entry transition period
to the end of the power-down exit transition period, even if the entry period ends later
than the exit period.

If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the re-
sponse of the DRAM’s R

TT

 to a change in the ODT state may be synchronous or asyn-

chronous from the start of power-down exit transition period to the end of the power-
down entry transition period.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

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Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Ta0

Ta1

Ta2

Ta3

Ta4

CK

CK#

CKE

Command

Don’t Care

Transitioning

t

XPDLL

t

RFC (MIN)

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

REF

NOP

NOP

NOP

NOP

PDE transition period

PDX transition period

Indicates break
in time scale

t

ANPD

Short CKE low transition period (R

TT

 change asynchronous or synchronous)

t

ANPD

Note:

1. AL = 0, WL = 5, 

t

ANPD = 4.

Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK

CK#

Command

Don’t Care

Transitioning

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

ANPD

t

XPDLL

Indicates break
in time scale

Ta0

Ta1

Ta2

Ta3

Ta4

CKE

t

ANPD

Short CKE HIGH transition period (R

TT

 change asynchronous or synchonous)

Note:

1. AL = 0, WL = 5, 

t

ANPD = 4.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchr

onous to Synchr

onous ODT Mode T

ransition (Power

-

Down Exit)

09005aef85af8fa8

4Gb_DDR3L.pdf - Rev

. R 09/18 EN

217

Micron T

echnology

, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron T

echnology

, Inc. All rights reserved.

MT41K256M16TW-html.html

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

4Gb: x4, x8, x16 DDR3L SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN

218

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2017 Micron Technology, Inc. All rights reserved.